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UPSTREAM: usb: dwc3: Increase DWC3 controller halt timeout
Since EP0 transactions need to be completed before the controller halt
sequence is finished, this may take some time depending on the host and the
enabled functions. Increase the controller halt timeout, so that we give
the controller sufficient time to handle EP0 transfers.
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Link: https://lore.kernel.org/r/20220901193625.8727-4-quic_wcheng@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 461ee46750)
Bug: 263189538
Change-Id: Idb8998c4ae1d346a63043f40a3915a8a02601982
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
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@@ -2434,7 +2434,7 @@ static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
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static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
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{
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u32 reg;
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u32 timeout = 500;
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u32 timeout = 2000;
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if (pm_runtime_suspended(dwc->dev))
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return 0;
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@@ -2467,6 +2467,7 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
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dwc3_gadget_dctl_write_safe(dwc, reg);
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do {
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usleep_range(1000, 2000);
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reg = dwc3_readl(dwc->regs, DWC3_DSTS);
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reg &= DWC3_DSTS_DEVCTRLHLT;
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} while (--timeout && !(!is_on ^ !reg));
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