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drm/mipi-dbi: align max_chunk to 2 in spi_transfer

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[ Upstream commit 435c249008 ]

In __spi_validate, there's a validation that no partial transfers
are accepted (xfer->len % w_size must be zero). When
max_chunk is not a multiple of bpw (e.g. max_chunk = 65535,
bpw = 16), the transfer will be rejected.

This patch aligns max_chunk to 2 bytes (the maximum value of bpw is 16),
so that no partial transfer will occur.

Fixes: d23d4d4dac ("drm/tinydrm: Move tinydrm_spi_transfer()")

Signed-off-by: Yunhao Tian <t123yh.xyz@gmail.com>
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220510030219.2486687-1-t123yh.xyz@gmail.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Yunhao Tian
2022-05-10 11:02:19 +08:00
committed by Greg Kroah-Hartman
parent a2c45f8c3d
commit 648d3c8714
1 changed files with 7 additions and 0 deletions
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7
drivers/gpu/drm/drm_mipi_dbi.c
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@@ -1137,6 +1137,13 @@ int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
size_t chunk;
int ret;
/* In __spi_validate, there's a validation that no partial transfers
* are accepted (xfer->len % w_size must be zero).
* Here we align max_chunk to multiple of 2 (16bits),
* to prevent transfers from being rejected.
*/
max_chunk = ALIGN_DOWN(max_chunk, 2);
spi_message_init_with_transfers(&m, &tr, 1);
while (len) {