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crypto: inside-secure - add support for PCI based FPGA development board

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This patch adds support for a PCIE development board with FPGA from Xilinx,
to facilitate pre-silicon driver development by both Inside Secure and its
IP customers. Since Inside Secure neither produces nor has access to actual
silicon, this is required functionality to allow us to contribute.

Signed-off-by: Pascal van Leeuwen <pvanleeuwen@verimatrix.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Pascal van Leeuwen
2019-08-19 16:40:25 +02:00
committed by Herbert Xu
parent 70e39e2259
commit 625f269a5a
3 changed files with 431 additions and 193 deletions
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591
drivers/crypto/inside-secure/safexcel.c
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File diff suppressed because it is too large Load Diff

30
drivers/crypto/inside-secure/safexcel.h
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@@ -38,6 +38,27 @@
char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \
struct type##_request *name = (void *)__##name##_desc
/* Xilinx dev board base offsets */
#define EIP197_XLX_GPIO_BASE 0x200000
#define EIP197_XLX_IRQ_BLOCK_ID_ADDR 0x2000
#define EIP197_XLX_IRQ_BLOCK_ID_VALUE 0x1fc2
#define EIP197_XLX_USER_INT_ENB_MSK 0x2004
#define EIP197_XLX_USER_INT_ENB_SET 0x2008
#define EIP197_XLX_USER_INT_ENB_CLEAR 0x200c
#define EIP197_XLX_USER_INT_BLOCK 0x2040
#define EIP197_XLX_USER_INT_PEND 0x2048
#define EIP197_XLX_USER_VECT_LUT0_ADDR 0x2080
#define EIP197_XLX_USER_VECT_LUT0_IDENT 0x03020100
#define EIP197_XLX_USER_VECT_LUT1_ADDR 0x2084
#define EIP197_XLX_USER_VECT_LUT1_IDENT 0x07060504
#define EIP197_XLX_USER_VECT_LUT2_ADDR 0x2088
#define EIP197_XLX_USER_VECT_LUT2_IDENT 0x0b0a0908
#define EIP197_XLX_USER_VECT_LUT3_ADDR 0x208c
#define EIP197_XLX_USER_VECT_LUT3_IDENT 0x0f0e0d0c
/* Helper defines for probe function */
#define EIP197_IRQ_NUMBER(i, is_pci) (i + is_pci)
/* Register base offsets */
#define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic)
#define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g)
@@ -554,10 +575,13 @@ struct safexcel_ring {
struct crypto_async_request *backlog;
};
/* EIP integration context flags */
enum safexcel_eip_version {
EIP97IES = BIT(0),
EIP197B = BIT(1),
EIP197D = BIT(2),
/* Platform (EIP integration context) specifier */
EIP97IES_MRVL,
EIP197B_MRVL,
EIP197D_MRVL,
EIP197_DEVBRD
};
struct safexcel_register_offsets {

3
drivers/crypto/inside-secure/safexcel_ring.c
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@@ -145,7 +145,8 @@ struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *pr
(lower_32_bits(context) & GENMASK(31, 2)) >> 2;
cdesc->control_data.context_hi = upper_32_bits(context);
if (priv->version == EIP197B || priv->version == EIP197D)
if (priv->version == EIP197B_MRVL ||
priv->version == EIP197D_MRVL)
cdesc->control_data.options |= EIP197_OPTION_RC_AUTO;
/* TODO: large xform HMAC with SHA-384/512 uses refresh = 3 */