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mailbox: mediatek: Add Mediatek CMDQ driver

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This patch is first version of Mediatek Command Queue(CMDQ) driver. The
CMDQ is used to help write registers with critical time limitation,
such as updating display configuration during the vblank. It controls
Global Command Engine (GCE) hardware to achieve this requirement.
Currently, CMDQ only supports display related hardwares, but we expect
it can be extended to other hardwares for future requirements.

Signed-off-by: Houlong Wei <houlong.wei@mediatek.com>
Signed-off-by: HS Liao <hs.liao@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Houlong Wei
2018-07-25 09:26:40 +08:00
committed by Jassi Brar
parent 1c82407aa3
commit 623a6143a8
4 changed files with 658 additions and 0 deletions
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10
drivers/mailbox/Kconfig
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@@ -189,4 +189,14 @@ config STM32_IPCC
Mailbox implementation for STMicroelectonics STM32 family chips
with hardware for Inter-Processor Communication Controller (IPCC)
between processors. Say Y here if you want to have this support.
config MTK_CMDQ_MBOX
tristate "MediaTek CMDQ Mailbox Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
select MTK_INFRACFG
help
Say yes here to add support for the MediaTek Command Queue (CMDQ)
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
endif

2
drivers/mailbox/Makefile
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@@ -40,3 +40,5 @@ obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o

569
drivers/mailbox/mtk-cmdq-mailbox.c Normal file
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File diff suppressed because it is too large Load Diff

77
include/linux/mailbox/mtk-cmdq-mailbox.h Normal file
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@@ -0,0 +1,77 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018 MediaTek Inc.
*
*/
#ifndef __MTK_CMDQ_MAILBOX_H__
#define __MTK_CMDQ_MAILBOX_H__
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#define CMDQ_INST_SIZE 8 /* instruction is 64-bit */
#define CMDQ_SUBSYS_SHIFT 16
#define CMDQ_OP_CODE_SHIFT 24
#define CMDQ_JUMP_PASS CMDQ_INST_SIZE
#define CMDQ_WFE_UPDATE BIT(31)
#define CMDQ_WFE_WAIT BIT(15)
#define CMDQ_WFE_WAIT_VALUE 0x1
/*
* CMDQ_CODE_MASK:
* set write mask
* format: op mask
* CMDQ_CODE_WRITE:
* write value into target register
* format: op subsys address value
* CMDQ_CODE_JUMP:
* jump by offset
* format: op offset
* CMDQ_CODE_WFE:
* wait for event and clear
* it is just clear if no wait
* format: [wait] op event update:1 to_wait:1 wait:1
* [clear] op event update:1 to_wait:0 wait:0
* CMDQ_CODE_EOC:
* end of command
* format: op irq_flag
*/
enum cmdq_code {
CMDQ_CODE_MASK = 0x02,
CMDQ_CODE_WRITE = 0x04,
CMDQ_CODE_JUMP = 0x10,
CMDQ_CODE_WFE = 0x20,
CMDQ_CODE_EOC = 0x40,
};
enum cmdq_cb_status {
CMDQ_CB_NORMAL = 0,
CMDQ_CB_ERROR
};
struct cmdq_cb_data {
enum cmdq_cb_status sta;
void *data;
};
typedef void (*cmdq_async_flush_cb)(struct cmdq_cb_data data);
struct cmdq_task_cb {
cmdq_async_flush_cb cb;
void *data;
};
struct cmdq_pkt {
void *va_base;
dma_addr_t pa_base;
size_t cmd_buf_size; /* command occupied size */
size_t buf_size; /* real buffer size */
struct cmdq_task_cb cb;
struct cmdq_task_cb async_cb;
void *cl;
};
#endif /* __MTK_CMDQ_MAILBOX_H__ */