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Merge 5.10.158 into android12-5.10-lts
Changes in 5.10.158
btrfs: sink iterator parameter to btrfs_ioctl_logical_to_ino
btrfs: free btrfs_path before copying inodes to userspace
spi: spi-imx: Fix spi_bus_clk if requested clock is higher than input clock
btrfs: move QUOTA_ENABLED check to rescan_should_stop from btrfs_qgroup_rescan_worker
drm/display/dp_mst: Fix drm_dp_mst_add_affected_dsc_crtcs() return code
drm/amdgpu: update drm_display_info correctly when the edid is read
drm/amdgpu: Partially revert "drm/amdgpu: update drm_display_info correctly when the edid is read"
btrfs: qgroup: fix sleep from invalid context bug in btrfs_qgroup_inherit()
iio: health: afe4403: Fix oob read in afe4403_read_raw
iio: health: afe4404: Fix oob read in afe4404_[read|write]_raw
iio: light: rpr0521: add missing Kconfig dependencies
bpf, perf: Use subprog name when reporting subprog ksymbol
scripts/faddr2line: Fix regression in name resolution on ppc64le
ARM: at91: rm9200: fix usb device clock id
libbpf: Handle size overflow for ringbuf mmap
hwmon: (ltc2947) fix temperature scaling
hwmon: (ina3221) Fix shunt sum critical calculation
hwmon: (i5500_temp) fix missing pci_disable_device()
hwmon: (ibmpex) Fix possible UAF when ibmpex_register_bmc() fails
bpf: Do not copy spin lock field from user in bpf_selem_alloc
of: property: decrement node refcount in of_fwnode_get_reference_args()
ixgbevf: Fix resource leak in ixgbevf_init_module()
i40e: Fix error handling in i40e_init_module()
fm10k: Fix error handling in fm10k_init_module()
iavf: remove redundant ret variable
iavf: Fix error handling in iavf_init_module()
e100: switch from 'pci_' to 'dma_' API
e100: Fix possible use after free in e100_xmit_prepare
net/mlx5: Fix uninitialized variable bug in outlen_write()
net/mlx5e: Fix use-after-free when reverting termination table
can: sja1000_isa: sja1000_isa_probe(): add missing free_sja1000dev()
can: cc770: cc770_isa_probe(): add missing free_cc770dev()
qlcnic: fix sleep-in-atomic-context bugs caused by msleep
aquantia: Do not purge addresses when setting the number of rings
wifi: cfg80211: fix buffer overflow in elem comparison
wifi: cfg80211: don't allow multi-BSSID in S1G
wifi: mac8021: fix possible oob access in ieee80211_get_rate_duration
net: phy: fix null-ptr-deref while probe() failed
net: net_netdev: Fix error handling in ntb_netdev_init_module()
net/9p: Fix a potential socket leak in p9_socket_open
net: ethernet: nixge: fix NULL dereference
dsa: lan9303: Correct stat name
tipc: re-fetch skb cb after tipc_msg_validate
net: hsr: Fix potential use-after-free
afs: Fix fileserver probe RTT handling
net: tun: Fix use-after-free in tun_detach()
packet: do not set TP_STATUS_CSUM_VALID on CHECKSUM_COMPLETE
sctp: fix memory leak in sctp_stream_outq_migrate()
net: ethernet: renesas: ravb: Fix promiscuous mode after system resumed
hwmon: (coretemp) Check for null before removing sysfs attrs
hwmon: (coretemp) fix pci device refcount leak in nv1a_ram_new()
net/mlx5: DR, Fix uninitialized var warning
riscv: vdso: fix section overlapping under some conditions
error-injection: Add prompt for function error injection
tools/vm/slabinfo-gnuplot: use "grep -E" instead of "egrep"
nilfs2: fix NULL pointer dereference in nilfs_palloc_commit_free_entry()
x86/bugs: Make sure MSR_SPEC_CTRL is updated properly upon resume from S3
pinctrl: intel: Save and restore pins in "direct IRQ" mode
net: stmmac: Set MAC's flow control register to reflect current settings
mmc: mmc_test: Fix removal of debugfs file
mmc: core: Fix ambiguous TRIM and DISCARD arg
mmc: sdhci-esdhc-imx: correct CQHCI exit halt state check
mmc: sdhci-sprd: Fix no reset data and command after voltage switch
mmc: sdhci: Fix voltage switch delay
drm/amdgpu: temporarily disable broken Clang builds due to blown stack-frame
drm/i915: Never return 0 if not all requests retired
tracing: Free buffers when a used dynamic event is removed
io_uring: don't hold uring_lock when calling io_run_task_work*
ASoC: ops: Fix bounds check for _sx controls
pinctrl: single: Fix potential division by zero
iommu/vt-d: Fix PCI device refcount leak in has_external_pci()
iommu/vt-d: Fix PCI device refcount leak in dmar_dev_scope_init()
parisc: Increase size of gcc stack frame check
xtensa: increase size of gcc stack frame check
parisc: Increase FRAME_WARN to 2048 bytes on parisc
Kconfig.debug: provide a little extra FRAME_WARN leeway when KASAN is enabled
selftests: net: add delete nexthop route warning test
selftests: net: fix nexthop warning cleanup double ip typo
ipv4: Handle attempt to delete multipath route when fib_info contains an nh reference
ipv4: Fix route deletion when nexthop info is not specified
Revert "tty: n_gsm: avoid call of sleeping functions from atomic context"
x86/tsx: Add a feature bit for TSX control MSR support
x86/pm: Add enumeration check before spec MSRs save/restore setup
i2c: npcm7xx: Fix error handling in npcm_i2c_init()
i2c: imx: Only DMA messages with I2C_M_DMA_SAFE flag set
ACPI: HMAT: remove unnecessary variable initialization
ACPI: HMAT: Fix initiator registration for single-initiator systems
Revert "clocksource/drivers/riscv: Events are stopped during CPU suspend"
char: tpm: Protect tpm_pm_suspend with locks
Input: raydium_ts_i2c - fix memory leak in raydium_i2c_send()
block: unhash blkdev part inode when the part is deleted
proc: avoid integer type confusion in get_proc_long
proc: proc_skip_spaces() shouldn't think it is working on C strings
v4l2: don't fall back to follow_pfn() if pin_user_pages_fast() fails
ipc/sem: Fix dangling sem_array access in semtimedop race
Linux 5.10.158
Change-Id: I8db196fa535e260ed31965b52ed53ef0b6bd526b
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
2
Makefile
2
Makefile
@@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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VERSION = 5
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PATCHLEVEL = 10
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SUBLEVEL = 157
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SUBLEVEL = 158
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EXTRAVERSION =
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NAME = Dare mighty things
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@@ -660,7 +660,7 @@
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compatible = "atmel,at91rm9200-udc";
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reg = <0xfffb0000 0x4000>;
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interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 1>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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};
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@@ -17,6 +17,7 @@ vdso-syms += flush_icache
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obj-vdso = $(patsubst %, %.o, $(vdso-syms)) note.o
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ccflags-y := -fno-stack-protector
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ccflags-y += -DDISABLE_BRANCH_PROFILING
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ifneq ($(c-gettimeofday-y),)
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CFLAGS_vgettimeofday.o += -fPIC -include $(c-gettimeofday-y)
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@@ -300,6 +300,7 @@
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#define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */
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#define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */
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#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
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#define X86_FEATURE_MSR_TSX_CTRL (11*32+18) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
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/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
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@@ -310,7 +310,7 @@ static inline void indirect_branch_prediction_barrier(void)
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/* The Intel SPEC CTRL MSR base value cache */
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extern u64 x86_spec_ctrl_base;
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DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
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extern void write_spec_ctrl_current(u64 val, bool force);
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extern void update_spec_ctrl_cond(u64 val);
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extern u64 spec_ctrl_current(void);
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/*
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@@ -59,11 +59,18 @@ EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
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static DEFINE_MUTEX(spec_ctrl_mutex);
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/* Update SPEC_CTRL MSR and its cached copy unconditionally */
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static void update_spec_ctrl(u64 val)
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{
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this_cpu_write(x86_spec_ctrl_current, val);
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wrmsrl(MSR_IA32_SPEC_CTRL, val);
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}
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/*
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* Keep track of the SPEC_CTRL MSR value for the current task, which may differ
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* from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
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*/
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void write_spec_ctrl_current(u64 val, bool force)
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void update_spec_ctrl_cond(u64 val)
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{
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if (this_cpu_read(x86_spec_ctrl_current) == val)
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return;
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@@ -74,7 +81,7 @@ void write_spec_ctrl_current(u64 val, bool force)
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* When KERNEL_IBRS this MSR is written on return-to-user, unless
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* forced the update can be delayed until that time.
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*/
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if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
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if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
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wrmsrl(MSR_IA32_SPEC_CTRL, val);
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}
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@@ -1291,7 +1298,7 @@ static void __init spec_ctrl_disable_kernel_rrsba(void)
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if (ia32_cap & ARCH_CAP_RRSBA) {
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x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
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write_spec_ctrl_current(x86_spec_ctrl_base, true);
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update_spec_ctrl(x86_spec_ctrl_base);
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}
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}
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@@ -1413,7 +1420,7 @@ static void __init spectre_v2_select_mitigation(void)
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if (spectre_v2_in_ibrs_mode(mode)) {
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x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
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write_spec_ctrl_current(x86_spec_ctrl_base, true);
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update_spec_ctrl(x86_spec_ctrl_base);
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}
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switch (mode) {
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@@ -1527,7 +1534,7 @@ static void __init spectre_v2_select_mitigation(void)
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static void update_stibp_msr(void * __unused)
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{
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u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
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write_spec_ctrl_current(val, true);
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update_spec_ctrl(val);
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}
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/* Update x86_spec_ctrl_base in case SMT state changed. */
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@@ -1760,7 +1767,7 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
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x86_amd_ssb_disable();
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} else {
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x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
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write_spec_ctrl_current(x86_spec_ctrl_base, true);
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update_spec_ctrl(x86_spec_ctrl_base);
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}
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}
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@@ -1978,7 +1985,7 @@ int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
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void x86_spec_ctrl_setup_ap(void)
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{
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if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
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write_spec_ctrl_current(x86_spec_ctrl_base, true);
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update_spec_ctrl(x86_spec_ctrl_base);
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if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
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x86_amd_ssb_disable();
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@@ -58,24 +58,6 @@ void tsx_enable(void)
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wrmsrl(MSR_IA32_TSX_CTRL, tsx);
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}
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static bool __init tsx_ctrl_is_supported(void)
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{
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u64 ia32_cap = x86_read_arch_cap_msr();
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/*
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* TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
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* MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
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*
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* TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
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* microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
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* bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
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* MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
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* tsx= cmdline requests will do nothing on CPUs without
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* MSR_IA32_TSX_CTRL support.
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*/
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return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR);
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}
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static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
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{
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if (boot_cpu_has_bug(X86_BUG_TAA))
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@@ -89,9 +71,22 @@ void __init tsx_init(void)
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char arg[5] = {};
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int ret;
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if (!tsx_ctrl_is_supported())
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/*
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* TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
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* MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
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*
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* TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
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* microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
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* bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
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* MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
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* tsx= cmdline requests will do nothing on CPUs without
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* MSR_IA32_TSX_CTRL support.
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*/
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if (!(x86_read_arch_cap_msr() & ARCH_CAP_TSX_CTRL_MSR))
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return;
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setup_force_cpu_cap(X86_FEATURE_MSR_TSX_CTRL);
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ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));
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if (ret >= 0) {
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if (!strcmp(arg, "on")) {
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@@ -556,7 +556,7 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp,
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}
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if (updmsr)
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write_spec_ctrl_current(msr, false);
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update_spec_ctrl_cond(msr);
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}
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static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
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@@ -529,16 +529,23 @@ static int pm_cpu_check(const struct x86_cpu_id *c)
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static void pm_save_spec_msr(void)
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{
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u32 spec_msr_id[] = {
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MSR_IA32_SPEC_CTRL,
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MSR_IA32_TSX_CTRL,
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MSR_TSX_FORCE_ABORT,
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MSR_IA32_MCU_OPT_CTRL,
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MSR_AMD64_LS_CFG,
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MSR_AMD64_DE_CFG,
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struct msr_enumeration {
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u32 msr_no;
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u32 feature;
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} msr_enum[] = {
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{ MSR_IA32_SPEC_CTRL, X86_FEATURE_MSR_SPEC_CTRL },
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{ MSR_IA32_TSX_CTRL, X86_FEATURE_MSR_TSX_CTRL },
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{ MSR_TSX_FORCE_ABORT, X86_FEATURE_TSX_FORCE_ABORT },
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{ MSR_IA32_MCU_OPT_CTRL, X86_FEATURE_SRBDS_CTRL },
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{ MSR_AMD64_LS_CFG, X86_FEATURE_LS_CFG_SSBD },
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{ MSR_AMD64_DE_CFG, X86_FEATURE_LFENCE_RDTSC },
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};
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int i;
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msr_build_context(spec_msr_id, ARRAY_SIZE(spec_msr_id));
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for (i = 0; i < ARRAY_SIZE(msr_enum); i++) {
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if (boot_cpu_has(msr_enum[i].feature))
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msr_build_context(&msr_enum[i].msr_no, 1);
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}
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}
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static int pm_check_save_msr(void)
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@@ -329,6 +329,7 @@ void delete_partition(struct hd_struct *part)
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struct gendisk *disk = part_to_disk(part);
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struct disk_part_tbl *ptbl =
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rcu_dereference_protected(disk->part_tbl, 1);
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struct block_device *bdev;
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/*
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* ->part_tbl is referenced in this part's release handler, so
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@@ -346,6 +347,12 @@ void delete_partition(struct hd_struct *part)
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* "in-use" until we really free the gendisk.
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*/
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blk_invalidate_devt(part_devt(part));
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bdev = bdget_part(part);
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if (bdev) {
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remove_inode_hash(bdev->bd_inode);
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bdput(bdev);
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}
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percpu_ref_kill(&part->ref);
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}
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@@ -562,17 +562,26 @@ static int initiator_cmp(void *priv, struct list_head *a, struct list_head *b)
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{
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struct memory_initiator *ia;
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struct memory_initiator *ib;
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unsigned long *p_nodes = priv;
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ia = list_entry(a, struct memory_initiator, node);
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ib = list_entry(b, struct memory_initiator, node);
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set_bit(ia->processor_pxm, p_nodes);
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set_bit(ib->processor_pxm, p_nodes);
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return ia->processor_pxm - ib->processor_pxm;
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}
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static int initiators_to_nodemask(unsigned long *p_nodes)
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{
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struct memory_initiator *initiator;
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if (list_empty(&initiators))
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return -ENXIO;
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list_for_each_entry(initiator, &initiators, node)
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set_bit(initiator->processor_pxm, p_nodes);
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return 0;
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}
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static void hmat_register_target_initiators(struct memory_target *target)
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{
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static DECLARE_BITMAP(p_nodes, MAX_NUMNODES);
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@@ -609,7 +618,10 @@ static void hmat_register_target_initiators(struct memory_target *target)
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* initiators.
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*/
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bitmap_zero(p_nodes, MAX_NUMNODES);
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list_sort(p_nodes, &initiators, initiator_cmp);
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list_sort(NULL, &initiators, initiator_cmp);
|
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if (initiators_to_nodemask(p_nodes) < 0)
|
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return;
|
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|
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if (!access0done) {
|
||||
for (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) {
|
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loc = localities_types[i];
|
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@@ -643,8 +655,9 @@ static void hmat_register_target_initiators(struct memory_target *target)
|
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|
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/* Access 1 ignores Generic Initiators */
|
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bitmap_zero(p_nodes, MAX_NUMNODES);
|
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list_sort(p_nodes, &initiators, initiator_cmp);
|
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best = 0;
|
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if (initiators_to_nodemask(p_nodes) < 0)
|
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return;
|
||||
|
||||
for (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) {
|
||||
loc = localities_types[i];
|
||||
if (!loc)
|
||||
|
||||
@@ -401,13 +401,14 @@ int tpm_pm_suspend(struct device *dev)
|
||||
!pm_suspend_via_firmware())
|
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goto suspended;
|
||||
|
||||
if (!tpm_chip_start(chip)) {
|
||||
rc = tpm_try_get_ops(chip);
|
||||
if (!rc) {
|
||||
if (chip->flags & TPM_CHIP_FLAG_TPM2)
|
||||
tpm2_shutdown(chip, TPM2_SU_STATE);
|
||||
else
|
||||
rc = tpm1_pm_suspend(chip, tpm_suspend_pcr);
|
||||
|
||||
tpm_chip_stop(chip);
|
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tpm_put_ops(chip);
|
||||
}
|
||||
|
||||
suspended:
|
||||
|
||||
@@ -38,7 +38,7 @@ static const struct clk_pll_characteristics rm9200_pll_characteristics = {
|
||||
};
|
||||
|
||||
static const struct sck at91rm9200_systemck[] = {
|
||||
{ .n = "udpck", .p = "usbck", .id = 2 },
|
||||
{ .n = "udpck", .p = "usbck", .id = 1 },
|
||||
{ .n = "uhpck", .p = "usbck", .id = 4 },
|
||||
{ .n = "pck0", .p = "prog0", .id = 8 },
|
||||
{ .n = "pck1", .p = "prog1", .id = 9 },
|
||||
|
||||
@@ -32,7 +32,7 @@ static int riscv_clock_next_event(unsigned long delta,
|
||||
static unsigned int riscv_clock_event_irq;
|
||||
static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
|
||||
.name = "riscv_timer_clockevent",
|
||||
.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP,
|
||||
.features = CLOCK_EVT_FEAT_ONESHOT,
|
||||
.rating = 100,
|
||||
.set_next_event = riscv_clock_next_event,
|
||||
};
|
||||
|
||||
@@ -315,8 +315,10 @@ static void amdgpu_connector_get_edid(struct drm_connector *connector)
|
||||
if (!amdgpu_connector->edid) {
|
||||
/* some laptops provide a hardcoded edid in rom for LCDs */
|
||||
if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
|
||||
(connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
|
||||
(connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
|
||||
amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
|
||||
drm_connector_update_edid_property(connector, amdgpu_connector->edid);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -5,6 +5,7 @@ menu "Display Engine Configuration"
|
||||
config DRM_AMD_DC
|
||||
bool "AMD DC - Enable new display engine"
|
||||
default y
|
||||
depends on BROKEN || !CC_IS_CLANG || X86_64 || SPARC64 || ARM64
|
||||
select SND_HDA_COMPONENT if SND_HDA_CORE
|
||||
select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
|
||||
help
|
||||
@@ -12,6 +13,12 @@ config DRM_AMD_DC
|
||||
support for AMDGPU. This adds required support for Vega and
|
||||
Raven ASICs.
|
||||
|
||||
calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 || ARM64)
|
||||
architectures built with Clang (all released versions), whereby the stack
|
||||
frame gets blown up to well over 5k. This would cause an immediate kernel
|
||||
panic on most architectures. We'll revert this when the following bug report
|
||||
has been resolved: https://github.com/llvm/llvm-project/issues/41896.
|
||||
|
||||
config DRM_AMD_DC_DCN
|
||||
def_bool n
|
||||
help
|
||||
|
||||
@@ -2348,13 +2348,12 @@ void amdgpu_dm_update_connector_after_detect(
|
||||
aconnector->edid =
|
||||
(struct edid *)sink->dc_edid.raw_edid;
|
||||
|
||||
drm_connector_update_edid_property(connector,
|
||||
aconnector->edid);
|
||||
if (aconnector->dc_link->aux_mode)
|
||||
drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
|
||||
aconnector->edid);
|
||||
}
|
||||
|
||||
drm_connector_update_edid_property(connector, aconnector->edid);
|
||||
amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
|
||||
update_connector_ext_caps(aconnector);
|
||||
} else {
|
||||
|
||||
@@ -5238,7 +5238,7 @@ int drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_state *state, struct drm
|
||||
mst_state = drm_atomic_get_mst_topology_state(state, mgr);
|
||||
|
||||
if (IS_ERR(mst_state))
|
||||
return -EINVAL;
|
||||
return PTR_ERR(mst_state);
|
||||
|
||||
list_for_each_entry(pos, &mst_state->vcpis, next) {
|
||||
|
||||
|
||||
@@ -200,7 +200,7 @@ out_active: spin_lock(&timelines->lock);
|
||||
if (flush_submission(gt, timeout)) /* Wait, there's more! */
|
||||
active_count++;
|
||||
|
||||
return active_count ? timeout : 0;
|
||||
return active_count ? timeout ?: -ETIME : 0;
|
||||
}
|
||||
|
||||
int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
|
||||
|
||||
@@ -242,10 +242,13 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
|
||||
*/
|
||||
if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) {
|
||||
for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) {
|
||||
if (host_bridge->device == tjmax_pci_table[i].device)
|
||||
if (host_bridge->device == tjmax_pci_table[i].device) {
|
||||
pci_dev_put(host_bridge);
|
||||
return tjmax_pci_table[i].tjmax;
|
||||
}
|
||||
}
|
||||
}
|
||||
pci_dev_put(host_bridge);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) {
|
||||
if (strstr(c->x86_model_id, tjmax_table[i].id))
|
||||
@@ -533,6 +536,10 @@ static void coretemp_remove_core(struct platform_data *pdata, int indx)
|
||||
{
|
||||
struct temp_data *tdata = pdata->core_data[indx];
|
||||
|
||||
/* if we errored on add then this is already gone */
|
||||
if (!tdata)
|
||||
return;
|
||||
|
||||
/* Remove the sysfs attributes */
|
||||
sysfs_remove_group(&pdata->hwmon_dev->kobj, &tdata->attr_group);
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user