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perf vendor events powerpc: Update POWER9 events
Update and cleanup POWER9 PMU events. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Cc: Anton Blanchard <anton@au1.ibm.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Link: http://lkml.kernel.org/r/20170802174617.GA32545@us.ibm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Sukadev Bhattiprolu
committed by
Arnaldo Carvalho de Melo
Arnaldo Carvalho de Melo
parent
2862a16875
commit
3c22ba5243
@@ -1,176 +1,137 @@
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[
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{,
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"EventCode": "0x1002A",
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"EventName": "PM_CMPLU_STALL_LARX",
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"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x1003C",
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"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
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"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x14048",
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"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
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"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x3E054",
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"EventName": "PM_LD_MISS_L1",
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"BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x400F0",
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"EventName": "PM_LD_MISS_L1",
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"BriefDescription": "Load Missed L1, at execution time (not gated by finish, which means this counter can be greater than loads finished)",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x1404A",
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"EventName": "PM_INST_FROM_RL2L3_SHR",
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"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x1C058",
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"EventName": "PM_DTLB_MISS_16G",
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"BriefDescription": "Data TLB Miss page size 16G",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x1D15C",
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"EventName": "PM_MRK_DTLB_MISS_1G",
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"BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used",
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"PublicDescription": ""
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"EventCode": "0x300F4",
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"EventName": "PM_THRD_CONC_RUN_INST",
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"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
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},
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{,
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"EventCode": "0x1E056",
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"EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
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"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x101E6",
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"EventName": "PM_THRESH_EXC_4096",
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"BriefDescription": "Threshold counter exceed a count of 4096",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x2C01A",
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"EventName": "PM_CMPLU_STALL_LHS",
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"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x2D016",
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"EventName": "PM_CMPLU_STALL_FXU",
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"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x24046",
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"EventName": "PM_INST_FROM_RL2L3_MOD",
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"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x2404A",
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"EventName": "PM_INST_FROM_RL4",
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"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x2F140",
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"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x2D15E",
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"EventName": "PM_MRK_DTLB_MISS_16G",
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"BriefDescription": "Marked Data TLB Miss page size 16G",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x3F14A",
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"EventName": "PM_MRK_DPTEG_FROM_RMEM",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x3D156",
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"EventName": "PM_MRK_DTLB_MISS_64K",
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"BriefDescription": "Marked Data TLB Miss page size 64K",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x3006C",
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"EventName": "PM_RUN_CYC_SMT2_MODE",
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"BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT2 mode",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x300F4",
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"EventName": "PM_THRD_CONC_RUN_INST",
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"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x4C014",
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"EventName": "PM_CMPLU_STALL_LMQ_FULL",
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"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x4C016",
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"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
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"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x4D014",
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"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
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"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish",
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"PublicDescription": ""
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"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion"
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},
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{,
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"EventCode": "0x4D016",
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"EventName": "PM_CMPLU_STALL_FXLONG",
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"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)",
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"PublicDescription": ""
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"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)"
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},
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{,
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"EventCode": "0x2D016",
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"EventName": "PM_CMPLU_STALL_FXU",
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"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
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},
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{,
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"EventCode": "0x1D15C",
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"EventName": "PM_MRK_DTLB_MISS_1G",
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"BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used"
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},
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{,
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"EventCode": "0x4D12A",
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"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
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"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
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"PublicDescription": ""
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"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
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},
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{,
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"EventCode": "0x4C15E",
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"EventName": "PM_MRK_DTLB_MISS_16M",
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"BriefDescription": "Marked Data TLB Miss page size 16M",
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"PublicDescription": ""
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"EventCode": "0x1003C",
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"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
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"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3"
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},
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{,
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"EventCode": "0x401E4",
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"EventName": "PM_MRK_DTLB_MISS",
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"BriefDescription": "Marked dtlb miss",
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"PublicDescription": ""
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"EventCode": "0x4C014",
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"EventName": "PM_CMPLU_STALL_LMQ_FULL",
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"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full"
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},
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{,
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"EventCode": "0x14048",
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"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
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"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x4D014",
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"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
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"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish"
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},
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{,
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"EventCode": "0x2404A",
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"EventName": "PM_INST_FROM_RL4",
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"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x1404A",
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"EventName": "PM_INST_FROM_RL2L3_SHR",
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"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x401EA",
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"EventName": "PM_THRESH_EXC_128",
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"BriefDescription": "Threshold counter exceeded a value of 128",
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"PublicDescription": ""
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"BriefDescription": "Threshold counter exceeded a value of 128"
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},
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{,
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"EventCode": "0x400F6",
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"EventName": "PM_BR_MPRED_CMPL",
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"BriefDescription": "Number of Branch Mispredicts",
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"PublicDescription": ""
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"BriefDescription": "Number of Branch Mispredicts"
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},
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{,
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"EventCode": "0x2F140",
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"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{,
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"EventCode": "0x101E6",
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"EventName": "PM_THRESH_EXC_4096",
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"BriefDescription": "Threshold counter exceed a count of 4096"
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},
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{,
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"EventCode": "0x3D156",
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"EventName": "PM_MRK_DTLB_MISS_64K",
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"BriefDescription": "Marked Data TLB Miss page size 64K"
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},
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{,
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"EventCode": "0x4C15E",
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"EventName": "PM_MRK_DTLB_MISS_16M",
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"BriefDescription": "Marked Data TLB Miss page size 16M"
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},
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{,
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"EventCode": "0x2D15E",
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"EventName": "PM_MRK_DTLB_MISS_16G",
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"BriefDescription": "Marked Data TLB Miss page size 16G"
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},
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{,
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"EventCode": "0x3F14A",
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"EventName": "PM_MRK_DPTEG_FROM_RMEM",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{,
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"EventCode": "0x4C016",
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"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
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"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict"
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},
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{,
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"EventCode": "0x2C01A",
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"EventName": "PM_CMPLU_STALL_LHS",
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"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data"
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},
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{,
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"EventCode": "0x401E4",
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"EventName": "PM_MRK_DTLB_MISS",
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"BriefDescription": "Marked dtlb miss"
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},
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{,
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"EventCode": "0x24046",
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"EventName": "PM_INST_FROM_RL2L3_MOD",
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"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x1002A",
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"EventName": "PM_CMPLU_STALL_LARX",
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"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
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},
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{,
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"EventCode": "0x3006C",
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"EventName": "PM_RUN_CYC_SMT2_MODE",
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"BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT2 mode"
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},
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{,
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"EventCode": "0x1C058",
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"EventName": "PM_DTLB_MISS_16G",
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"BriefDescription": "Data TLB Miss page size 16G"
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}
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]
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]
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@@ -1,44 +1,32 @@
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[
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{,
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"EventCode": "0x10058",
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"EventName": "PM_MEM_LOC_THRESH_IFU",
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"BriefDescription": "Local Memory above threshold for IFU speculation control",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x4505E",
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"EventName": "PM_FLOP_CMPL",
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"BriefDescription": "Floating Point Operation Finished",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x1415A",
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"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
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"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
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"PublicDescription": ""
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"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load"
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},
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{,
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"EventCode": "0x10058",
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"EventName": "PM_MEM_LOC_THRESH_IFU",
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"BriefDescription": "Local Memory above threshold for IFU speculation control"
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},
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{,
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"EventCode": "0x2D028",
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"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
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"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x2D154",
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"EventName": "PM_MRK_DERAT_MISS_64K",
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"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K",
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"PublicDescription": ""
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"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache"
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},
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{,
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"EventCode": "0x30012",
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"EventName": "PM_FLUSH_COMPLETION",
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"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush",
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"PublicDescription": ""
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"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush"
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},
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{,
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"EventCode": "0x2D154",
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"EventName": "PM_MRK_DERAT_MISS_64K",
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"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K"
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},
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{,
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"EventCode": "0x4016E",
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"EventName": "PM_THRESH_NOT_MET",
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"BriefDescription": "Threshold counter did not meet threshold",
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"PublicDescription": ""
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"BriefDescription": "Threshold counter did not meet threshold"
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}
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]
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]
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,158 +1,132 @@
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[
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{,
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"EventCode": "0x10008",
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"EventName": "PM_RUN_SPURR",
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"BriefDescription": "Run SPURR",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x1000A",
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"EventName": "PM_PMC3_REWIND",
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"BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change.",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x1C040",
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"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
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"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x1C050",
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"EventName": "PM_DATA_CHIP_PUMP_CPRED",
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"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x1D15E",
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"EventName": "PM_MRK_RUN_CYC",
|
||||
"BriefDescription": "Run cycles in which a marked instruction is in the pipeline",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x15158",
|
||||
"EventName": "PM_SYNC_MRK_L2HIT",
|
||||
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt",
|
||||
"PublicDescription": ""
|
||||
"EventCode": "0x3006E",
|
||||
"EventName": "PM_NEST_REF_CLK",
|
||||
"BriefDescription": "Multiply by 4 to obtain the number of PB cycles"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x20010",
|
||||
"EventName": "PM_PMC1_OVERFLOW",
|
||||
"BriefDescription": "Overflow from counter 1",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2C040",
|
||||
"EventName": "PM_DATA_FROM_L2_MEPF",
|
||||
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
|
||||
"PublicDescription": ""
|
||||
"BriefDescription": "Overflow from counter 1"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2005A",
|
||||
"EventName": "PM_DARQ1_7_9_ENTRIES",
|
||||
"BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2C05C",
|
||||
"EventName": "PM_INST_GRP_PUMP_CPRED",
|
||||
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2D156",
|
||||
"EventName": "PM_MRK_DTLB_MISS_4K",
|
||||
"BriefDescription": "Marked Data TLB Miss page size 4k",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2E05A",
|
||||
"EventName": "PM_LRQ_REJECT",
|
||||
"BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2E05C",
|
||||
"EventName": "PM_LSU_REJECT_ERAT_MISS",
|
||||
"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x200F6",
|
||||
"EventName": "PM_LSU_DERAT_MISS",
|
||||
"BriefDescription": "DERAT Reloaded due to a DERAT miss",
|
||||
"PublicDescription": ""
|
||||
"BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3C048",
|
||||
"EventName": "PM_DATA_FROM_DL2L3_SHR",
|
||||
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
|
||||
"PublicDescription": ""
|
||||
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3404A",
|
||||
"EventName": "PM_INST_FROM_RMEM",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
|
||||
"PublicDescription": ""
|
||||
"EventCode": "0x10008",
|
||||
"EventName": "PM_RUN_SPURR",
|
||||
"BriefDescription": "Run SPURR"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3C058",
|
||||
"EventName": "PM_LARX_FIN",
|
||||
"BriefDescription": "Larx finished",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3E050",
|
||||
"EventName": "PM_DARQ1_4_6_ENTRIES",
|
||||
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3006E",
|
||||
"EventName": "PM_NEST_REF_CLK",
|
||||
"BriefDescription": "Multiply by 4 to obtain the number of PB cycles",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x301E2",
|
||||
"EventName": "PM_MRK_ST_CMPL",
|
||||
"BriefDescription": "Marked store completed and sent to nest",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D02C",
|
||||
"EventName": "PM_PMC1_REWIND",
|
||||
"BriefDescription": "",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4003E",
|
||||
"EventName": "PM_LD_CMPL",
|
||||
"BriefDescription": "count of Loads completed",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4C040",
|
||||
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
|
||||
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4C042",
|
||||
"EventName": "PM_DATA_FROM_L3",
|
||||
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load",
|
||||
"PublicDescription": ""
|
||||
"EventCode": "0x200F6",
|
||||
"EventName": "PM_LSU_DERAT_MISS",
|
||||
"BriefDescription": "DERAT Reloaded due to a DERAT miss"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4C048",
|
||||
"EventName": "PM_DATA_FROM_DL2L3_MOD",
|
||||
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
|
||||
"PublicDescription": ""
|
||||
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1D15E",
|
||||
"EventName": "PM_MRK_RUN_CYC",
|
||||
"BriefDescription": "Run cycles in which a marked instruction is in the pipeline"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4003E",
|
||||
"EventName": "PM_LD_CMPL",
|
||||
"BriefDescription": "count of Loads completed"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2D156",
|
||||
"EventName": "PM_MRK_DTLB_MISS_4K",
|
||||
"BriefDescription": "Marked Data TLB Miss page size 4k"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4C042",
|
||||
"EventName": "PM_DATA_FROM_L3",
|
||||
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D02C",
|
||||
"EventName": "PM_PMC1_REWIND",
|
||||
"BriefDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x15158",
|
||||
"EventName": "PM_SYNC_MRK_L2HIT",
|
||||
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3404A",
|
||||
"EventName": "PM_INST_FROM_RMEM",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x301E2",
|
||||
"EventName": "PM_MRK_ST_CMPL",
|
||||
"BriefDescription": "Marked store completed and sent to nest"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1C050",
|
||||
"EventName": "PM_DATA_CHIP_PUMP_CPRED",
|
||||
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4C040",
|
||||
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
|
||||
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2E05C",
|
||||
"EventName": "PM_LSU_REJECT_ERAT_MISS",
|
||||
"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1000A",
|
||||
"EventName": "PM_PMC3_REWIND",
|
||||
"BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change."
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3C058",
|
||||
"EventName": "PM_LARX_FIN",
|
||||
"BriefDescription": "Larx finished"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1C040",
|
||||
"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
|
||||
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2C040",
|
||||
"EventName": "PM_DATA_FROM_L2_MEPF",
|
||||
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2E05A",
|
||||
"EventName": "PM_LRQ_REJECT",
|
||||
"BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2C05C",
|
||||
"EventName": "PM_INST_GRP_PUMP_CPRED",
|
||||
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D056",
|
||||
"EventName": "PM_NON_FMA_FLOP_CMPL",
|
||||
"BriefDescription": "Non FMA instruction completed",
|
||||
"PublicDescription": ""
|
||||
"BriefDescription": "Non FMA instruction completed"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3E050",
|
||||
"EventName": "PM_DARQ1_4_6_ENTRIES",
|
||||
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use"
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,146 +1,127 @@
|
||||
[
|
||||
{,
|
||||
"EventCode": "0x0",
|
||||
"EventName": "PM_SUSPENDED",
|
||||
"BriefDescription": "Counter OFF",
|
||||
"PublicDescription": ""
|
||||
"EventCode": "0x20036",
|
||||
"EventName": "PM_BR_2PATH",
|
||||
"BriefDescription": "Branches that are not strongly biased"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x10026",
|
||||
"EventName": "PM_TABLEWALK_CYC",
|
||||
"BriefDescription": "Cycles when an instruction tablewalk is active",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1E04C",
|
||||
"EventName": "PM_DPTEG_FROM_LL4",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1F14E",
|
||||
"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x10060",
|
||||
"EventName": "PM_TM_TRANS_RUN_CYC",
|
||||
"BriefDescription": "run cycles in transactional state",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2C012",
|
||||
"EventName": "PM_CMPLU_STALL_DCACHE_MISS",
|
||||
"BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2E04C",
|
||||
"EventName": "PM_DPTEG_FROM_MEMORY",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2C056",
|
||||
"EventName": "PM_DTLB_MISS_4K",
|
||||
"BriefDescription": "Data TLB Miss page size 4k",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3000C",
|
||||
"EventName": "PM_FREQ_DOWN",
|
||||
"BriefDescription": "Power Management: Below Threshold B",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3D142",
|
||||
"EventName": "PM_MRK_DATA_FROM_LMEM",
|
||||
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3F142",
|
||||
"EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x301E8",
|
||||
"EventName": "PM_THRESH_EXC_64",
|
||||
"BriefDescription": "Threshold counter exceeded a value of 64",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x40118",
|
||||
"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
|
||||
"BriefDescription": "Combined Intervention event",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4C01E",
|
||||
"EventName": "PM_CMPLU_STALL_CRYPTO",
|
||||
"BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D018",
|
||||
"EventName": "PM_CMPLU_STALL_BRU",
|
||||
"BriefDescription": "Completion stall due to a Branch Unit",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D128",
|
||||
"EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
|
||||
"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4E04E",
|
||||
"EventName": "PM_DPTEG_FROM_L3MISS",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4F142",
|
||||
"EventName": "PM_MRK_DPTEG_FROM_L3",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4F148",
|
||||
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x40050",
|
||||
"EventName": "PM_SYS_PUMP_MPRED_RTY",
|
||||
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
|
||||
"PublicDescription": ""
|
||||
"EventCode": "0x40036",
|
||||
"EventName": "PM_BR_2PATH",
|
||||
"BriefDescription": "Branches that are not strongly biased"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x40056",
|
||||
"EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
|
||||
"BriefDescription": "Local memory above threshold for LSU medium",
|
||||
"PublicDescription": ""
|
||||
"BriefDescription": "Local memory above threshold for LSU medium"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D054",
|
||||
"EventName": "PM_8FLOP_CMPL",
|
||||
"BriefDescription": "8 FLOP instruction completed",
|
||||
"PublicDescription": ""
|
||||
"EventCode": "0x2C056",
|
||||
"EventName": "PM_DTLB_MISS_4K",
|
||||
"BriefDescription": "Data TLB Miss page size 4k"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x45050",
|
||||
"EventName": "PM_1FLOP_CMPL",
|
||||
"BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed",
|
||||
"PublicDescription": ""
|
||||
"EventCode": "0x40118",
|
||||
"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
|
||||
"BriefDescription": "Combined Intervention event"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4F148",
|
||||
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x301E8",
|
||||
"EventName": "PM_THRESH_EXC_64",
|
||||
"BriefDescription": "Threshold counter exceeded a value of 64"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4E04E",
|
||||
"EventName": "PM_DPTEG_FROM_L3MISS",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x40050",
|
||||
"EventName": "PM_SYS_PUMP_MPRED_RTY",
|
||||
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1F14E",
|
||||
"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D018",
|
||||
"EventName": "PM_CMPLU_STALL_BRU",
|
||||
"BriefDescription": "Completion stall due to a Branch Unit"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x45052",
|
||||
"EventName": "PM_4FLOP_CMPL",
|
||||
"BriefDescription": "4 FLOP instruction completed",
|
||||
"PublicDescription": ""
|
||||
"BriefDescription": "4 FLOP instruction completed"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3D142",
|
||||
"EventName": "PM_MRK_DATA_FROM_LMEM",
|
||||
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4C01E",
|
||||
"EventName": "PM_CMPLU_STALL_CRYPTO",
|
||||
"BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3000C",
|
||||
"EventName": "PM_FREQ_DOWN",
|
||||
"BriefDescription": "Power Management: Below Threshold B"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D128",
|
||||
"EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
|
||||
"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D054",
|
||||
"EventName": "PM_8FLOP_CMPL",
|
||||
"BriefDescription": "8 FLOP instruction completed"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x10026",
|
||||
"EventName": "PM_TABLEWALK_CYC",
|
||||
"BriefDescription": "Cycles when an instruction tablewalk is active"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2C012",
|
||||
"EventName": "PM_CMPLU_STALL_DCACHE_MISS",
|
||||
"BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2E04C",
|
||||
"EventName": "PM_DPTEG_FROM_MEMORY",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3F142",
|
||||
"EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4F142",
|
||||
"EventName": "PM_MRK_DPTEG_FROM_L3",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x10060",
|
||||
"EventName": "PM_TM_TRANS_RUN_CYC",
|
||||
"BriefDescription": "run cycles in transactional state"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1E04C",
|
||||
"EventName": "PM_DPTEG_FROM_LL4",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x45050",
|
||||
"EventName": "PM_1FLOP_CMPL",
|
||||
"BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed"
|
||||
}
|
||||
]
|
||||
]
|
||||
@@ -1,272 +1,232 @@
|
||||
[
|
||||
{,
|
||||
"EventCode": "0x10028",
|
||||
"EventName": "PM_STALL_END_ICT_EMPTY",
|
||||
"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this thread",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1C04E",
|
||||
"EventName": "PM_DATA_FROM_L2MISS_MOD",
|
||||
"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x14044",
|
||||
"EventName": "PM_INST_FROM_L3_NO_CONFLICT",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1404E",
|
||||
"EventName": "PM_INST_FROM_L2MISS",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1D142",
|
||||
"EventName": "PM_MRK_DATA_FROM_L3.1_ECO_SHR_CYC",
|
||||
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x15048",
|
||||
"EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1504A",
|
||||
"EventName": "PM_IPTEG_FROM_RL2L3_SHR",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1E058",
|
||||
"EventName": "PM_STCX_FAIL",
|
||||
"BriefDescription": "stcx failed",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1F15E",
|
||||
"EventName": "PM_MRK_PROBE_NOP_CMPL",
|
||||
"BriefDescription": "Marked probeNops completed",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x20112",
|
||||
"EventName": "PM_MRK_NTF_FIN",
|
||||
"BriefDescription": "Marked next to finish instruction finished",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x20016",
|
||||
"EventName": "PM_ST_FIN",
|
||||
"BriefDescription": "Store finish count. Includes speculative activity",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x20018",
|
||||
"EventName": "PM_ST_FWD",
|
||||
"BriefDescription": "Store forwards that finished",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2011C",
|
||||
"EventName": "PM_MRK_NTC_CYC",
|
||||
"BriefDescription": "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2E018",
|
||||
"EventName": "PM_CMPLU_STALL_VFXLONG",
|
||||
"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2E01C",
|
||||
"EventName": "PM_CMPLU_STALL_TLBIE",
|
||||
"BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2003E",
|
||||
"EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
|
||||
"BriefDescription": "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x24042",
|
||||
"EventName": "PM_INST_FROM_L3_MEPF",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2D14A",
|
||||
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
|
||||
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x25046",
|
||||
"EventName": "PM_IPTEG_FROM_RL2L3_MOD",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2504A",
|
||||
"EventName": "PM_IPTEG_FROM_RL4",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2504C",
|
||||
"EventName": "PM_IPTEG_FROM_MEMORY",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x201E6",
|
||||
"EventName": "PM_THRESH_EXC_32",
|
||||
"BriefDescription": "Threshold counter exceeded a value of 32",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x200F0",
|
||||
"EventName": "PM_ST_CMPL",
|
||||
"BriefDescription": "Stores completed from S2Q (2nd-level store queue).",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x200FE",
|
||||
"EventName": "PM_DATA_FROM_L2MISS",
|
||||
"BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
|
||||
"PublicDescription": ""
|
||||
"EventCode": "0x1E",
|
||||
"EventName": "PM_CYC",
|
||||
"BriefDescription": "Processor cycles"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x30010",
|
||||
"EventName": "PM_PMC2_OVERFLOW",
|
||||
"BriefDescription": "Overflow from counter 2",
|
||||
"PublicDescription": ""
|
||||
"BriefDescription": "Overflow from counter 2"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3C046",
|
||||
"EventName": "PM_DATA_FROM_L2.1_SHR",
|
||||
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x34042",
|
||||
"EventName": "PM_INST_FROM_L3_DISP_CONFLICT",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x34046",
|
||||
"EventName": "PM_INST_FROM_L2.1_SHR",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3504A",
|
||||
"EventName": "PM_IPTEG_FROM_RMEM",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3E048",
|
||||
"EventName": "PM_DPTEG_FROM_DL2L3_SHR",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3E04C",
|
||||
"EventName": "PM_DPTEG_FROM_DL4",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3C05A",
|
||||
"EventName": "PM_CMPLU_STALL_VDPLONG",
|
||||
"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3C05C",
|
||||
"EventName": "PM_CMPLU_STALL_VFXU",
|
||||
"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x30066",
|
||||
"EventName": "PM_LSU_FIN",
|
||||
"BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x300F0",
|
||||
"EventName": "PM_ST_MISS_L1",
|
||||
"BriefDescription": "Store Missed L1",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D010",
|
||||
"EventName": "PM_PMC1_SAVED",
|
||||
"BriefDescription": "PMC1 Rewind Value saved",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x40132",
|
||||
"EventName": "PM_MRK_LSU_FIN",
|
||||
"BriefDescription": "lsu marked instr PPC finish",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4C046",
|
||||
"EventName": "PM_DATA_FROM_L2.1_MOD",
|
||||
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x44042",
|
||||
"EventName": "PM_INST_FROM_L3",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4504A",
|
||||
"EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4E048",
|
||||
"EventName": "PM_DPTEG_FROM_DL2L3_MOD",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4E04C",
|
||||
"EventName": "PM_DPTEG_FROM_DMEM",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
|
||||
"PublicDescription": ""
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4405C",
|
||||
"EventName": "PM_CMPLU_STALL_VDP",
|
||||
"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector",
|
||||
"PublicDescription": ""
|
||||
"EventName": "PM_DATA_FROM_L21_SHR",
|
||||
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D05C",
|
||||
"EventName": "PM_DP_QP_FLOP_CMPL",
|
||||
"BriefDescription": "Double-Precion or Quad-Precision instruction completed",
|
||||
"PublicDescription": ""
|
||||
"BriefDescription": "Double-Precion or Quad-Precision instruction completed"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4E04C",
|
||||
"EventName": "PM_DPTEG_FROM_DMEM",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x20016",
|
||||
"EventName": "PM_ST_FIN",
|
||||
"BriefDescription": "Store finish count. Includes speculative activity"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x44042",
|
||||
"EventName": "PM_INST_FROM_L3",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1504A",
|
||||
"EventName": "PM_IPTEG_FROM_RL2L3_SHR",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x40132",
|
||||
"EventName": "PM_MRK_LSU_FIN",
|
||||
"BriefDescription": "lsu marked instr PPC finish"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3C05C",
|
||||
"EventName": "PM_CMPLU_STALL_VFXU",
|
||||
"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x30066",
|
||||
"EventName": "PM_LSU_FIN",
|
||||
"BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2011C",
|
||||
"EventName": "PM_MRK_NTC_CYC",
|
||||
"BriefDescription": "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3E048",
|
||||
"EventName": "PM_DPTEG_FROM_DL2L3_SHR",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2E018",
|
||||
"EventName": "PM_CMPLU_STALL_VFXLONG",
|
||||
"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1C04E",
|
||||
"EventName": "PM_DATA_FROM_L2MISS_MOD",
|
||||
"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x15048",
|
||||
"EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x34046",
|
||||
"EventName": "PM_INST_FROM_L21_SHR",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1E058",
|
||||
"EventName": "PM_STCX_FAIL",
|
||||
"BriefDescription": "stcx failed"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x20112",
|
||||
"EventName": "PM_MRK_NTF_FIN",
|
||||
"BriefDescription": "Marked next to finish instruction finished"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x300F0",
|
||||
"EventName": "PM_ST_MISS_L1",
|
||||
"BriefDescription": "Store Missed L1"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4C046",
|
||||
"EventName": "PM_DATA_FROM_L21_MOD",
|
||||
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2504A",
|
||||
"EventName": "PM_IPTEG_FROM_RL4",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2003E",
|
||||
"EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
|
||||
"BriefDescription": "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x201E6",
|
||||
"EventName": "PM_THRESH_EXC_32",
|
||||
"BriefDescription": "Threshold counter exceeded a value of 32"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4405C",
|
||||
"EventName": "PM_CMPLU_STALL_VDP",
|
||||
"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4D010",
|
||||
"EventName": "PM_PMC1_SAVED",
|
||||
"BriefDescription": "PMC1 Rewind Value saved"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x200FE",
|
||||
"EventName": "PM_DATA_FROM_L2MISS",
|
||||
"BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2D14A",
|
||||
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
|
||||
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x10028",
|
||||
"EventName": "PM_STALL_END_ICT_EMPTY",
|
||||
"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this thread"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2504C",
|
||||
"EventName": "PM_IPTEG_FROM_MEMORY",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4504A",
|
||||
"EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1404E",
|
||||
"EventName": "PM_INST_FROM_L2MISS",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x34042",
|
||||
"EventName": "PM_INST_FROM_L3_DISP_CONFLICT",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4E048",
|
||||
"EventName": "PM_DPTEG_FROM_DL2L3_MOD",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x200F0",
|
||||
"EventName": "PM_ST_CMPL",
|
||||
"BriefDescription": "Stores completed from S2Q (2nd-level store queue)."
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x4E05C",
|
||||
"EventName": "PM_LSU_REJECT_LHS",
|
||||
"BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)",
|
||||
"PublicDescription": ""
|
||||
"BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x14044",
|
||||
"EventName": "PM_INST_FROM_L3_NO_CONFLICT",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3E04C",
|
||||
"EventName": "PM_DPTEG_FROM_DL4",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1F15E",
|
||||
"EventName": "PM_MRK_PROBE_NOP_CMPL",
|
||||
"BriefDescription": "Marked probeNops completed"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x20018",
|
||||
"EventName": "PM_ST_FWD",
|
||||
"BriefDescription": "Store forwards that finished"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x1D142",
|
||||
"EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC",
|
||||
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x24042",
|
||||
"EventName": "PM_INST_FROM_L3_MEPF",
|
||||
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x25046",
|
||||
"EventName": "PM_IPTEG_FROM_RL2L3_MOD",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3504A",
|
||||
"EventName": "PM_IPTEG_FROM_RMEM",
|
||||
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x3C05A",
|
||||
"EventName": "PM_CMPLU_STALL_VDPLONG",
|
||||
"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle"
|
||||
},
|
||||
{,
|
||||
"EventCode": "0x2E01C",
|
||||
"EventName": "PM_CMPLU_STALL_TLBIE",
|
||||
"BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2"
|
||||
}
|
||||
]
|
||||
]
|
||||
Reference in New Issue
Block a user