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phy: Add lan966x ethernet serdes PHY driver

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Add the Microchip lan966x ethernet serdes PHY driver for interfaces
available in the lan966x SoC.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20211116100818.1615762-4-horatiu.vultur@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Horatiu Vultur
2021-11-16 11:08:18 +01:00
committed by Vinod Koul
parent ea8a163e02
commit 305524902a
4 changed files with 766 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/phy/microchip/Kconfig
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@@ -11,3 +11,11 @@ config PHY_SPARX5_SERDES
depends on HAS_IOMEM
help
Enable this for support of the 10G/25G SerDes on Microchip Sparx5.
config PHY_LAN966X_SERDES
tristate "SerDes PHY driver for Microchip LAN966X"
select GENERIC_PHY
depends on OF
depends on MFD_SYSCON
help
Enable this for supporting SerDes muxing with Microchip LAN966X

1
drivers/phy/microchip/Makefile
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@@ -4,3 +4,4 @@
#
obj-$(CONFIG_PHY_SPARX5_SERDES) := sparx5_serdes.o
obj-$(CONFIG_PHY_LAN966X_SERDES) := lan966x_serdes.o

548
drivers/phy/microchip/lan966x_serdes.c Normal file
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File diff suppressed because it is too large Load Diff

209
drivers/phy/microchip/lan966x_serdes_regs.h Normal file
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@@ -0,0 +1,209 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _LAN966X_SERDES_REGS_H_
#define _LAN966X_SERDES_REGS_H_
#include <linux/bitfield.h>
#include <linux/types.h>
#include <linux/bug.h>
enum lan966x_target {
TARGET_HSIO = 32,
NUM_TARGETS = 66
};
#define __REG(...) __VA_ARGS__
/* HSIO:SD:SD_CFG */
#define HSIO_SD_CFG(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 0, 0, 1, 4)
#define HSIO_SD_CFG_PHY_RESET BIT(27)
#define HSIO_SD_CFG_PHY_RESET_SET(x)\
FIELD_PREP(HSIO_SD_CFG_PHY_RESET, x)
#define HSIO_SD_CFG_PHY_RESET_GET(x)\
FIELD_GET(HSIO_SD_CFG_PHY_RESET, x)
#define HSIO_SD_CFG_TX_RESET BIT(18)
#define HSIO_SD_CFG_TX_RESET_SET(x)\
FIELD_PREP(HSIO_SD_CFG_TX_RESET, x)
#define HSIO_SD_CFG_TX_RESET_GET(x)\
FIELD_GET(HSIO_SD_CFG_TX_RESET, x)
#define HSIO_SD_CFG_TX_RATE GENMASK(17, 16)
#define HSIO_SD_CFG_TX_RATE_SET(x)\
FIELD_PREP(HSIO_SD_CFG_TX_RATE, x)
#define HSIO_SD_CFG_TX_RATE_GET(x)\
FIELD_GET(HSIO_SD_CFG_TX_RATE, x)
#define HSIO_SD_CFG_TX_INVERT BIT(15)
#define HSIO_SD_CFG_TX_INVERT_SET(x)\
FIELD_PREP(HSIO_SD_CFG_TX_INVERT, x)
#define HSIO_SD_CFG_TX_INVERT_GET(x)\
FIELD_GET(HSIO_SD_CFG_TX_INVERT, x)
#define HSIO_SD_CFG_TX_EN BIT(14)
#define HSIO_SD_CFG_TX_EN_SET(x)\
FIELD_PREP(HSIO_SD_CFG_TX_EN, x)
#define HSIO_SD_CFG_TX_EN_GET(x)\
FIELD_GET(HSIO_SD_CFG_TX_EN, x)
#define HSIO_SD_CFG_TX_DATA_EN BIT(12)
#define HSIO_SD_CFG_TX_DATA_EN_SET(x)\
FIELD_PREP(HSIO_SD_CFG_TX_DATA_EN, x)
#define HSIO_SD_CFG_TX_DATA_EN_GET(x)\
FIELD_GET(HSIO_SD_CFG_TX_DATA_EN, x)
#define HSIO_SD_CFG_TX_CM_EN BIT(11)
#define HSIO_SD_CFG_TX_CM_EN_SET(x)\
FIELD_PREP(HSIO_SD_CFG_TX_CM_EN, x)
#define HSIO_SD_CFG_TX_CM_EN_GET(x)\
FIELD_GET(HSIO_SD_CFG_TX_CM_EN, x)
#define HSIO_SD_CFG_LANE_10BIT_SEL BIT(10)
#define HSIO_SD_CFG_LANE_10BIT_SEL_SET(x)\
FIELD_PREP(HSIO_SD_CFG_LANE_10BIT_SEL, x)
#define HSIO_SD_CFG_LANE_10BIT_SEL_GET(x)\
FIELD_GET(HSIO_SD_CFG_LANE_10BIT_SEL, x)
#define HSIO_SD_CFG_RX_TERM_EN BIT(9)
#define HSIO_SD_CFG_RX_TERM_EN_SET(x)\
FIELD_PREP(HSIO_SD_CFG_RX_TERM_EN, x)
#define HSIO_SD_CFG_RX_TERM_EN_GET(x)\
FIELD_GET(HSIO_SD_CFG_RX_TERM_EN, x)
#define HSIO_SD_CFG_RX_RESET BIT(8)
#define HSIO_SD_CFG_RX_RESET_SET(x)\
FIELD_PREP(HSIO_SD_CFG_RX_RESET, x)
#define HSIO_SD_CFG_RX_RESET_GET(x)\
FIELD_GET(HSIO_SD_CFG_RX_RESET, x)
#define HSIO_SD_CFG_RX_RATE GENMASK(7, 6)
#define HSIO_SD_CFG_RX_RATE_SET(x)\
FIELD_PREP(HSIO_SD_CFG_RX_RATE, x)
#define HSIO_SD_CFG_RX_RATE_GET(x)\
FIELD_GET(HSIO_SD_CFG_RX_RATE, x)
#define HSIO_SD_CFG_RX_PLL_EN BIT(5)
#define HSIO_SD_CFG_RX_PLL_EN_SET(x)\
FIELD_PREP(HSIO_SD_CFG_RX_PLL_EN, x)
#define HSIO_SD_CFG_RX_PLL_EN_GET(x)\
FIELD_GET(HSIO_SD_CFG_RX_PLL_EN, x)
#define HSIO_SD_CFG_RX_INVERT BIT(3)
#define HSIO_SD_CFG_RX_INVERT_SET(x)\
FIELD_PREP(HSIO_SD_CFG_RX_INVERT, x)
#define HSIO_SD_CFG_RX_INVERT_GET(x)\
FIELD_GET(HSIO_SD_CFG_RX_INVERT, x)
#define HSIO_SD_CFG_RX_DATA_EN BIT(2)
#define HSIO_SD_CFG_RX_DATA_EN_SET(x)\
FIELD_PREP(HSIO_SD_CFG_RX_DATA_EN, x)
#define HSIO_SD_CFG_RX_DATA_EN_GET(x)\
FIELD_GET(HSIO_SD_CFG_RX_DATA_EN, x)
#define HSIO_SD_CFG_LANE_LOOPBK_EN BIT(0)
#define HSIO_SD_CFG_LANE_LOOPBK_EN_SET(x)\
FIELD_PREP(HSIO_SD_CFG_LANE_LOOPBK_EN, x)
#define HSIO_SD_CFG_LANE_LOOPBK_EN_GET(x)\
FIELD_GET(HSIO_SD_CFG_LANE_LOOPBK_EN, x)
/* HSIO:SD:MPLL_CFG */
#define HSIO_MPLL_CFG(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 8, 0, 1, 4)
#define HSIO_MPLL_CFG_REF_SSP_EN BIT(18)
#define HSIO_MPLL_CFG_REF_SSP_EN_SET(x)\
FIELD_PREP(HSIO_MPLL_CFG_REF_SSP_EN, x)
#define HSIO_MPLL_CFG_REF_SSP_EN_GET(x)\
FIELD_GET(HSIO_MPLL_CFG_REF_SSP_EN, x)
#define HSIO_MPLL_CFG_REF_CLKDIV2 BIT(17)
#define HSIO_MPLL_CFG_REF_CLKDIV2_SET(x)\
FIELD_PREP(HSIO_MPLL_CFG_REF_CLKDIV2, x)
#define HSIO_MPLL_CFG_REF_CLKDIV2_GET(x)\
FIELD_GET(HSIO_MPLL_CFG_REF_CLKDIV2, x)
#define HSIO_MPLL_CFG_MPLL_EN BIT(16)
#define HSIO_MPLL_CFG_MPLL_EN_SET(x)\
FIELD_PREP(HSIO_MPLL_CFG_MPLL_EN, x)
#define HSIO_MPLL_CFG_MPLL_EN_GET(x)\
FIELD_GET(HSIO_MPLL_CFG_MPLL_EN, x)
#define HSIO_MPLL_CFG_MPLL_MULTIPLIER GENMASK(6, 0)
#define HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(x)\
FIELD_PREP(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)
#define HSIO_MPLL_CFG_MPLL_MULTIPLIER_GET(x)\
FIELD_GET(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)
/* HSIO:SD:SD_STAT */
#define HSIO_SD_STAT(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 12, 0, 1, 4)
#define HSIO_SD_STAT_MPLL_STATE BIT(6)
#define HSIO_SD_STAT_MPLL_STATE_SET(x)\
FIELD_PREP(HSIO_SD_STAT_MPLL_STATE, x)
#define HSIO_SD_STAT_MPLL_STATE_GET(x)\
FIELD_GET(HSIO_SD_STAT_MPLL_STATE, x)
#define HSIO_SD_STAT_TX_STATE BIT(5)
#define HSIO_SD_STAT_TX_STATE_SET(x)\
FIELD_PREP(HSIO_SD_STAT_TX_STATE, x)
#define HSIO_SD_STAT_TX_STATE_GET(x)\
FIELD_GET(HSIO_SD_STAT_TX_STATE, x)
#define HSIO_SD_STAT_TX_CM_STATE BIT(2)
#define HSIO_SD_STAT_TX_CM_STATE_SET(x)\
FIELD_PREP(HSIO_SD_STAT_TX_CM_STATE, x)
#define HSIO_SD_STAT_TX_CM_STATE_GET(x)\
FIELD_GET(HSIO_SD_STAT_TX_CM_STATE, x)
#define HSIO_SD_STAT_RX_PLL_STATE BIT(0)
#define HSIO_SD_STAT_RX_PLL_STATE_SET(x)\
FIELD_PREP(HSIO_SD_STAT_RX_PLL_STATE, x)
#define HSIO_SD_STAT_RX_PLL_STATE_GET(x)\
FIELD_GET(HSIO_SD_STAT_RX_PLL_STATE, x)
/* HSIO:HW_CFGSTAT:HW_CFG */
#define HSIO_HW_CFG __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 0, 0, 1, 4)
#define HSIO_HW_CFG_RGMII_1_CFG BIT(15)
#define HSIO_HW_CFG_RGMII_1_CFG_SET(x)\
(((x) << 15) & GENMASK(15, 15))
#define HSIO_HW_CFG_RGMII_1_CFG_GET(x)\
FIELD_GET(HSIO_HW_CFG_RGMII_1_CFG, x)
#define HSIO_HW_CFG_RGMII_0_CFG BIT(14)
#define HSIO_HW_CFG_RGMII_0_CFG_SET(x)\
(((x) << 14) & GENMASK(14, 14))
#define HSIO_HW_CFG_RGMII_0_CFG_GET(x)\
FIELD_GET(HSIO_HW_CFG_RGMII_0_CFG, x)
#define HSIO_HW_CFG_RGMII_ENA GENMASK(13, 12)
#define HSIO_HW_CFG_RGMII_ENA_SET(x)\
(((x) << 12) & GENMASK(13, 12))
#define HSIO_HW_CFG_RGMII_ENA_GET(x)\
FIELD_GET(HSIO_HW_CFG_RGMII_ENA, x)
#define HSIO_HW_CFG_SD6G_0_CFG BIT(11)
#define HSIO_HW_CFG_SD6G_0_CFG_SET(x)\
(((x) << 11) & GENMASK(11, 11))
#define HSIO_HW_CFG_SD6G_0_CFG_GET(x)\
FIELD_GET(HSIO_HW_CFG_SD6G_0_CFG, x)
#define HSIO_HW_CFG_SD6G_1_CFG BIT(10)
#define HSIO_HW_CFG_SD6G_1_CFG_SET(x)\
(((x) << 10) & GENMASK(10, 10))
#define HSIO_HW_CFG_SD6G_1_CFG_GET(x)\
FIELD_GET(HSIO_HW_CFG_SD6G_1_CFG, x)
#define HSIO_HW_CFG_GMII_ENA GENMASK(9, 2)
#define HSIO_HW_CFG_GMII_ENA_SET(x)\
(((x) << 2) & GENMASK(9, 2))
#define HSIO_HW_CFG_GMII_ENA_GET(x)\
FIELD_GET(HSIO_HW_CFG_GMII_ENA, x)
#define HSIO_HW_CFG_QSGMII_ENA GENMASK(1, 0)
#define HSIO_HW_CFG_QSGMII_ENA_SET(x)\
((x) & GENMASK(1, 0))
#define HSIO_HW_CFG_QSGMII_ENA_GET(x)\
FIELD_GET(HSIO_HW_CFG_QSGMII_ENA, x)
#endif /* _LAN966X_HSIO_REGS_H_ */