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arm64: dts: ti: k3-j7200: Fix the L2 cache sets

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[ Upstream commit d0c826106f ]

A72's L2 cache[1] on J7200[2] is 1MB. A72's L2 is fixed line length of
64 bytes and 16-way set-associative cache structure.

1MB of L2 / 64 (line length) = 16384 ways
16384 ways / 16 = 1024 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
[2] https://www.ti.com/lit/pdf/spruiu1

Fixes: d361ed8845 ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211113043638.4358-1-nm@ti.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Nishanth Menon
2021-11-12 22:36:38 -06:00
committed by Greg Kroah-Hartman
parent f277978d6c
commit 2dcfa3c765
1 changed files with 1 additions and 1 deletions
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2
arch/arm64/boot/dts/ti/k3-j7200.dtsi
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@@ -84,7 +84,7 @@
cache-level = <2>;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <2048>;
cache-sets = <1024>;
next-level-cache = <&msmc_l3>;
};