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net: dsa: add Broadcom SF2 switch driver
Add support for the Broadcom Starfigther 2 switch chip using a DSA driver. This switch driver supports the following features: - configuration of the external switch port interface: MII, RevMII, RGMII and RGMII_NO_ID are supported - support for the per-port MIB counters - support for link interrupts for special ports (e.g: MoCA) - powering up/down of switch memories to conserve power when ports are unused Finally, update the compatible property for the DSA core code to match our switch top-level compatible node. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Florian Fainelli
committed by
David S. Miller
David S. Miller
parent
5037d532b8
commit
246d7f773c
@@ -36,4 +36,15 @@ config NET_DSA_MV88E6123_61_65
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This enables support for the Marvell 88E6123/6161/6165
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ethernet switch chips.
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config NET_DSA_BCM_SF2
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tristate "Broadcom Starfighter 2 Ethernet switch support"
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select NET_DSA
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select NET_DSA_TAG_BRCM
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select FIXED_PHY if NET_DSA_BCM_SF2=y
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select BCM7XXX_PHY
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select MDIO_BCM_UNIMAC
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---help---
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This enables support for the Broadcom Starfighter 2 Ethernet
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switch chips.
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endmenu
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@@ -7,3 +7,4 @@ endif
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ifdef CONFIG_NET_DSA_MV88E6131
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mv88e6xxx_drv-y += mv88e6131.o
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endif
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obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm_sf2.o
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626
drivers/net/dsa/bcm_sf2.c
Normal file
626
drivers/net/dsa/bcm_sf2.c
Normal file
File diff suppressed because it is too large
Load Diff
140
drivers/net/dsa/bcm_sf2.h
Normal file
140
drivers/net/dsa/bcm_sf2.h
Normal file
@@ -0,0 +1,140 @@
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/*
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* Broadcom Starfighter2 private context
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*
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* Copyright (C) 2014, Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __BCM_SF2_H
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#define __BCM_SF2_H
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/mii.h>
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#include <net/dsa.h>
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#include "bcm_sf2_regs.h"
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struct bcm_sf2_hw_params {
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u16 top_rev;
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u16 core_rev;
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u32 num_gphy;
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u8 num_acb_queue;
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u8 num_rgmii;
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u8 num_ports;
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u8 fcb_pause_override:1;
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u8 acb_packets_inflight:1;
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};
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#define BCM_SF2_REGS_NAME {\
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"core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
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}
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#define BCM_SF2_REGS_NUM 6
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struct bcm_sf2_port_status {
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unsigned int link;
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};
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struct bcm_sf2_priv {
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/* Base registers, keep those in order with BCM_SF2_REGS_NAME */
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void __iomem *core;
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void __iomem *reg;
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void __iomem *intrl2_0;
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void __iomem *intrl2_1;
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void __iomem *fcb;
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void __iomem *acb;
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/* spinlock protecting access to the indirect registers */
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spinlock_t indir_lock;
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int irq0;
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int irq1;
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u32 irq0_stat;
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u32 irq0_mask;
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u32 irq1_stat;
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u32 irq1_mask;
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/* Mutex protecting access to the MIB counters */
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struct mutex stats_mutex;
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struct bcm_sf2_hw_params hw_params;
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struct bcm_sf2_port_status port_sts[DSA_MAX_PORTS];
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};
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struct bcm_sf2_hw_stats {
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const char *string;
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u16 reg;
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u8 sizeof_stat;
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};
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#define SF2_IO_MACRO(name) \
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static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
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{ \
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return __raw_readl(priv->name + off); \
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} \
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static inline void name##_writel(struct bcm_sf2_priv *priv, \
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u32 val, u32 off) \
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{ \
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__raw_writel(val, priv->name + off); \
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} \
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/* Accesses to 64-bits register requires us to latch the hi/lo pairs
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* using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
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* spinlock is automatically grabbed and released to provide relative
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* atomiticy with latched reads/writes.
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*/
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#define SF2_IO64_MACRO(name) \
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static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \
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{ \
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u32 indir, dir; \
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spin_lock(&priv->indir_lock); \
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indir = reg_readl(priv, REG_DIR_DATA_READ); \
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dir = __raw_readl(priv->name + off); \
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spin_unlock(&priv->indir_lock); \
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return (u64)indir << 32 | dir; \
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} \
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static inline void name##_writeq(struct bcm_sf2_priv *priv, u32 off, \
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u64 val) \
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{ \
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spin_lock(&priv->indir_lock); \
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reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \
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__raw_writel(lower_32_bits(val), priv->name + off); \
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spin_unlock(&priv->indir_lock); \
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}
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#define SWITCH_INTR_L2(which) \
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static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
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u32 mask) \
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{ \
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intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
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priv->irq##which##_mask &= ~(mask); \
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} \
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static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
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u32 mask) \
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{ \
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intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
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priv->irq##which##_mask |= (mask); \
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} \
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SF2_IO_MACRO(core);
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SF2_IO_MACRO(reg);
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SF2_IO64_MACRO(core);
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SF2_IO_MACRO(intrl2_0);
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SF2_IO_MACRO(intrl2_1);
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SF2_IO_MACRO(fcb);
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SF2_IO_MACRO(acb);
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SWITCH_INTR_L2(0);
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SWITCH_INTR_L2(1);
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#endif /* __BCM_SF2_H */
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227
drivers/net/dsa/bcm_sf2_regs.h
Normal file
227
drivers/net/dsa/bcm_sf2_regs.h
Normal file
@@ -0,0 +1,227 @@
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/*
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* Broadcom Starfighter 2 switch register defines
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*
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* Copyright (C) 2014, Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __BCM_SF2_REGS_H
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#define __BCM_SF2_REGS_H
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/* Register set relative to 'REG' */
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#define REG_SWITCH_CNTRL 0x00
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#define MDIO_MASTER_SEL (1 << 0)
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#define REG_SWITCH_STATUS 0x04
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#define REG_DIR_DATA_WRITE 0x08
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#define REG_DIR_DATA_READ 0x0C
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#define REG_SWITCH_REVISION 0x18
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#define SF2_REV_MASK 0xffff
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#define SWITCH_TOP_REV_SHIFT 16
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#define SWITCH_TOP_REV_MASK 0xffff
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#define REG_PHY_REVISION 0x1C
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#define REG_SPHY_CNTRL 0x2C
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#define IDDQ_BIAS (1 << 0)
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#define EXT_PWR_DOWN (1 << 1)
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#define FORCE_DLL_EN (1 << 2)
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#define IDDQ_GLOBAL_PWR (1 << 3)
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#define CK25_DIS (1 << 4)
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#define PHY_RESET (1 << 5)
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#define PHY_PHYAD_SHIFT 8
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#define PHY_PHYAD_MASK 0x1F
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#define REG_RGMII_0_BASE 0x34
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#define REG_RGMII_CNTRL 0x00
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#define REG_RGMII_IB_STATUS 0x04
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#define REG_RGMII_RX_CLOCK_DELAY_CNTRL 0x08
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#define REG_RGMII_CNTRL_SIZE 0x0C
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#define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_BASE + \
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((x) * REG_RGMII_CNTRL_SIZE))
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/* Relative to REG_RGMII_CNTRL */
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#define RGMII_MODE_EN (1 << 0)
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#define ID_MODE_DIS (1 << 1)
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#define PORT_MODE_SHIFT 2
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#define INT_EPHY (0 << PORT_MODE_SHIFT)
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#define INT_GPHY (1 << PORT_MODE_SHIFT)
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#define EXT_EPHY (2 << PORT_MODE_SHIFT)
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#define EXT_GPHY (3 << PORT_MODE_SHIFT)
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#define EXT_REVMII (4 << PORT_MODE_SHIFT)
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#define PORT_MODE_MASK 0x7
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#define RVMII_REF_SEL (1 << 5)
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#define RX_PAUSE_EN (1 << 6)
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#define TX_PAUSE_EN (1 << 7)
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#define TX_CLK_STOP_EN (1 << 8)
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#define LPI_COUNT_SHIFT 9
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#define LPI_COUNT_MASK 0x3F
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/* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
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#define INTRL2_CPU_STATUS 0x00
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#define INTRL2_CPU_SET 0x04
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#define INTRL2_CPU_CLEAR 0x08
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#define INTRL2_CPU_MASK_STATUS 0x0c
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#define INTRL2_CPU_MASK_SET 0x10
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#define INTRL2_CPU_MASK_CLEAR 0x14
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/* Shared INTRL2_0 and INTRL2_ interrupt sources macros */
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#define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
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#define P_LINK_DOWN_IRQ(x) (1 << (1 + (x)))
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#define P_ENERGY_ON_IRQ(x) (1 << (2 + (x)))
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#define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x)))
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#define P_GPHY_IRQ(x) (1 << (4 + (x)))
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#define P_NUM_IRQ 5
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#define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \
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P_LINK_DOWN_IRQ((x)) | \
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P_ENERGY_ON_IRQ((x)) | \
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P_ENERGY_OFF_IRQ((x)) | \
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P_GPHY_IRQ((x)))
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/* INTRL2_0 interrupt sources */
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#define P0_IRQ_OFF 0
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#define MEM_DOUBLE_IRQ (1 << 5)
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#define EEE_LPI_IRQ (1 << 6)
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#define P5_CPU_WAKE_IRQ (1 << 7)
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#define P8_CPU_WAKE_IRQ (1 << 8)
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#define P7_CPU_WAKE_IRQ (1 << 9)
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#define IEEE1588_IRQ (1 << 10)
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#define MDIO_ERR_IRQ (1 << 11)
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#define MDIO_DONE_IRQ (1 << 12)
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#define GISB_ERR_IRQ (1 << 13)
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#define UBUS_ERR_IRQ (1 << 14)
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#define FAILOVER_ON_IRQ (1 << 15)
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#define FAILOVER_OFF_IRQ (1 << 16)
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#define TCAM_SOFT_ERR_IRQ (1 << 17)
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/* INTRL2_1 interrupt sources */
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#define P7_IRQ_OFF 0
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#define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ)
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/* Register set relative to 'CORE' */
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#define CORE_G_PCTL_PORT0 0x00000
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#define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
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#define CORE_IMP_CTL 0x00020
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#define RX_DIS (1 << 0)
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#define TX_DIS (1 << 1)
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#define RX_BCST_EN (1 << 2)
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#define RX_MCST_EN (1 << 3)
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#define RX_UCST_EN (1 << 4)
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#define G_MISTP_STATE_SHIFT 5
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#define G_MISTP_NO_STP (0 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_DIS_STATE (1 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_BLOCK_STATE (2 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_LISTEN_STATE (3 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_LEARN_STATE (4 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_FWD_STATE (5 << G_MISTP_STATE_SHIFT)
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#define G_MISTP_STATE_MASK 0x7
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#define CORE_SWMODE 0x0002c
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#define SW_FWDG_MODE (1 << 0)
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#define SW_FWDG_EN (1 << 1)
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#define RTRY_LMT_DIS (1 << 2)
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#define CORE_STS_OVERRIDE_IMP 0x00038
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#define GMII_SPEED_UP_2G (1 << 6)
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#define MII_SW_OR (1 << 7)
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#define CORE_NEW_CTRL 0x00084
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#define IP_MC (1 << 0)
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#define OUTRANGEERR_DISCARD (1 << 1)
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#define INRANGEERR_DISCARD (1 << 2)
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#define CABLE_DIAG_LEN (1 << 3)
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#define OVERRIDE_AUTO_PD_WAR (1 << 4)
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#define EN_AUTO_PD_WAR (1 << 5)
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#define UC_FWD_EN (1 << 6)
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#define MC_FWD_EN (1 << 7)
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#define CORE_SWITCH_CTRL 0x00088
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#define MII_DUMB_FWDG_EN (1 << 6)
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#define CORE_SFT_LRN_CTRL 0x000f8
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#define SW_LEARN_CNTL(x) (1 << (x))
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#define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
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#define LINK_STS (1 << 0)
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#define DUPLX_MODE (1 << 1)
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#define SPEED_SHIFT 2
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#define SPEED_MASK 0x3
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#define RXFLOW_CNTL (1 << 4)
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#define TXFLOW_CNTL (1 << 5)
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#define SW_OVERRIDE (1 << 6)
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#define CORE_WATCHDOG_CTRL 0x001e4
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#define SOFTWARE_RESET (1 << 7)
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#define EN_CHIP_RST (1 << 6)
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#define EN_SW_RESET (1 << 4)
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#define CORE_LNKSTS 0x00400
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#define LNK_STS_MASK 0x1ff
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#define CORE_SPDSTS 0x00410
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#define SPDSTS_10 0
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#define SPDSTS_100 1
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#define SPDSTS_1000 2
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#define SPDSTS_SHIFT 2
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#define SPDSTS_MASK 0x3
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#define CORE_DUPSTS 0x00420
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#define CORE_DUPSTS_MASK 0x1ff
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#define CORE_PAUSESTS 0x00428
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#define PAUSESTS_TX_PAUSE_SHIFT 9
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#define CORE_GMNCFGCFG 0x0800
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#define RST_MIB_CNT (1 << 0)
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#define RXBPDU_EN (1 << 1)
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#define CORE_IMP0_PRT_ID 0x0804
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#define CORE_BRCM_HDR_CTRL 0x0080c
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#define BRCM_HDR_EN_P8 (1 << 0)
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#define BRCM_HDR_EN_P5 (1 << 1)
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#define BRCM_HDR_EN_P7 (1 << 2)
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#define CORE_BRCM_HDR_CTRL2 0x0828
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#define CORE_HL_PRTC_CTRL 0x0940
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#define ARP_EN (1 << 0)
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#define RARP_EN (1 << 1)
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#define DHCP_EN (1 << 2)
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#define ICMPV4_EN (1 << 3)
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#define ICMPV6_EN (1 << 4)
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#define ICMPV6_FWD_MODE (1 << 5)
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#define IGMP_DIP_EN (1 << 8)
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#define IGMP_RPTLVE_EN (1 << 9)
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#define IGMP_RTPLVE_FWD_MODE (1 << 10)
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#define IGMP_QRY_EN (1 << 11)
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#define IGMP_QRY_FWD_MODE (1 << 12)
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#define IGMP_UKN_EN (1 << 13)
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#define IGMP_UKN_FWD_MODE (1 << 14)
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#define MLD_RPTDONE_EN (1 << 15)
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#define MLD_RPTDONE_FWD_MODE (1 << 16)
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#define MLD_QRY_EN (1 << 17)
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#define MLD_QRY_FWD_MODE (1 << 18)
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#define CORE_RST_MIB_CNT_EN 0x0950
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#define CORE_BRCM_HDR_RX_DIS 0x0980
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#define CORE_BRCM_HDR_TX_DIS 0x0988
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#define CORE_MEM_PSM_VDD_CTRL 0x2380
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#define P_TXQ_PSM_VDD_SHIFT 2
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#define P_TXQ_PSM_VDD_MASK 0x3
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#define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
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((x) * P_TXQ_PSM_VDD_SHIFT))
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#define CORE_P0_MIB_OFFSET 0x8000
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#define P_MIB_SIZE 0x400
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#define CORE_P_MIB_OFFSET(x) (CORE_P0_MIB_OFFSET + (x) * P_MIB_SIZE)
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#define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
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#define PORT_VLAN_CTRL_MASK 0x1ff
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#endif /* __BCM_SF2_REGS_H */
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@@ -635,6 +635,7 @@ struct packet_type dsa_pack_type __read_mostly = {
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};
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static const struct of_device_id dsa_of_match_table[] = {
|
||||
{ .compatible = "brcm,bcm7445-switch-v4.0" },
|
||||
{ .compatible = "marvell,dsa", },
|
||||
{}
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user