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Staging: wavelan: delete the driver
It has sat in the staging directory since October of 2009, and no one has stepped up to take it over, so odds are, no one cares about it anymore. So, it is now deleted as scheduled, and documented in the TODO file. Cc: John W. Linville <linville@tuxdriver.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Greg Kroah-Hartman
@@ -125,8 +125,6 @@ source "drivers/staging/batman-adv/Kconfig"
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source "drivers/staging/samsung-laptop/Kconfig"
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source "drivers/staging/wavelan/Kconfig"
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source "drivers/staging/netwave/Kconfig"
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source "drivers/staging/sm7xx/Kconfig"
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@@ -43,8 +43,6 @@ obj-$(CONFIG_WLAGS49_H2) += wlags49_h2/
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obj-$(CONFIG_WLAGS49_H25) += wlags49_h25/
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obj-$(CONFIG_BATMAN_ADV) += batman-adv/
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obj-$(CONFIG_SAMSUNG_LAPTOP) += samsung-laptop/
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obj-$(CONFIG_WAVELAN) += wavelan/
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obj-$(CONFIG_PCMCIA_WAVELAN) += wavelan/
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obj-$(CONFIG_PCMCIA_NETWAVE) += netwave/
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obj-$(CONFIG_FB_SM7XX) += sm7xx/
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obj-$(CONFIG_DT3155) += dt3155/
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@@ -1,38 +0,0 @@
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config WAVELAN
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tristate "AT&T/Lucent old WaveLAN & DEC RoamAbout DS ISA support"
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depends on ISA && WLAN
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select WIRELESS_EXT
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select WEXT_SPY
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select WEXT_PRIV
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---help---
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The Lucent WaveLAN (formerly NCR and AT&T; or DEC RoamAbout DS) is
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a Radio LAN (wireless Ethernet-like Local Area Network) using the
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radio frequencies 900 MHz and 2.4 GHz.
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If you want to use an ISA WaveLAN card under Linux, say Y and read
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the Ethernet-HOWTO, available from
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<http://www.tldp.org/docs.html#howto>. Some more specific
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information is contained in
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<file:Documentation/networking/wavelan.txt> and in the source code
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<file:drivers/net/wireless/wavelan.p.h>.
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You will also need the wireless tools package available from
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<http://www.hpl.hp.com/personal/Jean_Tourrilhes/Linux/Tools.html>.
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Please read the man pages contained therein.
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To compile this driver as a module, choose M here: the module will be
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called wavelan.
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config PCMCIA_WAVELAN
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tristate "AT&T/Lucent old WaveLAN Pcmcia wireless support"
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depends on PCMCIA && WLAN
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select WIRELESS_EXT
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select WEXT_SPY
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select WEXT_PRIV
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help
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Say Y here if you intend to attach an AT&T/Lucent Wavelan PCMCIA
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(PC-card) wireless Ethernet networking card to your computer. This
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driver is for the non-IEEE-802.11 Wavelan cards.
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To compile this driver as a module, choose M here: the module will be
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called wavelan_cs. If unsure, say N.
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@@ -1,2 +0,0 @@
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obj-$(CONFIG_WAVELAN) += wavelan.o
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obj-$(CONFIG_PCMCIA_WAVELAN) += wavelan_cs.o
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@@ -1,7 +0,0 @@
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TODO:
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- step up and maintain this driver to ensure that it continues
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to work. Having the hardware for this is pretty much a
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requirement. If this does not happen, the will be removed in
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the 2.6.35 kernel release.
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Please send patches to Greg Kroah-Hartman <greg@kroah.com>.
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@@ -1,397 +0,0 @@
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/*
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* Intel 82586 IEEE 802.3 Ethernet LAN Coprocessor.
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*
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* See:
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* Intel Microcommunications 1991
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* p1-1 to p1-37
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* Intel order No. 231658
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* ISBN 1-55512-119-5
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*
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* Unfortunately, the above chapter mentions neither
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* the System Configuration Pointer (SCP) nor the
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* Intermediate System Configuration Pointer (ISCP),
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* so we probably need to look elsewhere for the
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* whole story -- some recommend the "Intel LAN
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* Components manual" but I have neither a copy
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* nor a full reference. But "elsewhere" may be
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* in the same publication...
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* The description of a later device, the
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* "82596CA High-Performance 32-Bit Local Area Network
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* Coprocessor", (ibid. p1-38 to p1-109) does mention
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* the SCP and ISCP and also has an i82586 compatibility
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* mode. Even more useful is "AP-235 An 82586 Data Link
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* Driver" (ibid. p1-337 to p1-417).
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*/
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#define I82586_MEMZ (64 * 1024)
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#define I82586_SCP_ADDR (I82586_MEMZ - sizeof(scp_t))
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#define ADDR_LEN 6
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#define I82586NULL 0xFFFF
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#define toff(t, p, f) (unsigned short)((void *)(&((t *)((void *)0 + (p)))->f) - (void *)0)
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/*
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* System Configuration Pointer (SCP).
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*/
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typedef struct scp_t scp_t;
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struct scp_t {
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unsigned short scp_sysbus; /* 82586 bus width: */
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#define SCP_SY_16BBUS (0x0 << 0) /* 16 bits */
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#define SCP_SY_8BBUS (0x1 << 0) /* 8 bits. */
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unsigned short scp_junk[2]; /* Unused */
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unsigned short scp_iscpl; /* lower 16 bits of ISCP_ADDR */
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unsigned short scp_iscph; /* upper 16 bits of ISCP_ADDR */
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};
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/*
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* Intermediate System Configuration Pointer (ISCP).
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*/
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typedef struct iscp_t iscp_t;
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struct iscp_t {
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unsigned short iscp_busy; /* set by CPU before first CA, */
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/* cleared by 82586 after read. */
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unsigned short iscp_offset; /* offset of SCB */
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unsigned short iscp_basel; /* base of SCB */
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unsigned short iscp_baseh; /* " */
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};
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/*
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* System Control Block (SCB).
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* The 82586 writes its status to scb_status and then
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* raises an interrupt to alert the CPU.
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* The CPU writes a command to scb_command and
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* then issues a Channel Attention (CA) to alert the 82586.
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*/
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typedef struct scb_t scb_t;
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struct scb_t {
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unsigned short scb_status; /* Status of 82586 */
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#define SCB_ST_INT (0xF << 12) /* Some of: */
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#define SCB_ST_CX (0x1 << 15) /* Cmd completed */
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#define SCB_ST_FR (0x1 << 14) /* Frame received */
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#define SCB_ST_CNA (0x1 << 13) /* Cmd unit not active */
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#define SCB_ST_RNR (0x1 << 12) /* Rcv unit not ready */
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#define SCB_ST_JUNK0 (0x1 << 11) /* 0 */
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#define SCB_ST_CUS (0x7 << 8) /* Cmd unit status */
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#define SCB_ST_CUS_IDLE (0 << 8) /* Idle */
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#define SCB_ST_CUS_SUSP (1 << 8) /* Suspended */
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#define SCB_ST_CUS_ACTV (2 << 8) /* Active */
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#define SCB_ST_JUNK1 (0x1 << 7) /* 0 */
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#define SCB_ST_RUS (0x7 << 4) /* Rcv unit status */
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#define SCB_ST_RUS_IDLE (0 << 4) /* Idle */
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#define SCB_ST_RUS_SUSP (1 << 4) /* Suspended */
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#define SCB_ST_RUS_NRES (2 << 4) /* No resources */
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#define SCB_ST_RUS_RDY (4 << 4) /* Ready */
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unsigned short scb_command; /* Next command */
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#define SCB_CMD_ACK_CX (0x1 << 15) /* Ack cmd completion */
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#define SCB_CMD_ACK_FR (0x1 << 14) /* Ack frame received */
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#define SCB_CMD_ACK_CNA (0x1 << 13) /* Ack CU not active */
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#define SCB_CMD_ACK_RNR (0x1 << 12) /* Ack RU not ready */
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#define SCB_CMD_JUNKX (0x1 << 11) /* Unused */
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#define SCB_CMD_CUC (0x7 << 8) /* Command Unit command */
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#define SCB_CMD_CUC_NOP (0 << 8) /* Nop */
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#define SCB_CMD_CUC_GO (1 << 8) /* Start cbl_offset */
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#define SCB_CMD_CUC_RES (2 << 8) /* Resume execution */
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#define SCB_CMD_CUC_SUS (3 << 8) /* Suspend " */
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#define SCB_CMD_CUC_ABT (4 << 8) /* Abort " */
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#define SCB_CMD_RESET (0x1 << 7) /* Reset chip (hardware) */
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#define SCB_CMD_RUC (0x7 << 4) /* Receive Unit command */
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#define SCB_CMD_RUC_NOP (0 << 4) /* Nop */
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#define SCB_CMD_RUC_GO (1 << 4) /* Start rfa_offset */
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#define SCB_CMD_RUC_RES (2 << 4) /* Resume reception */
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#define SCB_CMD_RUC_SUS (3 << 4) /* Suspend " */
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#define SCB_CMD_RUC_ABT (4 << 4) /* Abort " */
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unsigned short scb_cbl_offset; /* Offset of first command unit */
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/* Action Command */
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unsigned short scb_rfa_offset; /* Offset of first Receive */
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/* Frame Descriptor in the */
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/* Receive Frame Area */
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unsigned short scb_crcerrs; /* Properly aligned frames */
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/* received with a CRC error */
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unsigned short scb_alnerrs; /* Misaligned frames received */
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/* with a CRC error */
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unsigned short scb_rscerrs; /* Frames lost due to no space */
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unsigned short scb_ovrnerrs; /* Frames lost due to slow bus */
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};
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#define scboff(p, f) toff(scb_t, p, f)
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/*
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* The eight Action Commands.
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*/
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typedef enum acmd_e acmd_e;
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enum acmd_e {
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acmd_nop = 0, /* Do nothing */
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acmd_ia_setup = 1, /* Load an (ethernet) address into the */
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/* 82586 */
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acmd_configure = 2, /* Update the 82586 operating parameters */
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acmd_mc_setup = 3, /* Load a list of (ethernet) multicast */
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/* addresses into the 82586 */
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acmd_transmit = 4, /* Transmit a frame */
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acmd_tdr = 5, /* Perform a Time Domain Reflectometer */
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/* test on the serial link */
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acmd_dump = 6, /* Copy 82586 registers to memory */
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acmd_diagnose = 7, /* Run an internal self test */
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};
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/*
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* Generic Action Command header.
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*/
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typedef struct ach_t ach_t;
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struct ach_t {
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unsigned short ac_status; /* Command status: */
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#define AC_SFLD_C (0x1 << 15) /* Command completed */
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#define AC_SFLD_B (0x1 << 14) /* Busy executing */
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#define AC_SFLD_OK (0x1 << 13) /* Completed error free */
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#define AC_SFLD_A (0x1 << 12) /* Command aborted */
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#define AC_SFLD_FAIL (0x1 << 11) /* Selftest failed */
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#define AC_SFLD_S10 (0x1 << 10) /* No carrier sense */
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/* during transmission */
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#define AC_SFLD_S9 (0x1 << 9) /* Tx unsuccessful: */
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/* (stopped) lost CTS */
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#define AC_SFLD_S8 (0x1 << 8) /* Tx unsuccessful: */
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/* (stopped) slow DMA */
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#define AC_SFLD_S7 (0x1 << 7) /* Tx deferred: */
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/* other link traffic */
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#define AC_SFLD_S6 (0x1 << 6) /* Heart Beat: collision */
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/* detect after last tx */
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#define AC_SFLD_S5 (0x1 << 5) /* Tx stopped: */
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/* excessive collisions */
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#define AC_SFLD_MAXCOL (0xF << 0) /* Collision count */
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unsigned short ac_command; /* Command specifier: */
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#define AC_CFLD_EL (0x1 << 15) /* End of command list */
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#define AC_CFLD_S (0x1 << 14) /* Suspend on completion */
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#define AC_CFLD_I (0x1 << 13) /* Interrupt on completion */
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#define AC_CFLD_CMD (0x7 << 0) /* acmd_e */
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unsigned short ac_link; /* Next Action Command */
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};
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#define acoff(p, f) toff(ach_t, p, f)
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/*
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* The Nop Action Command.
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*/
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typedef struct ac_nop_t ac_nop_t;
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struct ac_nop_t {
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ach_t nop_h;
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};
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/*
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* The IA-Setup Action Command.
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*/
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typedef struct ac_ias_t ac_ias_t;
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struct ac_ias_t {
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ach_t ias_h;
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unsigned char ias_addr[ADDR_LEN]; /* The (ethernet) address */
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};
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/*
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* The Configure Action Command.
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*/
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typedef struct ac_cfg_t ac_cfg_t;
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struct ac_cfg_t {
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ach_t cfg_h;
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unsigned char cfg_byte_cnt; /* Size foll data: 4-12 */
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#define AC_CFG_BYTE_CNT(v) (((v) & 0xF) << 0)
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unsigned char cfg_fifolim; /* FIFO threshold */
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#define AC_CFG_FIFOLIM(v) (((v) & 0xF) << 0)
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unsigned char cfg_byte8;
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#define AC_CFG_SAV_BF(v) (((v) & 0x1) << 7) /* Save rxd bad frames */
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#define AC_CFG_SRDY(v) (((v) & 0x1) << 6) /* SRDY/ARDY pin means */
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/* external sync. */
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unsigned char cfg_byte9;
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#define AC_CFG_ELPBCK(v) (((v) & 0x1) << 7) /* External loopback */
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#define AC_CFG_ILPBCK(v) (((v) & 0x1) << 6) /* Internal loopback */
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#define AC_CFG_PRELEN(v) (((v) & 0x3) << 4) /* Preamble length */
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#define AC_CFG_PLEN_2 0 /* 2 bytes */
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#define AC_CFG_PLEN_4 1 /* 4 bytes */
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#define AC_CFG_PLEN_8 2 /* 8 bytes */
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#define AC_CFG_PLEN_16 3 /* 16 bytes */
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#define AC_CFG_ALOC(v) (((v) & 0x1) << 3) /* Addr/len data is */
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/* explicit in buffers */
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#define AC_CFG_ADDRLEN(v) (((v) & 0x7) << 0) /* Bytes per address */
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unsigned char cfg_byte10;
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#define AC_CFG_BOFMET(v) (((v) & 0x1) << 7) /* Use alternate expo. */
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/* backoff method */
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#define AC_CFG_ACR(v) (((v) & 0x7) << 4) /* Accelerated cont. res. */
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#define AC_CFG_LINPRIO(v) (((v) & 0x7) << 0) /* Linear priority */
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unsigned char cfg_ifs; /* Interframe spacing */
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unsigned char cfg_slotl; /* Slot time (low byte) */
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unsigned char cfg_byte13;
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#define AC_CFG_RETRYNUM(v) (((v) & 0xF) << 4) /* Max. collision retry */
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#define AC_CFG_SLTTMHI(v) (((v) & 0x7) << 0) /* Slot time (high bits) */
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unsigned char cfg_byte14;
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#define AC_CFG_FLGPAD(v) (((v) & 0x1) << 7) /* Pad with HDLC flags */
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#define AC_CFG_BTSTF(v) (((v) & 0x1) << 6) /* Do HDLC bitstuffing */
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#define AC_CFG_CRC16(v) (((v) & 0x1) << 5) /* 16 bit CCITT CRC */
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#define AC_CFG_NCRC(v) (((v) & 0x1) << 4) /* Insert no CRC */
|
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#define AC_CFG_TNCRS(v) (((v) & 0x1) << 3) /* Tx even if no carrier */
|
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#define AC_CFG_MANCH(v) (((v) & 0x1) << 2) /* Manchester coding */
|
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#define AC_CFG_BCDIS(v) (((v) & 0x1) << 1) /* Disable broadcast */
|
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#define AC_CFG_PRM(v) (((v) & 0x1) << 0) /* Promiscuous mode */
|
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unsigned char cfg_byte15;
|
||||
#define AC_CFG_ICDS(v) (((v) & 0x1) << 7) /* Internal collision */
|
||||
/* detect source */
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#define AC_CFG_CDTF(v) (((v) & 0x7) << 4) /* Collision detect */
|
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/* filter in bit times */
|
||||
#define AC_CFG_ICSS(v) (((v) & 0x1) << 3) /* Internal carrier */
|
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/* sense source */
|
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#define AC_CFG_CSTF(v) (((v) & 0x7) << 0) /* Carrier sense */
|
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/* filter in bit times */
|
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unsigned short cfg_min_frm_len;
|
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#define AC_CFG_MNFRM(v) (((v) & 0xFF) << 0) /* Min. bytes/frame (<= 255) */
|
||||
};
|
||||
|
||||
/*
|
||||
* The MC-Setup Action Command.
|
||||
*/
|
||||
typedef struct ac_mcs_t ac_mcs_t;
|
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struct ac_mcs_t {
|
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ach_t mcs_h;
|
||||
unsigned short mcs_cnt; /* No. of bytes of MC addresses */
|
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#if 0
|
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unsigned char mcs_data[ADDR_LEN]; /* The first MC address .. */
|
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...
|
||||
#endif
|
||||
};
|
||||
|
||||
#define I82586_MAX_MULTICAST_ADDRESSES 128 /* Hardware hashed filter */
|
||||
|
||||
/*
|
||||
* The Transmit Action Command.
|
||||
*/
|
||||
typedef struct ac_tx_t ac_tx_t;
|
||||
struct ac_tx_t {
|
||||
ach_t tx_h;
|
||||
unsigned short tx_tbd_offset; /* Address of list of buffers. */
|
||||
#if 0
|
||||
Linux packets are passed down with the destination MAC address
|
||||
and length/type field already prepended to the data,
|
||||
so we do not need to insert it. Consistent with this
|
||||
we must also set the AC_CFG_ALOC(..) flag during the
|
||||
ac_cfg_t action command.
|
||||
unsigned char tx_addr[ADDR_LEN]; /* The frame dest. address */
|
||||
unsigned short tx_length; /* The frame length */
|
||||
#endif /* 0 */
|
||||
};
|
||||
|
||||
/*
|
||||
* The Time Domain Reflectometer Action Command.
|
||||
*/
|
||||
typedef struct ac_tdr_t ac_tdr_t;
|
||||
struct ac_tdr_t {
|
||||
ach_t tdr_h;
|
||||
unsigned short tdr_result; /* Result. */
|
||||
#define AC_TDR_LNK_OK (0x1 << 15) /* No link problem */
|
||||
#define AC_TDR_XCVR_PRB (0x1 << 14) /* Txcvr cable problem */
|
||||
#define AC_TDR_ET_OPN (0x1 << 13) /* Open on the link */
|
||||
#define AC_TDR_ET_SRT (0x1 << 12) /* Short on the link */
|
||||
#define AC_TDR_TIME (0x7FF << 0) /* Distance to problem */
|
||||
/* site in transmit */
|
||||
/* clock cycles */
|
||||
};
|
||||
|
||||
/*
|
||||
* The Dump Action Command.
|
||||
*/
|
||||
typedef struct ac_dmp_t ac_dmp_t;
|
||||
struct ac_dmp_t {
|
||||
ach_t dmp_h;
|
||||
unsigned short dmp_offset; /* Result. */
|
||||
};
|
||||
|
||||
/*
|
||||
* Size of the result of the dump command.
|
||||
*/
|
||||
#define DUMPBYTES 170
|
||||
|
||||
/*
|
||||
* The Diagnose Action Command.
|
||||
*/
|
||||
typedef struct ac_dgn_t ac_dgn_t;
|
||||
struct ac_dgn_t {
|
||||
ach_t dgn_h;
|
||||
};
|
||||
|
||||
/*
|
||||
* Transmit Buffer Descriptor (TBD).
|
||||
*/
|
||||
typedef struct tbd_t tbd_t;
|
||||
struct tbd_t {
|
||||
unsigned short tbd_status; /* Written by the CPU */
|
||||
#define TBD_STATUS_EOF (0x1 << 15) /* This TBD is the */
|
||||
/* last for this frame */
|
||||
#define TBD_STATUS_ACNT (0x3FFF << 0) /* Actual count of data */
|
||||
/* bytes in this buffer */
|
||||
unsigned short tbd_next_bd_offset; /* Next in list */
|
||||
unsigned short tbd_bufl; /* Buffer address (low) */
|
||||
unsigned short tbd_bufh; /* " " (high) */
|
||||
};
|
||||
|
||||
/*
|
||||
* Receive Buffer Descriptor (RBD).
|
||||
*/
|
||||
typedef struct rbd_t rbd_t;
|
||||
struct rbd_t {
|
||||
unsigned short rbd_status; /* Written by the 82586 */
|
||||
#define RBD_STATUS_EOF (0x1 << 15) /* This RBD is the */
|
||||
/* last for this frame */
|
||||
#define RBD_STATUS_F (0x1 << 14) /* ACNT field is valid */
|
||||
#define RBD_STATUS_ACNT (0x3FFF << 0) /* Actual no. of data */
|
||||
/* bytes in this buffer */
|
||||
unsigned short rbd_next_rbd_offset; /* Next rbd in list */
|
||||
unsigned short rbd_bufl; /* Data pointer (low) */
|
||||
unsigned short rbd_bufh; /* " " (high) */
|
||||
unsigned short rbd_el_size; /* EL+Data buf. size */
|
||||
#define RBD_EL (0x1 << 15) /* This BD is the */
|
||||
/* last in the list */
|
||||
#define RBD_SIZE (0x3FFF << 0) /* No. of bytes the */
|
||||
/* buffer can hold */
|
||||
};
|
||||
|
||||
#define rbdoff(p, f) toff(rbd_t, p, f)
|
||||
|
||||
/*
|
||||
* Frame Descriptor (FD).
|
||||
*/
|
||||
typedef struct fd_t fd_t;
|
||||
struct fd_t {
|
||||
unsigned short fd_status; /* Written by the 82586 */
|
||||
#define FD_STATUS_C (0x1 << 15) /* Completed storing frame */
|
||||
#define FD_STATUS_B (0x1 << 14) /* FD was consumed by RU */
|
||||
#define FD_STATUS_OK (0x1 << 13) /* Frame rxd successfully */
|
||||
#define FD_STATUS_S11 (0x1 << 11) /* CRC error */
|
||||
#define FD_STATUS_S10 (0x1 << 10) /* Alignment error */
|
||||
#define FD_STATUS_S9 (0x1 << 9) /* Ran out of resources */
|
||||
#define FD_STATUS_S8 (0x1 << 8) /* Rx DMA overrun */
|
||||
#define FD_STATUS_S7 (0x1 << 7) /* Frame too short */
|
||||
#define FD_STATUS_S6 (0x1 << 6) /* No EOF flag */
|
||||
unsigned short fd_command; /* Command */
|
||||
#define FD_COMMAND_EL (0x1 << 15) /* Last FD in list */
|
||||
#define FD_COMMAND_S (0x1 << 14) /* Suspend RU after rx */
|
||||
unsigned short fd_link_offset; /* Next FD */
|
||||
unsigned short fd_rbd_offset; /* First RBD (data) */
|
||||
/* Prepared by CPU, */
|
||||
/* updated by 82586 */
|
||||
#if 0
|
||||
I think the rest is unused since we
|
||||
have set AC_CFG_ALOC(..). However, just
|
||||
in case, we leave the space.
|
||||
#endif /* 0 */
|
||||
unsigned char fd_dest[ADDR_LEN]; /* Destination address */
|
||||
/* Written by 82586 */
|
||||
unsigned char fd_src[ADDR_LEN]; /* Source address */
|
||||
/* Written by 82586 */
|
||||
unsigned short fd_length; /* Frame length or type */
|
||||
/* Written by 82586 */
|
||||
};
|
||||
|
||||
#define fdoff(p, f) toff(fd_t, p, f)
|
||||
|
||||
/*
|
||||
* This software may only be used and distributed
|
||||
* according to the terms of the GNU General Public License.
|
||||
*
|
||||
* For more details, see wavelan.c.
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,363 +0,0 @@
|
||||
/*
|
||||
* WaveLAN ISA driver
|
||||
*
|
||||
* Jean II - HPLB '96
|
||||
*
|
||||
* Reorganisation and extension of the driver.
|
||||
* Original copyright follows. See wavelan.p.h for details.
|
||||
*
|
||||
* This file contains the declarations for the WaveLAN hardware. Note that
|
||||
* the WaveLAN ISA includes a i82586 controller (see definitions in
|
||||
* file i82586.h).
|
||||
*
|
||||
* The main difference between the ISA hardware and the PCMCIA one is
|
||||
* the Ethernet controller (i82586 instead of i82593).
|
||||
* The i82586 allows multiple transmit buffers. The PSA needs to be accessed
|
||||
* through the host interface.
|
||||
*/
|
||||
|
||||
#ifndef _WAVELAN_H
|
||||
#define _WAVELAN_H
|
||||
|
||||
/************************** MAGIC NUMBERS ***************************/
|
||||
|
||||
/* Detection of the WaveLAN card is done by reading the MAC
|
||||
* address from the card and checking it. If you have a non-AT&T
|
||||
* product (OEM, like DEC RoamAbout, Digital Ocean, or Epson),
|
||||
* you might need to modify this part to accommodate your hardware.
|
||||
*/
|
||||
static const char MAC_ADDRESSES[][3] = {
|
||||
{ 0x08, 0x00, 0x0E }, /* AT&T WaveLAN (standard) & DEC RoamAbout */
|
||||
{ 0x08, 0x00, 0x6A }, /* AT&T WaveLAN (alternate) */
|
||||
{ 0x00, 0x00, 0xE1 }, /* Hitachi Wavelan */
|
||||
{ 0x00, 0x60, 0x1D } /* Lucent Wavelan (another one) */
|
||||
/* Add your card here and send me the patch! */
|
||||
};
|
||||
|
||||
#define WAVELAN_ADDR_SIZE 6 /* Size of a MAC address */
|
||||
|
||||
#define WAVELAN_MTU 1500 /* Maximum size of WaveLAN packet */
|
||||
|
||||
#define MAXDATAZ (WAVELAN_ADDR_SIZE + WAVELAN_ADDR_SIZE + 2 + WAVELAN_MTU)
|
||||
|
||||
/*
|
||||
* Constants used to convert channels to frequencies
|
||||
*/
|
||||
|
||||
/* Frequency available in the 2.0 modem, in units of 250 kHz
|
||||
* (as read in the offset register of the dac area).
|
||||
* Used to map channel numbers used by `wfreqsel' to frequencies
|
||||
*/
|
||||
static const short channel_bands[] = { 0x30, 0x58, 0x64, 0x7A, 0x80, 0xA8,
|
||||
0xD0, 0xF0, 0xF8, 0x150 };
|
||||
|
||||
/* Frequencies of the 1.0 modem (fixed frequencies).
|
||||
* Use to map the PSA `subband' to a frequency
|
||||
* Note : all frequencies apart from the first one need to be multiplied by 10
|
||||
*/
|
||||
static const int fixed_bands[] = { 915e6, 2.425e8, 2.46e8, 2.484e8, 2.4305e8 };
|
||||
|
||||
|
||||
|
||||
/*************************** PC INTERFACE ****************************/
|
||||
|
||||
/*
|
||||
* Host Adaptor structure.
|
||||
* (base is board port address).
|
||||
*/
|
||||
typedef union hacs_u hacs_u;
|
||||
union hacs_u {
|
||||
unsigned short hu_command; /* Command register */
|
||||
#define HACR_RESET 0x0001 /* Reset board */
|
||||
#define HACR_CA 0x0002 /* Set Channel Attention for 82586 */
|
||||
#define HACR_16BITS 0x0004 /* 16-bit operation (0 => 8bits) */
|
||||
#define HACR_OUT0 0x0008 /* General purpose output pin 0 */
|
||||
/* not used - must be 1 */
|
||||
#define HACR_OUT1 0x0010 /* General purpose output pin 1 */
|
||||
/* not used - must be 1 */
|
||||
#define HACR_82586_INT_ENABLE 0x0020 /* Enable 82586 interrupts */
|
||||
#define HACR_MMC_INT_ENABLE 0x0040 /* Enable MMC interrupts */
|
||||
#define HACR_INTR_CLR_ENABLE 0x0080 /* Enable interrupt status read/clear */
|
||||
unsigned short hu_status; /* Status Register */
|
||||
#define HASR_82586_INTR 0x0001 /* Interrupt request from 82586 */
|
||||
#define HASR_MMC_INTR 0x0002 /* Interrupt request from MMC */
|
||||
#define HASR_MMC_BUSY 0x0004 /* MMC busy indication */
|
||||
#define HASR_PSA_BUSY 0x0008 /* LAN parameter storage area busy */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
typedef struct ha_t ha_t;
|
||||
struct ha_t {
|
||||
hacs_u ha_cs; /* Command and status registers */
|
||||
#define ha_command ha_cs.hu_command
|
||||
#define ha_status ha_cs.hu_status
|
||||
unsigned short ha_mmcr; /* Modem Management Ctrl Register */
|
||||
unsigned short ha_pior0; /* Program I/O Address Register Port 0 */
|
||||
unsigned short ha_piop0; /* Program I/O Port 0 */
|
||||
unsigned short ha_pior1; /* Program I/O Address Register Port 1 */
|
||||
unsigned short ha_piop1; /* Program I/O Port 1 */
|
||||
unsigned short ha_pior2; /* Program I/O Address Register Port 2 */
|
||||
unsigned short ha_piop2; /* Program I/O Port 2 */
|
||||
};
|
||||
|
||||
#define HA_SIZE 16
|
||||
|
||||
#define hoff(p, f) (unsigned short)((void *)(&((ha_t *)((void *)0 + (p)))->f) - (void *)0)
|
||||
#define HACR(p) hoff(p, ha_command)
|
||||
#define HASR(p) hoff(p, ha_status)
|
||||
#define MMCR(p) hoff(p, ha_mmcr)
|
||||
#define PIOR0(p) hoff(p, ha_pior0)
|
||||
#define PIOP0(p) hoff(p, ha_piop0)
|
||||
#define PIOR1(p) hoff(p, ha_pior1)
|
||||
#define PIOP1(p) hoff(p, ha_piop1)
|
||||
#define PIOR2(p) hoff(p, ha_pior2)
|
||||
#define PIOP2(p) hoff(p, ha_piop2)
|
||||
|
||||
/*
|
||||
* Program I/O Mode Register values.
|
||||
*/
|
||||
#define STATIC_PIO 0 /* Mode 1: static mode */
|
||||
/* RAM access ??? */
|
||||
#define AUTOINCR_PIO 1 /* Mode 2: auto increment mode */
|
||||
/* RAM access ??? */
|
||||
#define AUTODECR_PIO 2 /* Mode 3: auto decrement mode */
|
||||
/* RAM access ??? */
|
||||
#define PARAM_ACCESS_PIO 3 /* Mode 4: LAN parameter access mode */
|
||||
/* Parameter access. */
|
||||
#define PIO_MASK 3 /* register mask */
|
||||
#define PIOM(cmd, piono) ((u_short)cmd << 10 << (piono * 2))
|
||||
|
||||
#define HACR_DEFAULT (HACR_OUT0 | HACR_OUT1 | HACR_16BITS | PIOM(STATIC_PIO, 0) | PIOM(AUTOINCR_PIO, 1) | PIOM(PARAM_ACCESS_PIO, 2))
|
||||
#define HACR_INTRON (HACR_82586_INT_ENABLE | HACR_MMC_INT_ENABLE | HACR_INTR_CLR_ENABLE)
|
||||
|
||||
/************************** MEMORY LAYOUT **************************/
|
||||
|
||||
/*
|
||||
* Onboard 64 k RAM layout.
|
||||
* (Offsets from 0x0000.)
|
||||
*/
|
||||
#define OFFSET_RU 0x0000 /* 75% memory */
|
||||
#define OFFSET_CU 0xC000 /* 25% memory */
|
||||
#define OFFSET_SCB (OFFSET_ISCP - sizeof(scb_t))
|
||||
#define OFFSET_ISCP (OFFSET_SCP - sizeof(iscp_t))
|
||||
#define OFFSET_SCP I82586_SCP_ADDR
|
||||
|
||||
#define RXBLOCKZ (sizeof(fd_t) + sizeof(rbd_t) + MAXDATAZ)
|
||||
#define TXBLOCKZ (sizeof(ac_tx_t) + sizeof(ac_nop_t) + sizeof(tbd_t) + MAXDATAZ)
|
||||
|
||||
#define NRXBLOCKS ((OFFSET_CU - OFFSET_RU) / RXBLOCKZ)
|
||||
#define NTXBLOCKS ((OFFSET_SCB - OFFSET_CU) / TXBLOCKZ)
|
||||
|
||||
/********************** PARAMETER STORAGE AREA **********************/
|
||||
|
||||
/*
|
||||
* Parameter Storage Area (PSA).
|
||||
*/
|
||||
typedef struct psa_t psa_t;
|
||||
struct psa_t {
|
||||
unsigned char psa_io_base_addr_1; /* [0x00] Base address 1 ??? */
|
||||
unsigned char psa_io_base_addr_2; /* [0x01] Base address 2 */
|
||||
unsigned char psa_io_base_addr_3; /* [0x02] Base address 3 */
|
||||
unsigned char psa_io_base_addr_4; /* [0x03] Base address 4 */
|
||||
unsigned char psa_rem_boot_addr_1; /* [0x04] Remote Boot Address 1 */
|
||||
unsigned char psa_rem_boot_addr_2; /* [0x05] Remote Boot Address 2 */
|
||||
unsigned char psa_rem_boot_addr_3; /* [0x06] Remote Boot Address 3 */
|
||||
unsigned char psa_holi_params; /* [0x07] HOst Lan Interface (HOLI) Parameters */
|
||||
unsigned char psa_int_req_no; /* [0x08] Interrupt Request Line */
|
||||
unsigned char psa_unused0[7]; /* [0x09-0x0F] unused */
|
||||
|
||||
unsigned char psa_univ_mac_addr[WAVELAN_ADDR_SIZE]; /* [0x10-0x15] Universal (factory) MAC Address */
|
||||
unsigned char psa_local_mac_addr[WAVELAN_ADDR_SIZE]; /* [0x16-1B] Local MAC Address */
|
||||
unsigned char psa_univ_local_sel; /* [0x1C] Universal Local Selection */
|
||||
#define PSA_UNIVERSAL 0 /* Universal (factory) */
|
||||
#define PSA_LOCAL 1 /* Local */
|
||||
unsigned char psa_comp_number; /* [0x1D] Compatibility Number: */
|
||||
#define PSA_COMP_PC_AT_915 0 /* PC-AT 915 MHz */
|
||||
#define PSA_COMP_PC_MC_915 1 /* PC-MC 915 MHz */
|
||||
#define PSA_COMP_PC_AT_2400 2 /* PC-AT 2.4 GHz */
|
||||
#define PSA_COMP_PC_MC_2400 3 /* PC-MC 2.4 GHz */
|
||||
#define PSA_COMP_PCMCIA_915 4 /* PCMCIA 915 MHz or 2.0 */
|
||||
unsigned char psa_thr_pre_set; /* [0x1E] Modem Threshold Preset */
|
||||
unsigned char psa_feature_select; /* [0x1F] Call code required (1=on) */
|
||||
#define PSA_FEATURE_CALL_CODE 0x01 /* Call code required (Japan) */
|
||||
unsigned char psa_subband; /* [0x20] Subband */
|
||||
#define PSA_SUBBAND_915 0 /* 915 MHz or 2.0 */
|
||||
#define PSA_SUBBAND_2425 1 /* 2425 MHz */
|
||||
#define PSA_SUBBAND_2460 2 /* 2460 MHz */
|
||||
#define PSA_SUBBAND_2484 3 /* 2484 MHz */
|
||||
#define PSA_SUBBAND_2430_5 4 /* 2430.5 MHz */
|
||||
unsigned char psa_quality_thr; /* [0x21] Modem Quality Threshold */
|
||||
unsigned char psa_mod_delay; /* [0x22] Modem Delay (?) (reserved) */
|
||||
unsigned char psa_nwid[2]; /* [0x23-0x24] Network ID */
|
||||
unsigned char psa_nwid_select; /* [0x25] Network ID Select On/Off */
|
||||
unsigned char psa_encryption_select; /* [0x26] Encryption On/Off */
|
||||
unsigned char psa_encryption_key[8]; /* [0x27-0x2E] Encryption Key */
|
||||
unsigned char psa_databus_width; /* [0x2F] AT bus width select 8/16 */
|
||||
unsigned char psa_call_code[8]; /* [0x30-0x37] (Japan) Call Code */
|
||||
unsigned char psa_nwid_prefix[2]; /* [0x38-0x39] Roaming domain */
|
||||
unsigned char psa_reserved[2]; /* [0x3A-0x3B] Reserved - fixed 00 */
|
||||
unsigned char psa_conf_status; /* [0x3C] Conf Status, bit 0=1:config*/
|
||||
unsigned char psa_crc[2]; /* [0x3D] CRC-16 over PSA */
|
||||
unsigned char psa_crc_status; /* [0x3F] CRC Valid Flag */
|
||||
};
|
||||
|
||||
#define PSA_SIZE 64
|
||||
|
||||
/* Calculate offset of a field in the above structure.
|
||||
* Warning: only even addresses are used. */
|
||||
#define psaoff(p, f) ((unsigned short) ((void *)(&((psa_t *) ((void *) NULL + (p)))->f) - (void *) NULL))
|
||||
|
||||
/******************** MODEM MANAGEMENT INTERFACE ********************/
|
||||
|
||||
/*
|
||||
* Modem Management Controller (MMC) write structure.
|
||||
*/
|
||||
typedef struct mmw_t mmw_t;
|
||||
struct mmw_t {
|
||||
unsigned char mmw_encr_key[8]; /* encryption key */
|
||||
unsigned char mmw_encr_enable; /* Enable or disable encryption. */
|
||||
#define MMW_ENCR_ENABLE_MODE 0x02 /* mode of security option */
|
||||
#define MMW_ENCR_ENABLE_EN 0x01 /* Enable security option. */
|
||||
unsigned char mmw_unused0[1]; /* unused */
|
||||
unsigned char mmw_des_io_invert; /* encryption option */
|
||||
#define MMW_DES_IO_INVERT_RES 0x0F /* reserved */
|
||||
#define MMW_DES_IO_INVERT_CTRL 0xF0 /* control (?) (set to 0) */
|
||||
unsigned char mmw_unused1[5]; /* unused */
|
||||
unsigned char mmw_loopt_sel; /* looptest selection */
|
||||
#define MMW_LOOPT_SEL_DIS_NWID 0x40 /* Disable NWID filtering. */
|
||||
#define MMW_LOOPT_SEL_INT 0x20 /* Activate Attention Request. */
|
||||
#define MMW_LOOPT_SEL_LS 0x10 /* looptest, no collision avoidance */
|
||||
#define MMW_LOOPT_SEL_LT3A 0x08 /* looptest 3a */
|
||||
#define MMW_LOOPT_SEL_LT3B 0x04 /* looptest 3b */
|
||||
#define MMW_LOOPT_SEL_LT3C 0x02 /* looptest 3c */
|
||||
#define MMW_LOOPT_SEL_LT3D 0x01 /* looptest 3d */
|
||||
unsigned char mmw_jabber_enable; /* jabber timer enable */
|
||||
/* Abort transmissions > 200 ms */
|
||||
unsigned char mmw_freeze; /* freeze or unfreeze signal level */
|
||||
/* 0 : signal level & qual updated for every new message, 1 : frozen */
|
||||
unsigned char mmw_anten_sel; /* antenna selection */
|
||||
#define MMW_ANTEN_SEL_SEL 0x01 /* direct antenna selection */
|
||||
#define MMW_ANTEN_SEL_ALG_EN 0x02 /* antenna selection algo. enable */
|
||||
unsigned char mmw_ifs; /* inter frame spacing */
|
||||
/* min time between transmission in bit periods (.5 us) - bit 0 ignored */
|
||||
unsigned char mmw_mod_delay; /* modem delay (synchro) */
|
||||
unsigned char mmw_jam_time; /* jamming time (after collision) */
|
||||
unsigned char mmw_unused2[1]; /* unused */
|
||||
unsigned char mmw_thr_pre_set; /* level threshold preset */
|
||||
/* Discard all packet with signal < this value (4) */
|
||||
unsigned char mmw_decay_prm; /* decay parameters */
|
||||
unsigned char mmw_decay_updat_prm; /* decay update parameters */
|
||||
unsigned char mmw_quality_thr; /* quality (z-quotient) threshold */
|
||||
/* Discard all packet with quality < this value (3) */
|
||||
unsigned char mmw_netw_id_l; /* NWID low order byte */
|
||||
unsigned char mmw_netw_id_h; /* NWID high order byte */
|
||||
/* Network ID or Domain : create virtual net on the air */
|
||||
|
||||
/* 2.0 Hardware extension - frequency selection support */
|
||||
unsigned char mmw_mode_select; /* for analog tests (set to 0) */
|
||||
unsigned char mmw_unused3[1]; /* unused */
|
||||
unsigned char mmw_fee_ctrl; /* frequency EEPROM control */
|
||||
#define MMW_FEE_CTRL_PRE 0x10 /* Enable protected instructions. */
|
||||
#define MMW_FEE_CTRL_DWLD 0x08 /* Download EEPROM to mmc. */
|
||||
#define MMW_FEE_CTRL_CMD 0x07 /* EEPROM commands: */
|
||||
#define MMW_FEE_CTRL_READ 0x06 /* Read */
|
||||
#define MMW_FEE_CTRL_WREN 0x04 /* Write enable */
|
||||
#define MMW_FEE_CTRL_WRITE 0x05 /* Write data to address. */
|
||||
#define MMW_FEE_CTRL_WRALL 0x04 /* Write data to all addresses. */
|
||||
#define MMW_FEE_CTRL_WDS 0x04 /* Write disable */
|
||||
#define MMW_FEE_CTRL_PRREAD 0x16 /* Read addr from protect register */
|
||||
#define MMW_FEE_CTRL_PREN 0x14 /* Protect register enable */
|
||||
#define MMW_FEE_CTRL_PRCLEAR 0x17 /* Unprotect all registers. */
|
||||
#define MMW_FEE_CTRL_PRWRITE 0x15 /* Write address in protect register */
|
||||
#define MMW_FEE_CTRL_PRDS 0x14 /* Protect register disable */
|
||||
/* Never issue the PRDS command: it's irreversible! */
|
||||
|
||||
unsigned char mmw_fee_addr; /* EEPROM address */
|
||||
#define MMW_FEE_ADDR_CHANNEL 0xF0 /* Select the channel. */
|
||||
#define MMW_FEE_ADDR_OFFSET 0x0F /* Offset in channel data */
|
||||
#define MMW_FEE_ADDR_EN 0xC0 /* FEE_CTRL enable operations */
|
||||
#define MMW_FEE_ADDR_DS 0x00 /* FEE_CTRL disable operations */
|
||||
#define MMW_FEE_ADDR_ALL 0x40 /* FEE_CTRL all operations */
|
||||
#define MMW_FEE_ADDR_CLEAR 0xFF /* FEE_CTRL clear operations */
|
||||
|
||||
unsigned char mmw_fee_data_l; /* Write data to EEPROM. */
|
||||
unsigned char mmw_fee_data_h; /* high octet */
|
||||
unsigned char mmw_ext_ant; /* Setting for external antenna */
|
||||
#define MMW_EXT_ANT_EXTANT 0x01 /* Select external antenna */
|
||||
#define MMW_EXT_ANT_POL 0x02 /* Polarity of the antenna */
|
||||
#define MMW_EXT_ANT_INTERNAL 0x00 /* Internal antenna */
|
||||
#define MMW_EXT_ANT_EXTERNAL 0x03 /* External antenna */
|
||||
#define MMW_EXT_ANT_IQ_TEST 0x1C /* IQ test pattern (set to 0) */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#define MMW_SIZE 37
|
||||
|
||||
#define mmwoff(p, f) (unsigned short)((void *)(&((mmw_t *)((void *)0 + (p)))->f) - (void *)0)
|
||||
|
||||
/*
|
||||
* Modem Management Controller (MMC) read structure.
|
||||
*/
|
||||
typedef struct mmr_t mmr_t;
|
||||
struct mmr_t {
|
||||
unsigned char mmr_unused0[8]; /* unused */
|
||||
unsigned char mmr_des_status; /* encryption status */
|
||||
unsigned char mmr_des_avail; /* encryption available (0x55 read) */
|
||||
#define MMR_DES_AVAIL_DES 0x55 /* DES available */
|
||||
#define MMR_DES_AVAIL_AES 0x33 /* AES (AT&T) available */
|
||||
unsigned char mmr_des_io_invert; /* des I/O invert register */
|
||||
unsigned char mmr_unused1[5]; /* unused */
|
||||
unsigned char mmr_dce_status; /* DCE status */
|
||||
#define MMR_DCE_STATUS_RX_BUSY 0x01 /* receiver busy */
|
||||
#define MMR_DCE_STATUS_LOOPT_IND 0x02 /* loop test indicated */
|
||||
#define MMR_DCE_STATUS_TX_BUSY 0x04 /* transmitter on */
|
||||
#define MMR_DCE_STATUS_JBR_EXPIRED 0x08 /* jabber timer expired */
|
||||
#define MMR_DCE_STATUS 0x0F /* mask to get the bits */
|
||||
unsigned char mmr_dsp_id; /* DSP ID (AA = Daedalus rev A) */
|
||||
unsigned char mmr_unused2[2]; /* unused */
|
||||
unsigned char mmr_correct_nwid_l; /* # of correct NWIDs rxd (low) */
|
||||
unsigned char mmr_correct_nwid_h; /* # of correct NWIDs rxd (high) */
|
||||
/* Warning: read high-order octet first! */
|
||||
unsigned char mmr_wrong_nwid_l; /* # of wrong NWIDs rxd (low) */
|
||||
unsigned char mmr_wrong_nwid_h; /* # of wrong NWIDs rxd (high) */
|
||||
unsigned char mmr_thr_pre_set; /* level threshold preset */
|
||||
#define MMR_THR_PRE_SET 0x3F /* level threshold preset */
|
||||
#define MMR_THR_PRE_SET_CUR 0x80 /* Current signal above it */
|
||||
unsigned char mmr_signal_lvl; /* signal level */
|
||||
#define MMR_SIGNAL_LVL 0x3F /* signal level */
|
||||
#define MMR_SIGNAL_LVL_VALID 0x80 /* Updated since last read */
|
||||
unsigned char mmr_silence_lvl; /* silence level (noise) */
|
||||
#define MMR_SILENCE_LVL 0x3F /* silence level */
|
||||
#define MMR_SILENCE_LVL_VALID 0x80 /* Updated since last read */
|
||||
unsigned char mmr_sgnl_qual; /* signal quality */
|
||||
#define MMR_SGNL_QUAL 0x0F /* signal quality */
|
||||
#define MMR_SGNL_QUAL_ANT 0x80 /* current antenna used */
|
||||
unsigned char mmr_netw_id_l; /* NWID low order byte (?) */
|
||||
unsigned char mmr_unused3[3]; /* unused */
|
||||
|
||||
/* 2.0 Hardware extension - frequency selection support */
|
||||
unsigned char mmr_fee_status; /* Status of frequency EEPROM */
|
||||
#define MMR_FEE_STATUS_ID 0xF0 /* Modem revision ID */
|
||||
#define MMR_FEE_STATUS_DWLD 0x08 /* Download in progress */
|
||||
#define MMR_FEE_STATUS_BUSY 0x04 /* EEPROM busy */
|
||||
unsigned char mmr_unused4[1]; /* unused */
|
||||
unsigned char mmr_fee_data_l; /* Read data from EEPROM (low) */
|
||||
unsigned char mmr_fee_data_h; /* Read data from EEPROM (high) */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#define MMR_SIZE 36
|
||||
|
||||
#define mmroff(p, f) (unsigned short)((void *)(&((mmr_t *)((void *)0 + (p)))->f) - (void *)0)
|
||||
|
||||
/* Make the two above structures one */
|
||||
typedef union mm_t {
|
||||
struct mmw_t w; /* Write to the mmc */
|
||||
struct mmr_t r; /* Read from the mmc */
|
||||
} mm_t;
|
||||
|
||||
#endif /* _WAVELAN_H */
|
||||
|
||||
/*
|
||||
* This software may only be used and distributed
|
||||
* according to the terms of the GNU General Public License.
|
||||
*
|
||||
* For more details, see wavelan.c.
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,381 +0,0 @@
|
||||
/*
|
||||
* Wavelan Pcmcia driver
|
||||
*
|
||||
* Jean II - HPLB '96
|
||||
*
|
||||
* Reorganization and extension of the driver.
|
||||
* Original copyright follow. See wavelan_cs.h for details.
|
||||
*
|
||||
* This file contain the declarations of the Wavelan hardware. Note that
|
||||
* the Pcmcia Wavelan include a i82593 controller (see definitions in
|
||||
* file i82593.h).
|
||||
*
|
||||
* The main difference between the pcmcia hardware and the ISA one is
|
||||
* the Ethernet Controller (i82593 instead of i82586). The i82593 allow
|
||||
* only one send buffer. The PSA (Parameter Storage Area : EEprom for
|
||||
* permanent storage of various info) is memory mapped, but not the
|
||||
* MMI (Modem Management Interface).
|
||||
*/
|
||||
|
||||
/*
|
||||
* Definitions for the AT&T GIS (formerly NCR) WaveLAN PCMCIA card:
|
||||
* An Ethernet-like radio transceiver controlled by an Intel 82593
|
||||
* coprocessor.
|
||||
*
|
||||
*
|
||||
****************************************************************************
|
||||
* Copyright 1995
|
||||
* Anthony D. Joseph
|
||||
* Massachusetts Institute of Technology
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this program
|
||||
* for any purpose and without fee is hereby granted, provided
|
||||
* that this copyright and permission notice appear on all copies
|
||||
* and supporting documentation, the name of M.I.T. not be used
|
||||
* in advertising or publicity pertaining to distribution of the
|
||||
* program without specific prior permission, and notice be given
|
||||
* in supporting documentation that copying and distribution is
|
||||
* by permission of M.I.T. M.I.T. makes no representations about
|
||||
* the suitability of this software for any purpose. It is pro-
|
||||
* vided "as is" without express or implied warranty.
|
||||
****************************************************************************
|
||||
*
|
||||
*
|
||||
* Credits:
|
||||
* Special thanks to Jan Hoogendoorn of AT&T GIS Utrecht for
|
||||
* providing extremely useful information about WaveLAN PCMCIA hardware
|
||||
*
|
||||
* This driver is based upon several other drivers, in particular:
|
||||
* David Hinds' Linux driver for the PCMCIA 3c589 ethernet adapter
|
||||
* Bruce Janson's Linux driver for the AT-bus WaveLAN adapter
|
||||
* Anders Klemets' PCMCIA WaveLAN adapter driver
|
||||
* Robert Morris' BSDI driver for the PCMCIA WaveLAN adapter
|
||||
*/
|
||||
|
||||
#ifndef _WAVELAN_CS_H
|
||||
#define _WAVELAN_CS_H
|
||||
|
||||
/************************** MAGIC NUMBERS ***************************/
|
||||
|
||||
/* The detection of the wavelan card is made by reading the MAC address
|
||||
* from the card and checking it. If you have a non AT&T product (OEM,
|
||||
* like DEC RoamAbout, or Digital Ocean, Epson, ...), you must modify this
|
||||
* part to accommodate your hardware...
|
||||
*/
|
||||
static const unsigned char MAC_ADDRESSES[][3] = {
|
||||
{ 0x08, 0x00, 0x0E }, /* AT&T Wavelan (standard) & DEC RoamAbout */
|
||||
{ 0x08, 0x00, 0x6A }, /* AT&T Wavelan (alternate) */
|
||||
{ 0x00, 0x00, 0xE1 }, /* Hitachi Wavelan */
|
||||
{ 0x00, 0x60, 0x1D } /* Lucent Wavelan (another one) */
|
||||
/* Add your card here and send me the patch ! */
|
||||
};
|
||||
|
||||
/*
|
||||
* Constants used to convert channels to frequencies
|
||||
*/
|
||||
|
||||
/* Frequency available in the 2.0 modem, in units of 250 kHz
|
||||
* (as read in the offset register of the dac area).
|
||||
* Used to map channel numbers used by `wfreqsel' to frequencies
|
||||
*/
|
||||
static const short channel_bands[] = { 0x30, 0x58, 0x64, 0x7A, 0x80, 0xA8,
|
||||
0xD0, 0xF0, 0xF8, 0x150 };
|
||||
|
||||
/* Frequencies of the 1.0 modem (fixed frequencies).
|
||||
* Use to map the PSA `subband' to a frequency
|
||||
* Note : all frequencies apart from the first one need to be multiplied by 10
|
||||
*/
|
||||
static const int fixed_bands[] = { 915e6, 2.425e8, 2.46e8, 2.484e8, 2.4305e8 };
|
||||
|
||||
|
||||
/*************************** PC INTERFACE ****************************/
|
||||
|
||||
/* WaveLAN host interface definitions */
|
||||
|
||||
#define LCCR(base) (base) /* LAN Controller Command Register */
|
||||
#define LCSR(base) (base) /* LAN Controller Status Register */
|
||||
#define HACR(base) (base+0x1) /* Host Adapter Command Register */
|
||||
#define HASR(base) (base+0x1) /* Host Adapter Status Register */
|
||||
#define PIORL(base) (base+0x2) /* Program I/O Register Low */
|
||||
#define RPLL(base) (base+0x2) /* Receive Pointer Latched Low */
|
||||
#define PIORH(base) (base+0x3) /* Program I/O Register High */
|
||||
#define RPLH(base) (base+0x3) /* Receive Pointer Latched High */
|
||||
#define PIOP(base) (base+0x4) /* Program I/O Port */
|
||||
#define MMR(base) (base+0x6) /* MMI Address Register */
|
||||
#define MMD(base) (base+0x7) /* MMI Data Register */
|
||||
|
||||
/* Host Adaptor Command Register bit definitions */
|
||||
|
||||
#define HACR_LOF (1 << 3) /* Lock Out Flag, toggle every 250ms */
|
||||
#define HACR_PWR_STAT (1 << 4) /* Power State, 1=active, 0=sleep */
|
||||
#define HACR_TX_DMA_RESET (1 << 5) /* Reset transmit DMA ptr on high */
|
||||
#define HACR_RX_DMA_RESET (1 << 6) /* Reset receive DMA ptr on high */
|
||||
#define HACR_ROM_WEN (1 << 7) /* EEPROM write enabled when true */
|
||||
|
||||
#define HACR_RESET (HACR_TX_DMA_RESET | HACR_RX_DMA_RESET)
|
||||
#define HACR_DEFAULT (HACR_PWR_STAT)
|
||||
|
||||
/* Host Adapter Status Register bit definitions */
|
||||
|
||||
#define HASR_MMI_BUSY (1 << 2) /* MMI is busy when true */
|
||||
#define HASR_LOF (1 << 3) /* Lock out flag status */
|
||||
#define HASR_NO_CLK (1 << 4) /* active when modem not connected */
|
||||
|
||||
/* Miscellaneous bit definitions */
|
||||
|
||||
#define PIORH_SEL_TX (1 << 5) /* PIOR points to 0=rx/1=tx buffer */
|
||||
#define MMR_MMI_WR (1 << 0) /* Next MMI cycle is 0=read, 1=write */
|
||||
#define PIORH_MASK 0x1f /* only low 5 bits are significant */
|
||||
#define RPLH_MASK 0x1f /* only low 5 bits are significant */
|
||||
#define MMI_ADDR_MASK 0x7e /* Bits 1-6 of MMR are significant */
|
||||
|
||||
/* Attribute Memory map */
|
||||
|
||||
#define CIS_ADDR 0x0000 /* Card Information Status Register */
|
||||
#define PSA_ADDR 0x0e00 /* Parameter Storage Area address */
|
||||
#define EEPROM_ADDR 0x1000 /* EEPROM address (unused ?) */
|
||||
#define COR_ADDR 0x4000 /* Configuration Option Register */
|
||||
|
||||
/* Configuration Option Register bit definitions */
|
||||
|
||||
#define COR_CONFIG (1 << 0) /* Config Index, 0 when unconfigured */
|
||||
#define COR_SW_RESET (1 << 7) /* Software Reset on true */
|
||||
#define COR_LEVEL_IRQ (1 << 6) /* Level IRQ */
|
||||
|
||||
/* Local Memory map */
|
||||
|
||||
#define RX_BASE 0x0000 /* Receive memory, 8 kB */
|
||||
#define TX_BASE 0x2000 /* Transmit memory, 2 kB */
|
||||
#define UNUSED_BASE 0x2800 /* Unused, 22 kB */
|
||||
#define RX_SIZE (TX_BASE-RX_BASE) /* Size of receive area */
|
||||
#define RX_SIZE_SHIFT 6 /* Bits to shift in stop register */
|
||||
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
|
||||
#define MOD_ENAL 1
|
||||
#define MOD_PROM 2
|
||||
|
||||
/* Size of a MAC address */
|
||||
#define WAVELAN_ADDR_SIZE 6
|
||||
|
||||
/* Maximum size of Wavelan packet */
|
||||
#define WAVELAN_MTU 1500
|
||||
|
||||
#define MAXDATAZ (6 + 6 + 2 + WAVELAN_MTU)
|
||||
|
||||
/********************** PARAMETER STORAGE AREA **********************/
|
||||
|
||||
/*
|
||||
* Parameter Storage Area (PSA).
|
||||
*/
|
||||
typedef struct psa_t psa_t;
|
||||
struct psa_t {
|
||||
/* For the PCMCIA Adapter, locations 0x00-0x0F are unused and fixed at 00 */
|
||||
unsigned char psa_io_base_addr_1; /* [0x00] Base address 1 ??? */
|
||||
unsigned char psa_io_base_addr_2; /* [0x01] Base address 2 */
|
||||
unsigned char psa_io_base_addr_3; /* [0x02] Base address 3 */
|
||||
unsigned char psa_io_base_addr_4; /* [0x03] Base address 4 */
|
||||
unsigned char psa_rem_boot_addr_1; /* [0x04] Remote Boot Address 1 */
|
||||
unsigned char psa_rem_boot_addr_2; /* [0x05] Remote Boot Address 2 */
|
||||
unsigned char psa_rem_boot_addr_3; /* [0x06] Remote Boot Address 3 */
|
||||
unsigned char psa_holi_params; /* [0x07] HOst Lan Interface (HOLI) Parameters */
|
||||
unsigned char psa_int_req_no; /* [0x08] Interrupt Request Line */
|
||||
unsigned char psa_unused0[7]; /* [0x09-0x0F] unused */
|
||||
|
||||
unsigned char psa_univ_mac_addr[WAVELAN_ADDR_SIZE]; /* [0x10-0x15] Universal (factory) MAC Address */
|
||||
unsigned char psa_local_mac_addr[WAVELAN_ADDR_SIZE]; /* [0x16-1B] Local MAC Address */
|
||||
unsigned char psa_univ_local_sel; /* [0x1C] Universal Local Selection */
|
||||
#define PSA_UNIVERSAL 0 /* Universal (factory) */
|
||||
#define PSA_LOCAL 1 /* Local */
|
||||
unsigned char psa_comp_number; /* [0x1D] Compatability Number: */
|
||||
#define PSA_COMP_PC_AT_915 0 /* PC-AT 915 MHz */
|
||||
#define PSA_COMP_PC_MC_915 1 /* PC-MC 915 MHz */
|
||||
#define PSA_COMP_PC_AT_2400 2 /* PC-AT 2.4 GHz */
|
||||
#define PSA_COMP_PC_MC_2400 3 /* PC-MC 2.4 GHz */
|
||||
#define PSA_COMP_PCMCIA_915 4 /* PCMCIA 915 MHz or 2.0 */
|
||||
unsigned char psa_thr_pre_set; /* [0x1E] Modem Threshold Preset */
|
||||
unsigned char psa_feature_select; /* [0x1F] Call code required (1=on) */
|
||||
#define PSA_FEATURE_CALL_CODE 0x01 /* Call code required (Japan) */
|
||||
unsigned char psa_subband; /* [0x20] Subband */
|
||||
#define PSA_SUBBAND_915 0 /* 915 MHz or 2.0 */
|
||||
#define PSA_SUBBAND_2425 1 /* 2425 MHz */
|
||||
#define PSA_SUBBAND_2460 2 /* 2460 MHz */
|
||||
#define PSA_SUBBAND_2484 3 /* 2484 MHz */
|
||||
#define PSA_SUBBAND_2430_5 4 /* 2430.5 MHz */
|
||||
unsigned char psa_quality_thr; /* [0x21] Modem Quality Threshold */
|
||||
unsigned char psa_mod_delay; /* [0x22] Modem Delay ??? (reserved) */
|
||||
unsigned char psa_nwid[2]; /* [0x23-0x24] Network ID */
|
||||
unsigned char psa_nwid_select; /* [0x25] Network ID Select On Off */
|
||||
unsigned char psa_encryption_select; /* [0x26] Encryption On Off */
|
||||
unsigned char psa_encryption_key[8]; /* [0x27-0x2E] Encryption Key */
|
||||
unsigned char psa_databus_width; /* [0x2F] AT bus width select 8/16 */
|
||||
unsigned char psa_call_code[8]; /* [0x30-0x37] (Japan) Call Code */
|
||||
unsigned char psa_nwid_prefix[2]; /* [0x38-0x39] Roaming domain */
|
||||
unsigned char psa_reserved[2]; /* [0x3A-0x3B] Reserved - fixed 00 */
|
||||
unsigned char psa_conf_status; /* [0x3C] Conf Status, bit 0=1:config*/
|
||||
unsigned char psa_crc[2]; /* [0x3D] CRC-16 over PSA */
|
||||
unsigned char psa_crc_status; /* [0x3F] CRC Valid Flag */
|
||||
};
|
||||
|
||||
/* Size for structure checking (if padding is correct) */
|
||||
#define PSA_SIZE 64
|
||||
|
||||
/* Calculate offset of a field in the above structure
|
||||
* Warning : only even addresses are used */
|
||||
#define psaoff(p, f) ((unsigned short) ((void *)(&((psa_t *) ((void *) NULL + (p)))->f) - (void *) NULL))
|
||||
|
||||
/******************** MODEM MANAGEMENT INTERFACE ********************/
|
||||
|
||||
/*
|
||||
* Modem Management Controller (MMC) write structure.
|
||||
*/
|
||||
typedef struct mmw_t mmw_t;
|
||||
struct mmw_t {
|
||||
unsigned char mmw_encr_key[8]; /* encryption key */
|
||||
unsigned char mmw_encr_enable; /* enable/disable encryption */
|
||||
#define MMW_ENCR_ENABLE_MODE 0x02 /* Mode of security option */
|
||||
#define MMW_ENCR_ENABLE_EN 0x01 /* Enable security option */
|
||||
unsigned char mmw_unused0[1]; /* unused */
|
||||
unsigned char mmw_des_io_invert; /* Encryption option */
|
||||
#define MMW_DES_IO_INVERT_RES 0x0F /* Reserved */
|
||||
#define MMW_DES_IO_INVERT_CTRL 0xF0 /* Control ??? (set to 0) */
|
||||
unsigned char mmw_unused1[5]; /* unused */
|
||||
unsigned char mmw_loopt_sel; /* looptest selection */
|
||||
#define MMW_LOOPT_SEL_DIS_NWID 0x40 /* disable NWID filtering */
|
||||
#define MMW_LOOPT_SEL_INT 0x20 /* activate Attention Request */
|
||||
#define MMW_LOOPT_SEL_LS 0x10 /* looptest w/o collision avoidance */
|
||||
#define MMW_LOOPT_SEL_LT3A 0x08 /* looptest 3a */
|
||||
#define MMW_LOOPT_SEL_LT3B 0x04 /* looptest 3b */
|
||||
#define MMW_LOOPT_SEL_LT3C 0x02 /* looptest 3c */
|
||||
#define MMW_LOOPT_SEL_LT3D 0x01 /* looptest 3d */
|
||||
unsigned char mmw_jabber_enable; /* jabber timer enable */
|
||||
/* Abort transmissions > 200 ms */
|
||||
unsigned char mmw_freeze; /* freeze / unfreeeze signal level */
|
||||
/* 0 : signal level & qual updated for every new message, 1 : frozen */
|
||||
unsigned char mmw_anten_sel; /* antenna selection */
|
||||
#define MMW_ANTEN_SEL_SEL 0x01 /* direct antenna selection */
|
||||
#define MMW_ANTEN_SEL_ALG_EN 0x02 /* antenna selection algo. enable */
|
||||
unsigned char mmw_ifs; /* inter frame spacing */
|
||||
/* min time between transmission in bit periods (.5 us) - bit 0 ignored */
|
||||
unsigned char mmw_mod_delay; /* modem delay (synchro) */
|
||||
unsigned char mmw_jam_time; /* jamming time (after collision) */
|
||||
unsigned char mmw_unused2[1]; /* unused */
|
||||
unsigned char mmw_thr_pre_set; /* level threshold preset */
|
||||
/* Discard all packet with signal < this value (4) */
|
||||
unsigned char mmw_decay_prm; /* decay parameters */
|
||||
unsigned char mmw_decay_updat_prm; /* decay update parameterz */
|
||||
unsigned char mmw_quality_thr; /* quality (z-quotient) threshold */
|
||||
/* Discard all packet with quality < this value (3) */
|
||||
unsigned char mmw_netw_id_l; /* NWID low order byte */
|
||||
unsigned char mmw_netw_id_h; /* NWID high order byte */
|
||||
/* Network ID or Domain : create virtual net on the air */
|
||||
|
||||
/* 2.0 Hardware extension - frequency selection support */
|
||||
unsigned char mmw_mode_select; /* for analog tests (set to 0) */
|
||||
unsigned char mmw_unused3[1]; /* unused */
|
||||
unsigned char mmw_fee_ctrl; /* frequency eeprom control */
|
||||
#define MMW_FEE_CTRL_PRE 0x10 /* Enable protected instructions */
|
||||
#define MMW_FEE_CTRL_DWLD 0x08 /* Download eeprom to mmc */
|
||||
#define MMW_FEE_CTRL_CMD 0x07 /* EEprom commands : */
|
||||
#define MMW_FEE_CTRL_READ 0x06 /* Read */
|
||||
#define MMW_FEE_CTRL_WREN 0x04 /* Write enable */
|
||||
#define MMW_FEE_CTRL_WRITE 0x05 /* Write data to address */
|
||||
#define MMW_FEE_CTRL_WRALL 0x04 /* Write data to all addresses */
|
||||
#define MMW_FEE_CTRL_WDS 0x04 /* Write disable */
|
||||
#define MMW_FEE_CTRL_PRREAD 0x16 /* Read addr from protect register */
|
||||
#define MMW_FEE_CTRL_PREN 0x14 /* Protect register enable */
|
||||
#define MMW_FEE_CTRL_PRCLEAR 0x17 /* Unprotect all registers */
|
||||
#define MMW_FEE_CTRL_PRWRITE 0x15 /* Write addr in protect register */
|
||||
#define MMW_FEE_CTRL_PRDS 0x14 /* Protect register disable */
|
||||
/* Never issue this command (PRDS) : it's irreversible !!! */
|
||||
|
||||
unsigned char mmw_fee_addr; /* EEprom address */
|
||||
#define MMW_FEE_ADDR_CHANNEL 0xF0 /* Select the channel */
|
||||
#define MMW_FEE_ADDR_OFFSET 0x0F /* Offset in channel data */
|
||||
#define MMW_FEE_ADDR_EN 0xC0 /* FEE_CTRL enable operations */
|
||||
#define MMW_FEE_ADDR_DS 0x00 /* FEE_CTRL disable operations */
|
||||
#define MMW_FEE_ADDR_ALL 0x40 /* FEE_CTRL all operations */
|
||||
#define MMW_FEE_ADDR_CLEAR 0xFF /* FEE_CTRL clear operations */
|
||||
|
||||
unsigned char mmw_fee_data_l; /* Write data to EEprom */
|
||||
unsigned char mmw_fee_data_h; /* high octet */
|
||||
unsigned char mmw_ext_ant; /* Setting for external antenna */
|
||||
#define MMW_EXT_ANT_EXTANT 0x01 /* Select external antenna */
|
||||
#define MMW_EXT_ANT_POL 0x02 /* Polarity of the antenna */
|
||||
#define MMW_EXT_ANT_INTERNAL 0x00 /* Internal antenna */
|
||||
#define MMW_EXT_ANT_EXTERNAL 0x03 /* External antenna */
|
||||
#define MMW_EXT_ANT_IQ_TEST 0x1C /* IQ test pattern (set to 0) */
|
||||
} __attribute__((packed));
|
||||
|
||||
/* Size for structure checking (if padding is correct) */
|
||||
#define MMW_SIZE 37
|
||||
|
||||
/* Calculate offset of a field in the above structure */
|
||||
#define mmwoff(p, f) (unsigned short)((void *)(&((mmw_t *)((void *)0 + (p)))->f) - (void *)0)
|
||||
|
||||
|
||||
/*
|
||||
* Modem Management Controller (MMC) read structure.
|
||||
*/
|
||||
typedef struct mmr_t mmr_t;
|
||||
struct mmr_t {
|
||||
unsigned char mmr_unused0[8]; /* unused */
|
||||
unsigned char mmr_des_status; /* encryption status */
|
||||
unsigned char mmr_des_avail; /* encryption available (0x55 read) */
|
||||
#define MMR_DES_AVAIL_DES 0x55 /* DES available */
|
||||
#define MMR_DES_AVAIL_AES 0x33 /* AES (AT&T) available */
|
||||
unsigned char mmr_des_io_invert; /* des I/O invert register */
|
||||
unsigned char mmr_unused1[5]; /* unused */
|
||||
unsigned char mmr_dce_status; /* DCE status */
|
||||
#define MMR_DCE_STATUS_RX_BUSY 0x01 /* receiver busy */
|
||||
#define MMR_DCE_STATUS_LOOPT_IND 0x02 /* loop test indicated */
|
||||
#define MMR_DCE_STATUS_TX_BUSY 0x04 /* transmitter on */
|
||||
#define MMR_DCE_STATUS_JBR_EXPIRED 0x08 /* jabber timer expired */
|
||||
#define MMR_DCE_STATUS 0x0F /* mask to get the bits */
|
||||
unsigned char mmr_dsp_id; /* DSP id (AA = Daedalus rev A) */
|
||||
unsigned char mmr_unused2[2]; /* unused */
|
||||
unsigned char mmr_correct_nwid_l; /* # of correct NWID's rxd (low) */
|
||||
unsigned char mmr_correct_nwid_h; /* # of correct NWID's rxd (high) */
|
||||
/* Warning : Read high order octet first !!! */
|
||||
unsigned char mmr_wrong_nwid_l; /* # of wrong NWID's rxd (low) */
|
||||
unsigned char mmr_wrong_nwid_h; /* # of wrong NWID's rxd (high) */
|
||||
unsigned char mmr_thr_pre_set; /* level threshold preset */
|
||||
#define MMR_THR_PRE_SET 0x3F /* level threshold preset */
|
||||
#define MMR_THR_PRE_SET_CUR 0x80 /* Current signal above it */
|
||||
unsigned char mmr_signal_lvl; /* signal level */
|
||||
#define MMR_SIGNAL_LVL 0x3F /* signal level */
|
||||
#define MMR_SIGNAL_LVL_VALID 0x80 /* Updated since last read */
|
||||
unsigned char mmr_silence_lvl; /* silence level (noise) */
|
||||
#define MMR_SILENCE_LVL 0x3F /* silence level */
|
||||
#define MMR_SILENCE_LVL_VALID 0x80 /* Updated since last read */
|
||||
unsigned char mmr_sgnl_qual; /* signal quality */
|
||||
#define MMR_SGNL_QUAL 0x0F /* signal quality */
|
||||
#define MMR_SGNL_QUAL_ANT 0x80 /* current antenna used */
|
||||
unsigned char mmr_netw_id_l; /* NWID low order byte ??? */
|
||||
unsigned char mmr_unused3[3]; /* unused */
|
||||
|
||||
/* 2.0 Hardware extension - frequency selection support */
|
||||
unsigned char mmr_fee_status; /* Status of frequency eeprom */
|
||||
#define MMR_FEE_STATUS_ID 0xF0 /* Modem revision id */
|
||||
#define MMR_FEE_STATUS_DWLD 0x08 /* Download in progress */
|
||||
#define MMR_FEE_STATUS_BUSY 0x04 /* EEprom busy */
|
||||
unsigned char mmr_unused4[1]; /* unused */
|
||||
unsigned char mmr_fee_data_l; /* Read data from eeprom (low) */
|
||||
unsigned char mmr_fee_data_h; /* Read data from eeprom (high) */
|
||||
};
|
||||
|
||||
/* Size for structure checking (if padding is correct) */
|
||||
#define MMR_SIZE 36
|
||||
|
||||
/* Calculate offset of a field in the above structure */
|
||||
#define mmroff(p, f) (unsigned short)((void *)(&((mmr_t *)((void *)0 + (p)))->f) - (void *)0)
|
||||
|
||||
|
||||
/* Make the two above structures one */
|
||||
typedef union mm_t {
|
||||
struct mmw_t w; /* Write to the mmc */
|
||||
struct mmr_t r; /* Read from the mmc */
|
||||
} mm_t;
|
||||
|
||||
#endif /* _WAVELAN_CS_H */
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user