From 097491a01d07e91a5d71f043bf16261e56d9dc3f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E8=92=B2=E5=85=AC=E8=8B=B1?= <77421578+YANXIAOXIH@users.noreply.github.com> Date: Sun, 9 Feb 2025 09:48:47 -0600 Subject: [PATCH] Add SOM3588-Cat Support Add SOM3588-Cat DTS file Add SOM3588-Cat to Makefile Add jlsemi-dt-phy.h --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-som3588-cat.dts | 1623 +++++++++++++++++ drivers/net/phy/jlsemi-dt-phy.h | 341 ++++ include/dt-bindings/phy/jlsemi-dt-phy.h | 341 ++++ 4 files changed, 2306 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-som3588-cat.dts create mode 100644 drivers/net/phy/jlsemi-dt-phy.h create mode 100644 include/dt-bindings/phy/jlsemi-dt-phy.h diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index bae23ac74e07..647adbacb68b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -411,6 +411,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-radxa-rock-5b+.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5-itx.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-som3588-cat.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mixtile-core3588e.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0-android.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-som3588-cat.dts b/arch/arm64/boot/dts/rockchip/rk3588-som3588-cat.dts new file mode 100644 index 000000000000..d2256c50b81a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-som3588-cat.dts @@ -0,0 +1,1623 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 EmbedFire + */ + +/dts-v1/; + +#include +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include "rk3588.dtsi" +#include "rk3588-linux.dtsi" + + +/ { + model = "SOM3588Cat"; + compatible = "rockchip,som588-cat", "rockchip,rk3588"; + + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 rcupdate.rcu_expedited=1 rcu_nocbs=all"; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + power { + label = "power"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + leds: leds { + status = "okay"; + compatible = "gpio-leds"; + + sys_led: sys-led { + label = "sys_led"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + abc_led: abc-led { + label = "abc_led"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + }; + + def_led: def-led { + label = "def_led"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_5v0: vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + combophy_avdd1v8: combophy-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd1v8"; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s0: vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_sd_s3: vcc-3v3-sd-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vbus_typec: vbus-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec_vbus_en>; + }; + + + mipi_dsi0_power: mipi-dsi0-power-regulator { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi0_power"; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + mipi_dsi1_power: mipi-dsi1-power-regulator { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi1_power"; + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + mipi_dp1_power: mipi-edp-power-regulator { + compatible = "regulator-fixed"; + regulator-name = "mipi_dp1_power"; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + hdmiin_sound: hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip-hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + io-channels = <&saradc 4>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + + previous-song-key { + label = "previoussong"; + linux,code = ; + press-threshold-microvolt = <145000>; + }; + + next-song-key { + label = "nextsong"; + linux,code = ; + press-threshold-microvolt = <290000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm4 0 5000 0>; + cooling-levels = <0 100 150 200 255>; + rockchip,temp-trips = < + 45000 1 + 50000 2 + 55000 3 + 60000 4 + >; + }; + + test-power { + status = "okay"; + }; +}; + +// &pwm11 { +// pinctrl-0 = <&pwm11m1_pins>; +// status = "okay"; +// }; + +&dmc_opp_table { + /delete-node/ opp-2750000000; +}; + +&av1d { + status = "okay"; +}; + +&av1d_mmu { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + upthreshold = <60>; + downdifferential = <30>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_CPU0_WKUP_EN + ) + >; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; + status = "okay"; + + gpio6: gpio-expander@21 { + compatible = "nxp,pca9535"; + status = "okay"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_pca9535_1>; + // interrupt-parent = <&gpio2>; + // interrupts = ; + // interrupt-controller; + // #interrupt-cells = <2>; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + gpio7: gpio-expander@21 { + compatible = "nxp,pca9535"; + status = "okay"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_pca9535_2>; + // interrupt-parent = <&gpio2>; + // interrupts = ; + // interrupt-controller; + // #interrupt-cells = <2>; + }; +}; + + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Typec Controller Fusb302 */ + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb302_int>; + vbus-supply = <&vbus_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_pwrdn>; + + /* 2800mv-3500mv */ + low_voltage_threshold = <3000>; + /* 2700mv-3400mv */ + shutdown_voltage_threshold = <2700>; + /* 140 160 */ + shutdown_temperture_threshold = <160>; + hotdie_temperture_threshold = <115>; + + /* 0: restart PMU; + * 1: reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode; + * 2: Reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode, + * and simultaneously pull down the RESETB PIN for 5mS before releasing + */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806: pinctrl_rk806 { + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null: rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_slp: rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_slp: rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vddq_ddr_s0: DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + avcc_1v8_s0: PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avcc_3v3_s0: PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + avdd_ddr_pll_s0: NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "avdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&tsadc { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pwm4 { + pinctrl-0 = <&pwm4m0_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&pwm6 { + pinctrl-0 = <&pwm6m0_pins>; + status = "okay"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m1_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key_lubancat{ + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xba KEY_POWER>, //电源按键 + <0xb8 KEY_MENU>, //菜单按键 + <0xbc KEY_BACK>, //返回按键 + <0xbb KEY_HOME>, //home键按键 + <0xea KEY_PLAY>, //播放按键 + <0xbf KEY_VOLUMEUP>, //音量加按键 + <0xe6 KEY_VOLUMEDOWN>, //音量键按键 + <0xf6 KEY_FASTFORWARD>, //快进按键 + <0xf8 KEY_FASTREVERSE>, //快退按键 + <0xf2 KEY_BACKSPACE>, //BaskSpace按键 + <0xf3 KEY_1>, //按键1 + <0xe7 KEY_2>, + <0xa1 KEY_3>, + <0xf7 KEY_4>, + <0xe3 KEY_5>, + <0xa5 KEY_6>, + <0xbd KEY_7>, + <0xad KEY_8>, + <0xb5 KEY_9>, + <0xe9 KEY_0>; //按键0 + }; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rkvtunnel { + status = "okay"; +}; + +/* this is a watchdog */ +&wdt { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x20>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x20>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00>; + jl2xxx,led-enable = <(JL2XXX_LED_STATIC_OP_EN | JL1XXX_LED_MODE_EN)>; + jl2xxx,led-mode = <(JL2XXX_LED1_LINK10 | \ + JL2XXX_LED1_LINK100 | \ + JL2XXX_LED1_LINK1000 | \ + JL2XXX_LED2_LINK10 | \ + JL2XXX_LED2_LINK100 | \ + JL2XXX_LED2_LINK1000 | \ + JL2XXX_LED2_ACTIVITY )>; //JL PHY + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00>; + jl2xxx,led-enable = <(JL2XXX_LED_STATIC_OP_EN | JL1XXX_LED_MODE_EN)>; + jl2xxx,led-mode = <(JL2XXX_LED1_LINK10 | \ + JL2XXX_LED1_LINK100 | \ + JL2XXX_LED1_LINK1000 | \ + JL2XXX_LED2_LINK10 | \ + JL2XXX_LED2_LINK100 | \ + JL2XXX_LED2_LINK1000 | \ + JL2XXX_LED2_ACTIVITY )>; //JL PHY + }; +}; + +/* PCIe30 PHY Port0 & Port1 */ +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +// PCIe30 Port0 & Port1: M.2 M-Key +&pcie3x4 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +/* SATA30_HOST0/PCIe20x1_2 Combo PHY */ +&combphy0_ps { + status = "okay"; +}; + +// Mini-PCIe +&sata0 { + status = "okay"; +}; +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + disable-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +/* SATA30_HOST1/PCIe20x1_0 Combo PHY */ +&combphy1_ps { + status = "okay"; +}; + +// M.2 E-Key +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + disable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* USB3.1/DP Combo PHY1 */ +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +/* USB3.1/DP Combo PHY0 */ +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +/* USB3.1 OTG0 Controller */ +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +/* USB2.0 PHY0 */ +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +/* USB30_HOST2/SATA30_HOST2/PCIe20x1_1 Combo PHY */ +&combphy2_psu { + status = "okay"; +}; + +/* USB3.1 HOST2 Controller */ +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB2.0 HOST0 PHY2 */ +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_usb>; + status = "okay"; +}; + +/* USB2.0 HOST0 Controller */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* USB2.0 HOST1 PHY3 */ +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb>; + status = "okay"; +}; + +/* USB2.0 HOST1 Controller */ +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +/* dp0 display */ +&dp0 { + status = "okay"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp1_out_dp0>; +}; + +&route_hdmi1{ + status = "okay"; + connect = <&vp0_out_hdmi1>; +}; + +&dp0_in_vp0 { + status = "disabled"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&hdmi1_in_vp0 { + status = "okay"; +}; + +&hdmi1_in_vp1 { + status = "disabled"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&vop { + status = "okay"; + // disable-win-move; +}; + +&vop_mmu { + status = "okay"; +}; + +&hdmirx_ctrler { + status = "okay"; + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; +}; + +/* HDMI IN Audio */ +&hdmiin_sound { + status = "okay"; +}; + +&i2s7_8ch{ + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + // cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&hdmi1 { + enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + fusb302_int: fusb302-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec_vbus_en: typec-vbus-en { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + sys_led_pin: sys-led-pin { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + io { + pinctrl_pca9535_1: pinctrl-pca9535-1{ + rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pinctrl_pca9535_2: pinctrl-pca9535-2{ + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/drivers/net/phy/jlsemi-dt-phy.h b/drivers/net/phy/jlsemi-dt-phy.h new file mode 100644 index 000000000000..0a6e2210ed05 --- /dev/null +++ b/drivers/net/phy/jlsemi-dt-phy.h @@ -0,0 +1,341 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Device Tree constants for JLSemi PHY + * + * Author: Gangqiao Kuang + * + * Copyright (c) 2021 JLSemi Corporation + */ + +#ifndef _DT_BINDINGS_JLSEMI_PHY_H +#define _DT_BINDINGS_JLSEMI_PHY_H + +/**************************** Linux Version Compatible ********************/ +#define JLSEMI_DEV_COMPATIBLE (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE) +#define JL2XXX_GET_STRING (KERNEL_VERSION(4, 5, 0) <= LINUX_VERSION_CODE) +#define JL2XXX_GET_STAT (KERNEL_VERSION(4, 5, 0) <= LINUX_VERSION_CODE) +#define JL2XXX_PHY_TUNABLE (KERNEL_VERSION(5, 0, 0) <= LINUX_VERSION_CODE) +#define JLSEMI_PHY_WOL (KERNEL_VERSION(3, 10, 0) < LINUX_VERSION_CODE) +/*************************************************************************/ + +/**************************** JLSemi Debug *******************************/ +#define JLSEMI_DEBUG_INFO 0 +/*************************************************************************/ + +/************************* JLSemi Phy Init Reentrant *********************/ +#define JLSEMI_PHY_NOT_REENTRANT false +/*************************************************************************/ + +/**************************** JL1XXX-LED *********************************/ +/* PHY LED Modes Select */ +#define JL1XXX_LED0_STRAP (1 << 0) +#define JL1XXX_LED0_EEE (1 << 1) +#define JL1XXX_LED0_100_ACTIVITY (1 << 2) +#define JL1XXX_LED0_10_ACTIVITY (1 << 3) +#define JL1XXX_LED0_100_LINK (1 << 4) +#define JL1XXX_LED0_10_LINK (1 << 5) +#define JL1XXX_LED1_STRAP (1 << 8) +#define JL1XXX_LED1_EEE (1 << 9) +#define JL1XXX_LED1_100_ACTIVITY (1 << 10) +#define JL1XXX_LED1_10_ACTIVITY (1 << 11) +#define JL1XXX_LED1_100_LINK (1 << 12) +#define JL1XXX_LED1_10_LINK (1 << 13) + +/* PHY LED As Gpio Output Select */ +#define JL1XXX_GPIO_LED0_OUT (1 << 2) +#define JL1XXX_GPIO_LED1_OUT (1 << 3) +#define JL1XXX_GPIO_LED0_EN (1 << 14) +#define JL1XXX_GPIO_LED1_EN (1 << 15) + +/* PHY LED Control Enable Mask Select */ +#define JL1XXX_LED_STATIC_OP_EN (1 << 0) +#define JL1XXX_LED_MODE_EN (1 << 1) +#define JL1XXX_LED_GLOABL_PERIOD_EN (1 << 2) +#define JL1XXX_LED_GLOBAL_ON_EN (1 << 3) +#define JL1XXX_LED_GPIO_OUT_EN (1 << 4) +//-----------------------------------------------------------------------// +/* PHY LED Control Enable Mask Config */ +#define JL1XXX_LED_CTRL_EN (0) + +/* PHY LED Modes Config */ +#define JL1XXX_CFG_LED_MODE (JL1XXX_LED0_100_LINK | \ + JL1XXX_LED0_10_LINK | \ + JL1XXX_LED1_100_ACTIVITY | \ + JL1XXX_LED1_10_ACTIVITY) + +/* PHY LED As Gpio Output Config */ +#define JL1XXX_CFG_GPIO (JL1XXX_GPIO_LED0_EN | \ + JL1XXX_GPIO_LED0_OUT | \ + JL1XXX_GPIO_LED1_EN | \ + JL1XXX_GPIO_LED1_OUT) + +/* PHY LED Global Period Config */ +#define JL1XXX_GLOBAL_PERIOD_MS 0x10 + +/* PHY LED Global Hold On Config */ +#define JL1XXX_GLOBAL_ON_MS 0x8 +/**************************************************************************/ + +/****************************** JL1XXX-WOL ********************************/ +/* PHY WOL Control Enable Mask Select */ +#define JL1XXX_WOL_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY WOL Control Enable Mask Config */ +#define JL1XXX_WOL_CTRL_EN (0) + +/*************************************************************************/ + +/***************************** JL1XXX-INTR *******************************/ +/* PHY Interrupt Control Enable Mask Select */ +#define JL1XXX_INTR_STATIC_OP_EN (1 << 0) +#define JL1XXX_INTR_LINK_CHANGE_EN (1 << 1) +#define JL1XXX_INTR_AN_ERR_EN (1 << 2) +//-----------------------------------------------------------------------// +/* PHY Interrupt Irq Number Config */ +#define JL1XXX_INTR_IRQ -1 + +/* PHY Interrupt Control Enable Mask Config */ +#define JL1XXX_INTR_CTRL_EN (0) +/*************************************************************************/ + +/**************************** JL1XXX-MDI *********************************/ +/* PHY MDI Control Mode Enable Mask Select */ +#define JL1XXX_MDI_STATIC_OP_EN (1 << 0) +#define JL1XXX_MDI_RATE_EN (1 << 1) +#define JL1XXX_MDI_AMPLITUDE_EN (1 << 2) + +/* PHY MDI Rate Select */ +#define JL1XXX_MDI_RATE_STANDARD 0 +#define JL1XXX_MDI_RATE_ACCELERATE 1 + +/* PHY MDI Amplitude Select */ +#define JL1XXX_MDI_AMPLITUDE0 0 +#define JL1XXX_MDI_AMPLITUDE1 1 +#define JL1XXX_MDI_AMPLITUDE2 2 +#define JL1XXX_MDI_AMPLITUDE3 3 +#define JL1XXX_MDI_AMPLITUDE4 4 +#define JL1XXX_MDI_AMPLITUDE5 5 +#define JL1XXX_MDI_AMPLITUDE6 6 +#define JL1XXX_MDI_AMPLITUDE7 7 +//-----------------------------------------------------------------------// +/* PHY MDI Control Mode Enable Mask Config */ +#define JL1XXX_MDI_CTRL_EN (0) + +/* PHY MDI Rate Config */ +#define JL1XXX_MDI_RATE JL1XXX_MDI_RATE_ACCELERATE + +/* PHY MDI Amplitude Config */ +#define JL1XXX_MDI_AMPLITUDE JL1XXX_MDI_AMPLITUDE4 + +/*************************************************************************/ + +/**************************** JL1XXX-RMII ********************************/ +/* PHY RMII Control Mode Enable Mask Select */ +#define JL1XXX_RMII_STATIC_OP_EN (1 << 0) +#define JL1XXX_RMII_MODE_EN (1 << 1) +#define JL1XXX_RMII_CLK_50M_INPUT_EN (1 << 2) +#define JL1XXX_RMII_TX_SKEW_EN (1 << 3) +#define JL1XXX_RMII_RX_SKEW_EN (1 << 4) +#define JL1XXX_RMII_CRS_DV_EN (1 << 5) +//-----------------------------------------------------------------------// +/* PHY RMII Control Mode Enable Mask Config */ +#define JL1XXX_RMII_CTRL_EN (0) + +/* PHY RMII Timing Config */ +#define JL1XXX_RMII_TX_TIMING 0xf +#define JL1XXX_RMII_RX_TIMING 0xf + +/*************************************************************************/ + +/**************************** JL2XXX-LED *********************************/ +/* PHY LED Modes Select*/ +#define JL2XXX_LED0_LINK10 (1 << 0) +#define JL2XXX_LED0_LINK100 (1 << 1) +#define JL2XXX_LED0_LINK1000 (1 << 3) +#define JL2XXX_LED0_ACTIVITY (1 << 4) +#define JL2XXX_LED1_LINK10 (1 << 5) +#define JL2XXX_LED1_LINK100 (1 << 6) +#define JL2XXX_LED1_LINK1000 (1 << 8) +#define JL2XXX_LED1_ACTIVITY (1 << 9) +#define JL2XXX_LED2_LINK10 (1 << 10) +#define JL2XXX_LED2_LINK100 (1 << 11) +#define JL2XXX_LED2_LINK1000 (1 << 13) +#define JL2XXX_LED2_ACTIVITY (1 << 14) +/* mode_A = 0 and mode_B = 1 default mode_A */ +#define JL2XXX_LED_GLB_MODE_B (1 << 15) + +/* PHY LED Polarity Select */ +#define JL2XXX_LED0_POLARITY (1 << 12) +#define JL2XXX_LED1_POLARITY (1 << 11) +#define JL2XXX_LED2_POLARITY (1 << 10) + +/* PHY LED Control Enable Mask Select */ +#define JL2XXX_LED_STATIC_OP_EN (1 << 0) +#define JL2XXX_LED_MODE_EN (1 << 1) +#define JL2XXX_LED_GLOABL_PERIOD_EN (1 << 2) +#define JL2XXX_LED_GLOBAL_ON_EN (1 << 3) +#define JL2XXX_LED_POLARITY_EN (1 << 4) + +//-----------------------------------------------------------------------// +/* PHY LED Control Enable Mask Config */ +#define JL2XXX_LED_CTRL_EN (0) + +/* PHY LED Modes Config */ +#define JL2XXX_CFG_LED_MODE (JL2XXX_LED0_LINK10 | \ + JL2XXX_LED0_ACTIVITY | \ + JL2XXX_LED1_LINK100 | \ + JL2XXX_LED1_ACTIVITY | \ + JL2XXX_LED2_LINK1000 | \ + JL2XXX_LED2_ACTIVITY) + +/* PHY LED Polarity Config */ +#define JL2XXX_LED_POLARITY (JL2XXX_LED0_POLARITY | \ + JL2XXX_LED1_POLARITY | \ + JL2XXX_LED2_POLARITY) + +/* PHY LED Global Period Config */ +#define JL2XXX_GLOBAL_PERIOD_MS 0x3 + +/* PHY LED Global Hold On Config */ +#define JL2XXX_GLOBAL_ON_MS 0x2 +/*************************************************************************/ + +/**************************** JL2XXX-FLD *********************************/ +/* PHY Fast Link Down Control Enable Mask Select */ +#define JL2XXX_FLD_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY Fast Link Down Control Enable Mask Config */ +#define JL2XXX_FLD_CTRL_EN (0) + +/* PHY Fast Link Down Delay Config */ +#define JL2XXX_FLD_DELAY 0 +/*************************************************************************/ + +/**************************** JL2XXX-WOL *********************************/ +/* PHY WOL Control Enable Mask Select */ +#define JL2XXX_WOL_STATIC_OP_EN (1 << 0) + +//-----------------------------------------------------------------------// +/* PHY WOL Control Enable Mask Config */ +#define JL2XXX_WOL_CTRL_EN (0) +/*************************************************************************/ + +/**************************** JL2XXX-INTR ********************************/ +/* PHY Interrupt Control Enable Mask Select */ +#define JL2XXX_INTR_STATIC_OP_EN (1 << 0) +#define JL2XXX_INTR_LINK_CHANGE_EN (1 << 1) +#define JL2XXX_INTR_AN_ERR_EN (1 << 2) +#define JL2XXX_INTR_AN_COMPLETE_EN (1 << 3) +#define JL2XXX_INTR_AN_PAGE_RECE (1 << 4) +//-----------------------------------------------------------------------// +/* PHY Interrupt Irq Number Config */ +#define JL2XXX_INTR_IRQ -1 + +/* PHY Interrupt Control Enable Mask Config */ +#define JL2XXX_INTR_CTRL_EN (0) +/*************************************************************************/ + +/**************************** JL2XXX-DSFT ********************************/ +/* PHY Downshift Control Enable Mask */ +#define JL2XXX_DSFT_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY Downshift Control Enable Config */ +#define JL2XXX_DSFT_CTRL_EN (0) + +/* PHY Downshift Count Config */ +#define JL2XXX_DSFT_AN_CNT 4 +/*************************************************************************/ + +/**************************** JL2XXX-RGMII *******************************/ +/* PHY RGMII Control Mode Enable Mask Select */ +#define JL2XXX_RGMII_STATIC_OP_EN (1 << 0) +#define JL2XXX_RGMII_TX_DLY_EN (1 << 1) +#define JL2XXX_RGMII_RX_DLY_EN (1 << 2) +/* PHY RGMII DELAY BIT */ +#define JL2XXX_RGMII_TX_DLY_2NS (1 << 8) +#define JL2XXX_RGMII_RX_DLY_2NS (1 << 9) +//-----------------------------------------------------------------------// +/* PHY RGMII Control Mode Enable Mask Config */ +#define JL2XXX_RGMII_CTRL_EN (0) + +/*************************************************************************/ + +/**************************** JL2XXX-PATCH *******************************/ +/* PHY Patch Control Mode Enable Mask Select */ +#define JL2XXX_PATCH_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY Patch Control Mode Enable Mask Config */ +#define JL2XXX_PATCH_CTRL_EN (JL2XXX_PATCH_STATIC_OP_EN) + +/*************************************************************************/ + +/**************************** JL2XXX-CLOCK *******************************/ +/* PHY Clock Control Mode Enable Mask Select */ +#define JL2XXX_CLK_STATIC_OP_EN (1 << 0) +#define JL2XXX_25M_CLK_OUT_EN (1 << 1) +#define JL2XXX_125M_CLK_OUT_EN (1 << 2) +#define JL2XXX_CLK_OUT_DIS (1 << 3) +//-----------------------------------------------------------------------// +/* PHY Clock Control Mode Enable Mask Config */ +#define JL2XXX_CLK_CTRL_EN (0) + +/*************************************************************************/ + +/**************************** JL2XXX-WORK_MODE ***************************/ +/* PHY Work Mode Control Mode Enable Mask Select */ +#define JL2XXX_WORK_MODE_STATIC_OP_EN (1 << 0) + +/* PHY Work Mode Select */ +#define JL2XXX_UTP_RGMII_MODE 0 +#define JL2XXX_FIBER_RGMII_MODE 1 +#define JL2XXX_UTP_FIBER_RGMII_MODE 2 +#define JL2XXX_UTP_SGMII_MODE 3 +#define JL2XXX_PHY_SGMII_RGMII_MODE 4 +#define JL2XXX_MAC_SGMII_RGMII_MODE 5 +#define JL2XXX_UTP_FIBER_FORCE_MODE1 6 +#define JL2XXX_UTP_FIBER_FORCE_MODE2 7 +//-----------------------------------------------------------------------// +/* PHY Work Mode Control Mode Enable Mask Config */ +#define JL2XXX_WORK_MODE_CTRL_EN (0) + +/* PHY Work Mode Config */ +#define JL2XXX_WORK_MODE_MODE JL2XXX_UTP_RGMII_MODE + +/*************************************************************************/ + +/**************************** JL2XXX-LOOPBACK ****************************/ +/* PHY Loopback Control Mode Enable Mask Select */ +#define JL2XXX_LPBK_STATIC_OP_EN (1 << 0) + +/* PHY Loopback Mode Select */ +#define JL2XXX_LPBK_PCS_10M 0 +#define JL2XXX_LPBK_PCS_100M 1 +#define JL2XXX_LPBK_PCS_1000M 2 +#define JL2XXX_LPBK_PMD_1000M 3 +#define JL2XXX_LPBK_EXT_STUB_1000M 4 +//-----------------------------------------------------------------------// +/* PHY Loopback Control Mode Enable Mask Config */ +#define JL2XXX_LPBK_CTRL_EN (0) + +/* PHY Loopback Mode Config */ +#define JL2XXX_LPBK_MODE JL2XXX_LPBK_PCS_1000M +/*************************************************************************/ + +/**************************** JL2XXX-SLEW_RATE ****************************/ +/* PHY Slew Rate Control Mode Enable Mask Select */ +#define JL2XXX_SLEW_RATE_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY Slew Rate Control Mode Enable Mask Config */ +#define JL2XXX_SLEW_RATE_CTRL_EN (0) + +/*************************************************************************/ + +/**************************** JL2XXX-RXC_OUT *****************************/ +/* PHY Rx Clock Out Control Mode Enable Mask Select */ +#define JL2XXX_RXC_OUT_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY Rx Clock Out Control Mode Enable Mask Config */ +#define JL2XXX_RXC_OUT_CTRL_EN (0) + +/*************************************************************************/ +#endif diff --git a/include/dt-bindings/phy/jlsemi-dt-phy.h b/include/dt-bindings/phy/jlsemi-dt-phy.h new file mode 100644 index 000000000000..0a6e2210ed05 --- /dev/null +++ b/include/dt-bindings/phy/jlsemi-dt-phy.h @@ -0,0 +1,341 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Device Tree constants for JLSemi PHY + * + * Author: Gangqiao Kuang + * + * Copyright (c) 2021 JLSemi Corporation + */ + +#ifndef _DT_BINDINGS_JLSEMI_PHY_H +#define _DT_BINDINGS_JLSEMI_PHY_H + +/**************************** Linux Version Compatible ********************/ +#define JLSEMI_DEV_COMPATIBLE (KERNEL_VERSION(4, 5, 0) > LINUX_VERSION_CODE) +#define JL2XXX_GET_STRING (KERNEL_VERSION(4, 5, 0) <= LINUX_VERSION_CODE) +#define JL2XXX_GET_STAT (KERNEL_VERSION(4, 5, 0) <= LINUX_VERSION_CODE) +#define JL2XXX_PHY_TUNABLE (KERNEL_VERSION(5, 0, 0) <= LINUX_VERSION_CODE) +#define JLSEMI_PHY_WOL (KERNEL_VERSION(3, 10, 0) < LINUX_VERSION_CODE) +/*************************************************************************/ + +/**************************** JLSemi Debug *******************************/ +#define JLSEMI_DEBUG_INFO 0 +/*************************************************************************/ + +/************************* JLSemi Phy Init Reentrant *********************/ +#define JLSEMI_PHY_NOT_REENTRANT false +/*************************************************************************/ + +/**************************** JL1XXX-LED *********************************/ +/* PHY LED Modes Select */ +#define JL1XXX_LED0_STRAP (1 << 0) +#define JL1XXX_LED0_EEE (1 << 1) +#define JL1XXX_LED0_100_ACTIVITY (1 << 2) +#define JL1XXX_LED0_10_ACTIVITY (1 << 3) +#define JL1XXX_LED0_100_LINK (1 << 4) +#define JL1XXX_LED0_10_LINK (1 << 5) +#define JL1XXX_LED1_STRAP (1 << 8) +#define JL1XXX_LED1_EEE (1 << 9) +#define JL1XXX_LED1_100_ACTIVITY (1 << 10) +#define JL1XXX_LED1_10_ACTIVITY (1 << 11) +#define JL1XXX_LED1_100_LINK (1 << 12) +#define JL1XXX_LED1_10_LINK (1 << 13) + +/* PHY LED As Gpio Output Select */ +#define JL1XXX_GPIO_LED0_OUT (1 << 2) +#define JL1XXX_GPIO_LED1_OUT (1 << 3) +#define JL1XXX_GPIO_LED0_EN (1 << 14) +#define JL1XXX_GPIO_LED1_EN (1 << 15) + +/* PHY LED Control Enable Mask Select */ +#define JL1XXX_LED_STATIC_OP_EN (1 << 0) +#define JL1XXX_LED_MODE_EN (1 << 1) +#define JL1XXX_LED_GLOABL_PERIOD_EN (1 << 2) +#define JL1XXX_LED_GLOBAL_ON_EN (1 << 3) +#define JL1XXX_LED_GPIO_OUT_EN (1 << 4) +//-----------------------------------------------------------------------// +/* PHY LED Control Enable Mask Config */ +#define JL1XXX_LED_CTRL_EN (0) + +/* PHY LED Modes Config */ +#define JL1XXX_CFG_LED_MODE (JL1XXX_LED0_100_LINK | \ + JL1XXX_LED0_10_LINK | \ + JL1XXX_LED1_100_ACTIVITY | \ + JL1XXX_LED1_10_ACTIVITY) + +/* PHY LED As Gpio Output Config */ +#define JL1XXX_CFG_GPIO (JL1XXX_GPIO_LED0_EN | \ + JL1XXX_GPIO_LED0_OUT | \ + JL1XXX_GPIO_LED1_EN | \ + JL1XXX_GPIO_LED1_OUT) + +/* PHY LED Global Period Config */ +#define JL1XXX_GLOBAL_PERIOD_MS 0x10 + +/* PHY LED Global Hold On Config */ +#define JL1XXX_GLOBAL_ON_MS 0x8 +/**************************************************************************/ + +/****************************** JL1XXX-WOL ********************************/ +/* PHY WOL Control Enable Mask Select */ +#define JL1XXX_WOL_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY WOL Control Enable Mask Config */ +#define JL1XXX_WOL_CTRL_EN (0) + +/*************************************************************************/ + +/***************************** JL1XXX-INTR *******************************/ +/* PHY Interrupt Control Enable Mask Select */ +#define JL1XXX_INTR_STATIC_OP_EN (1 << 0) +#define JL1XXX_INTR_LINK_CHANGE_EN (1 << 1) +#define JL1XXX_INTR_AN_ERR_EN (1 << 2) +//-----------------------------------------------------------------------// +/* PHY Interrupt Irq Number Config */ +#define JL1XXX_INTR_IRQ -1 + +/* PHY Interrupt Control Enable Mask Config */ +#define JL1XXX_INTR_CTRL_EN (0) +/*************************************************************************/ + +/**************************** JL1XXX-MDI *********************************/ +/* PHY MDI Control Mode Enable Mask Select */ +#define JL1XXX_MDI_STATIC_OP_EN (1 << 0) +#define JL1XXX_MDI_RATE_EN (1 << 1) +#define JL1XXX_MDI_AMPLITUDE_EN (1 << 2) + +/* PHY MDI Rate Select */ +#define JL1XXX_MDI_RATE_STANDARD 0 +#define JL1XXX_MDI_RATE_ACCELERATE 1 + +/* PHY MDI Amplitude Select */ +#define JL1XXX_MDI_AMPLITUDE0 0 +#define JL1XXX_MDI_AMPLITUDE1 1 +#define JL1XXX_MDI_AMPLITUDE2 2 +#define JL1XXX_MDI_AMPLITUDE3 3 +#define JL1XXX_MDI_AMPLITUDE4 4 +#define JL1XXX_MDI_AMPLITUDE5 5 +#define JL1XXX_MDI_AMPLITUDE6 6 +#define JL1XXX_MDI_AMPLITUDE7 7 +//-----------------------------------------------------------------------// +/* PHY MDI Control Mode Enable Mask Config */ +#define JL1XXX_MDI_CTRL_EN (0) + +/* PHY MDI Rate Config */ +#define JL1XXX_MDI_RATE JL1XXX_MDI_RATE_ACCELERATE + +/* PHY MDI Amplitude Config */ +#define JL1XXX_MDI_AMPLITUDE JL1XXX_MDI_AMPLITUDE4 + +/*************************************************************************/ + +/**************************** JL1XXX-RMII ********************************/ +/* PHY RMII Control Mode Enable Mask Select */ +#define JL1XXX_RMII_STATIC_OP_EN (1 << 0) +#define JL1XXX_RMII_MODE_EN (1 << 1) +#define JL1XXX_RMII_CLK_50M_INPUT_EN (1 << 2) +#define JL1XXX_RMII_TX_SKEW_EN (1 << 3) +#define JL1XXX_RMII_RX_SKEW_EN (1 << 4) +#define JL1XXX_RMII_CRS_DV_EN (1 << 5) +//-----------------------------------------------------------------------// +/* PHY RMII Control Mode Enable Mask Config */ +#define JL1XXX_RMII_CTRL_EN (0) + +/* PHY RMII Timing Config */ +#define JL1XXX_RMII_TX_TIMING 0xf +#define JL1XXX_RMII_RX_TIMING 0xf + +/*************************************************************************/ + +/**************************** JL2XXX-LED *********************************/ +/* PHY LED Modes Select*/ +#define JL2XXX_LED0_LINK10 (1 << 0) +#define JL2XXX_LED0_LINK100 (1 << 1) +#define JL2XXX_LED0_LINK1000 (1 << 3) +#define JL2XXX_LED0_ACTIVITY (1 << 4) +#define JL2XXX_LED1_LINK10 (1 << 5) +#define JL2XXX_LED1_LINK100 (1 << 6) +#define JL2XXX_LED1_LINK1000 (1 << 8) +#define JL2XXX_LED1_ACTIVITY (1 << 9) +#define JL2XXX_LED2_LINK10 (1 << 10) +#define JL2XXX_LED2_LINK100 (1 << 11) +#define JL2XXX_LED2_LINK1000 (1 << 13) +#define JL2XXX_LED2_ACTIVITY (1 << 14) +/* mode_A = 0 and mode_B = 1 default mode_A */ +#define JL2XXX_LED_GLB_MODE_B (1 << 15) + +/* PHY LED Polarity Select */ +#define JL2XXX_LED0_POLARITY (1 << 12) +#define JL2XXX_LED1_POLARITY (1 << 11) +#define JL2XXX_LED2_POLARITY (1 << 10) + +/* PHY LED Control Enable Mask Select */ +#define JL2XXX_LED_STATIC_OP_EN (1 << 0) +#define JL2XXX_LED_MODE_EN (1 << 1) +#define JL2XXX_LED_GLOABL_PERIOD_EN (1 << 2) +#define JL2XXX_LED_GLOBAL_ON_EN (1 << 3) +#define JL2XXX_LED_POLARITY_EN (1 << 4) + +//-----------------------------------------------------------------------// +/* PHY LED Control Enable Mask Config */ +#define JL2XXX_LED_CTRL_EN (0) + +/* PHY LED Modes Config */ +#define JL2XXX_CFG_LED_MODE (JL2XXX_LED0_LINK10 | \ + JL2XXX_LED0_ACTIVITY | \ + JL2XXX_LED1_LINK100 | \ + JL2XXX_LED1_ACTIVITY | \ + JL2XXX_LED2_LINK1000 | \ + JL2XXX_LED2_ACTIVITY) + +/* PHY LED Polarity Config */ +#define JL2XXX_LED_POLARITY (JL2XXX_LED0_POLARITY | \ + JL2XXX_LED1_POLARITY | \ + JL2XXX_LED2_POLARITY) + +/* PHY LED Global Period Config */ +#define JL2XXX_GLOBAL_PERIOD_MS 0x3 + +/* PHY LED Global Hold On Config */ +#define JL2XXX_GLOBAL_ON_MS 0x2 +/*************************************************************************/ + +/**************************** JL2XXX-FLD *********************************/ +/* PHY Fast Link Down Control Enable Mask Select */ +#define JL2XXX_FLD_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY Fast Link Down Control Enable Mask Config */ +#define JL2XXX_FLD_CTRL_EN (0) + +/* PHY Fast Link Down Delay Config */ +#define JL2XXX_FLD_DELAY 0 +/*************************************************************************/ + +/**************************** JL2XXX-WOL *********************************/ +/* PHY WOL Control Enable Mask Select */ +#define JL2XXX_WOL_STATIC_OP_EN (1 << 0) + +//-----------------------------------------------------------------------// +/* PHY WOL Control Enable Mask Config */ +#define JL2XXX_WOL_CTRL_EN (0) +/*************************************************************************/ + +/**************************** JL2XXX-INTR ********************************/ +/* PHY Interrupt Control Enable Mask Select */ +#define JL2XXX_INTR_STATIC_OP_EN (1 << 0) +#define JL2XXX_INTR_LINK_CHANGE_EN (1 << 1) +#define JL2XXX_INTR_AN_ERR_EN (1 << 2) +#define JL2XXX_INTR_AN_COMPLETE_EN (1 << 3) +#define JL2XXX_INTR_AN_PAGE_RECE (1 << 4) +//-----------------------------------------------------------------------// +/* PHY Interrupt Irq Number Config */ +#define JL2XXX_INTR_IRQ -1 + +/* PHY Interrupt Control Enable Mask Config */ +#define JL2XXX_INTR_CTRL_EN (0) +/*************************************************************************/ + +/**************************** JL2XXX-DSFT ********************************/ +/* PHY Downshift Control Enable Mask */ +#define JL2XXX_DSFT_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY Downshift Control Enable Config */ +#define JL2XXX_DSFT_CTRL_EN (0) + +/* PHY Downshift Count Config */ +#define JL2XXX_DSFT_AN_CNT 4 +/*************************************************************************/ + +/**************************** JL2XXX-RGMII *******************************/ +/* PHY RGMII Control Mode Enable Mask Select */ +#define JL2XXX_RGMII_STATIC_OP_EN (1 << 0) +#define JL2XXX_RGMII_TX_DLY_EN (1 << 1) +#define JL2XXX_RGMII_RX_DLY_EN (1 << 2) +/* PHY RGMII DELAY BIT */ +#define JL2XXX_RGMII_TX_DLY_2NS (1 << 8) +#define JL2XXX_RGMII_RX_DLY_2NS (1 << 9) +//-----------------------------------------------------------------------// +/* PHY RGMII Control Mode Enable Mask Config */ +#define JL2XXX_RGMII_CTRL_EN (0) + +/*************************************************************************/ + +/**************************** JL2XXX-PATCH *******************************/ +/* PHY Patch Control Mode Enable Mask Select */ +#define JL2XXX_PATCH_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY Patch Control Mode Enable Mask Config */ +#define JL2XXX_PATCH_CTRL_EN (JL2XXX_PATCH_STATIC_OP_EN) + +/*************************************************************************/ + +/**************************** JL2XXX-CLOCK *******************************/ +/* PHY Clock Control Mode Enable Mask Select */ +#define JL2XXX_CLK_STATIC_OP_EN (1 << 0) +#define JL2XXX_25M_CLK_OUT_EN (1 << 1) +#define JL2XXX_125M_CLK_OUT_EN (1 << 2) +#define JL2XXX_CLK_OUT_DIS (1 << 3) +//-----------------------------------------------------------------------// +/* PHY Clock Control Mode Enable Mask Config */ +#define JL2XXX_CLK_CTRL_EN (0) + +/*************************************************************************/ + +/**************************** JL2XXX-WORK_MODE ***************************/ +/* PHY Work Mode Control Mode Enable Mask Select */ +#define JL2XXX_WORK_MODE_STATIC_OP_EN (1 << 0) + +/* PHY Work Mode Select */ +#define JL2XXX_UTP_RGMII_MODE 0 +#define JL2XXX_FIBER_RGMII_MODE 1 +#define JL2XXX_UTP_FIBER_RGMII_MODE 2 +#define JL2XXX_UTP_SGMII_MODE 3 +#define JL2XXX_PHY_SGMII_RGMII_MODE 4 +#define JL2XXX_MAC_SGMII_RGMII_MODE 5 +#define JL2XXX_UTP_FIBER_FORCE_MODE1 6 +#define JL2XXX_UTP_FIBER_FORCE_MODE2 7 +//-----------------------------------------------------------------------// +/* PHY Work Mode Control Mode Enable Mask Config */ +#define JL2XXX_WORK_MODE_CTRL_EN (0) + +/* PHY Work Mode Config */ +#define JL2XXX_WORK_MODE_MODE JL2XXX_UTP_RGMII_MODE + +/*************************************************************************/ + +/**************************** JL2XXX-LOOPBACK ****************************/ +/* PHY Loopback Control Mode Enable Mask Select */ +#define JL2XXX_LPBK_STATIC_OP_EN (1 << 0) + +/* PHY Loopback Mode Select */ +#define JL2XXX_LPBK_PCS_10M 0 +#define JL2XXX_LPBK_PCS_100M 1 +#define JL2XXX_LPBK_PCS_1000M 2 +#define JL2XXX_LPBK_PMD_1000M 3 +#define JL2XXX_LPBK_EXT_STUB_1000M 4 +//-----------------------------------------------------------------------// +/* PHY Loopback Control Mode Enable Mask Config */ +#define JL2XXX_LPBK_CTRL_EN (0) + +/* PHY Loopback Mode Config */ +#define JL2XXX_LPBK_MODE JL2XXX_LPBK_PCS_1000M +/*************************************************************************/ + +/**************************** JL2XXX-SLEW_RATE ****************************/ +/* PHY Slew Rate Control Mode Enable Mask Select */ +#define JL2XXX_SLEW_RATE_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY Slew Rate Control Mode Enable Mask Config */ +#define JL2XXX_SLEW_RATE_CTRL_EN (0) + +/*************************************************************************/ + +/**************************** JL2XXX-RXC_OUT *****************************/ +/* PHY Rx Clock Out Control Mode Enable Mask Select */ +#define JL2XXX_RXC_OUT_STATIC_OP_EN (1 << 0) +//-----------------------------------------------------------------------// +/* PHY Rx Clock Out Control Mode Enable Mask Config */ +#define JL2XXX_RXC_OUT_CTRL_EN (0) + +/*************************************************************************/ +#endif