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c9268ac615
Currently a number of arch_atomic*_<op>() functions are optional, and where an arch does not provide a given arch_atomic*_<op>() we will define an implementation of arch_atomic*_<op>() in atomic-arch-fallback.h. Filling in the missing ops requires special care as we want to select the optimal definition of each op (e.g. preferentially defining ops in terms of their relaxed form rather than their fully-ordered form). The ifdeffery necessary for this requires us to group ordering variants together, which can be a bit painful to read, and is painful for kerneldoc generation. It would be easier to handle this if we generated ops into a separate namespace, as this would remove the need to take special care with the ifdeffery, and allow each ordering variant to be generated separately. This patch adds a new set of raw_atomic_<op>() definitions, which are currently trivial wrappers of their arch_atomic_<op>() equivalent. This will allow us to move treewide users of arch_atomic_<op>() over to raw atomic op before we rework the fallback generation to generate raw_atomic_<op> directly. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20230605070124.3741859-18-mark.rutland@arm.com
86 lines
2.6 KiB
C
86 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Atomic operations usable in machine independent code */
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#ifndef _LINUX_ATOMIC_H
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#define _LINUX_ATOMIC_H
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#include <linux/types.h>
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#include <asm/atomic.h>
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#include <asm/barrier.h>
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/*
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* Relaxed variants of xchg, cmpxchg and some atomic operations.
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*
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* We support four variants:
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*
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* - Fully ordered: The default implementation, no suffix required.
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* - Acquire: Provides ACQUIRE semantics, _acquire suffix.
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* - Release: Provides RELEASE semantics, _release suffix.
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* - Relaxed: No ordering guarantees, _relaxed suffix.
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*
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* For compound atomics performing both a load and a store, ACQUIRE
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* semantics apply only to the load and RELEASE semantics only to the
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* store portion of the operation. Note that a failed cmpxchg_acquire
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* does -not- imply any memory ordering constraints.
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*
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* See Documentation/memory-barriers.txt for ACQUIRE/RELEASE definitions.
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*/
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#define atomic_cond_read_acquire(v, c) smp_cond_load_acquire(&(v)->counter, (c))
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#define atomic_cond_read_relaxed(v, c) smp_cond_load_relaxed(&(v)->counter, (c))
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#define atomic64_cond_read_acquire(v, c) smp_cond_load_acquire(&(v)->counter, (c))
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#define atomic64_cond_read_relaxed(v, c) smp_cond_load_relaxed(&(v)->counter, (c))
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/*
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* The idea here is to build acquire/release variants by adding explicit
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* barriers on top of the relaxed variant. In the case where the relaxed
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* variant is already fully ordered, no additional barriers are needed.
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*
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* If an architecture overrides __atomic_acquire_fence() it will probably
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* want to define smp_mb__after_spinlock().
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*/
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#ifndef __atomic_acquire_fence
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#define __atomic_acquire_fence smp_mb__after_atomic
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#endif
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#ifndef __atomic_release_fence
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#define __atomic_release_fence smp_mb__before_atomic
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#endif
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#ifndef __atomic_pre_full_fence
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#define __atomic_pre_full_fence smp_mb__before_atomic
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#endif
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#ifndef __atomic_post_full_fence
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#define __atomic_post_full_fence smp_mb__after_atomic
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#endif
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#define __atomic_op_acquire(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret = op##_relaxed(args); \
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__atomic_acquire_fence(); \
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__ret; \
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})
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#define __atomic_op_release(op, args...) \
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({ \
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__atomic_release_fence(); \
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op##_relaxed(args); \
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})
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#define __atomic_op_fence(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret; \
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__atomic_pre_full_fence(); \
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__ret = op##_relaxed(args); \
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__atomic_post_full_fence(); \
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__ret; \
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})
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#include <linux/atomic/atomic-arch-fallback.h>
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#include <linux/atomic/atomic-long.h>
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#include <linux/atomic/atomic-raw.h>
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#include <linux/atomic/atomic-instrumented.h>
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#endif /* _LINUX_ATOMIC_H */
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