Allow SPI masters to define the set of bits_per_word values they support.
If they do this, then the SPI core will reject transfers that attempt to
use an unsupported bits_per_word value. This eliminates the need for each
SPI driver to implement this checking in most cases.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Pull staging tree update from Greg Kroah-Hartman:
"Here's the big staging tree merge for 3.9-rc1
Lots of cleanups and updates for drivers all through the staging tree.
We are pretty much "code neutral" here, adding just about as many
lines as we removed.
All of these have been in linux-next for a while."
* tag 'staging-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (804 commits)
staging: comedi: vmk80xx: wait for URBs to complete
staging: comedi: drivers: addi-data: hwdrv_apci3200.c: Add a missing semicolon
staging: et131x: Update TODO list
staging: et131x: Remove assignment of skb->dev
staging: wlan-ng: hfa384x.h: fix for error reported by smatch
staging/zache checkpatch ERROR: spaces prohibited around that
staging/ozwpan: Mark read only parameters and structs as const
staging/ozwpan: Remove empty and unused function oz_cdev_heartbeat
staging/ozwpan: Mark local functions as static (fix sparse warnings)
staging/ozwpan: Add missing header includes
staging/usbip: Mark local functions as static (fix sparse warnings)
staging/xgifb: Remove duplicated code in loops.
staging/xgifb: Consolidate return paths
staging/xgifb: Remove code without effect
staging/xgifb: Remove unnecessary casts
staging/xgifb: Consolidate if/else if with identical code branches
staging: vt6656: replaced custom TRUE definition with true
staging: vt6656: replaced custom FALSE definition with false
staging: vt6656: replace custom BOOL definition with bool
staging/rtl8187se: Mark functions as static to silence sparse
...
This adds missing kernel-doc entries for cs_gpios in struct spi_master and
cs_gpio in struct spi_device.
Signed-off-by: Andreas Larsson <andreas@gaisler.com>
[grant.likely: tweaked the language of the descriptions]
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Quite often the pattern used for setting up and transferring a synchronous SPI
transaction looks very much like the following:
struct spi_message msg;
struct spi_transfer xfers[] = {
...
};
spi_message_init(&msg);
spi_message_add_tail(&xfers[0], &msg);
...
spi_message_add_tail(&xfers[ARRAY_SIZE(xfers) - 1], &msg);
ret = spi_sync(&msg);
This patch adds two new helper functions for handling this case. The first
helper function spi_message_init_with_transfers() takes a spi_message and an
array of spi_transfers. It will initialize the message and then call
spi_message_add_tail() for each transfer in the array. E.g. the following
spi_message_init(&msg);
spi_message_add_tail(&xfers[0], &msg);
...
spi_message_add_tail(&xfers[ARRAY_SIZE(xfers) - 1], &msg);
can be rewritten as
spi_message_init_with_transfers(&msg, xfers, ARRAY_SIZE(xfers));
The second function spi_sync_transfer() takes a SPI device and an array of
spi_transfers. It will allocate a new spi_message (on the stack) and add all
transfers in the array to the message. Finally it will call spi_sync() on the
message.
E.g. the follwing
struct spi_message msg;
struct spi_transfer xfers[] = {
...
};
spi_message_init(&msg);
spi_message_add_tail(&xfers[0], &msg);
...
spi_message_add_tail(&xfers[ARRAY_SIZE(xfers) - 1], &msg);
ret = spi_sync(spi, &msg);
can be rewritten as
struct spi_transfer xfers[] = {
...
};
ret = spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers));
A coccinelle script to find such instances will follow.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Intel LPSS SPI is pretty much the same as the PXA27xx SPI except that it
has few additional features over the original:
o FIFO depth is 256 entries
o RX FIFO has one watermark
o TX FIFO has two watermarks, low and high
o chip select can be controlled by writing to a register
The new FIFO registers follow immediately the PXA27xx registers but then there
are some additional LPSS private registers at offset 1k or 2k from the base
address. For these private registers we add new accessors that take advantage
of drv_data->lpss_base once it is resolved.
We add a new type LPSS_SSP that can be used to distinguish the LPSS devices
from others.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: Lu Cao <lucao@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
To be able to use DMA with this driver on non-PXA platforms we implement
support for the generic DMA engine API. This lets user to use different DMA
engines with little or no modification to the driver.
Request lines and channel numbers can be passed to the driver from the
platform specific data.
The DMA engine implementation will be selected by default even on PXA
platform. User can select the legacy DMA API by enabling Kconfig option
CONFIG_SPI_PXA2XX_PXADMA.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Lu Cao <lucao@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The PXA SPI driver uses PXA platform specific private DMA implementation
which does not work on non-PXA platforms. In order to use this driver on
other platforms we break out the private DMA implementation into a separate
file that gets compiled only when CONFIG_SPI_PXA2XX_PXADMA is set. The DMA
functions are stubbed out if there is no DMA implementation selected (i.e
we are building on non-PXA platform).
While we are there we can kill the dummy DMA bits in pxa2xx_spi.h as they
are not needed anymore for CE4100.
Once this is done we can add the generic DMA engine support to the driver
that allows usage of any DMA controller that implements DMA engine API.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Lu Cao <lucao@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
SPI_GPIO_NO_MOSI and SPI_GPIO_NO_MISO flags are type casted to unsigned
long, yet, they are to be stored in an unsigned int field in the
spi_gpio_platform_data structure.
This leads to the following warning during compilation on 64 bits systems:
warning: large integer implicitly truncated to unsigned type [-Woverflow]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Convert clk_enable() to clk_prepare_enable() and clk_disable() to
clk_disable_unprepare() respectively in order to support the common clk
framework. Otherwise we get warnings on the console as the clock is not
prepared before it is enabled.
In addition we must cache the maximum clock rate to drv_data->max_clk_rate
at probe time because clk_get_rate() cannot be called in tasklet context.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The spi-pxa2xx-pci glue driver had to implement pxa_ssp_request()/free() in
order to support the spi-pxa2xx platform driver. Since the ACPI enabled
platforms can use the same platform driver we would need to implement
pxa_ssp_request()/free() in some central place that can be shared by the
ACPI and PCI glue code.
Instead of doing that we can make pxa_ssp_request()/free() to be available
only when CONFIG_ARCH_PXA is set. On other arches these are being stubbed
out in preference to passing the ssp_device from the platform data
directly.
We also change the SPI bus number to be taken from ssp->port_id instead of
platform device id. This way the supporting code that passes the ssp can
decide the number (or it can set it to the same as pdev->id).
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This will allow to use gpio for chip select with no modification in the
driver binding
When use the cs-gpios, the gpio number will be passed via the cs_gpio field
and the number of chip select will automatically increased with max(hw cs, gpio cs).
So if for example the controller has 2 CS lines, and the cs-gpios
property looks like this:
cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
Then it should be configured so that num_chipselect = 4 with the
following mapping:
cs0 : &gpio1 0 0
cs1 : native
cs2 : &gpio1 1 0
cs3 : &gpio1 2 0
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: spi-devel-general@lists.sourceforge.net
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
[grant.likely: fixed up type of cs count so min() can do type checking]
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Some platforms need the pendown GPIO debounce time setting programmed.
Since the pendown GPIO is handled by the driver, the debounce time
should also be handled along with the pendown GPIO request.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Pull spi fixes from Mark Brown:
"A bunch of fixes here, mostly minor except for the pl022 which has
just been a bit of a shambles all round, the recent runtime PM changes
have as far as I can tell never worked so they're just getting thrown
out."
* tag 'spi-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc:
spi/pl022: Revert recent runtime PM changes
spi: tsc2005: delete soon-obsolete e-mail address
spi: spi-rspi: fix build error for the latest shdma driver
Remove non-UAPI Kbuild files that have become empty as a result of UAPI
disintegration. They used to have only header-y lines in them and those have
now moved to the Kbuild files in the corresponding uapi/ directories.
Possibly these should not be removed but rather have a comment inserted to say
they are intentionally left blank. This would make it easier to add generated
header lines in future without having to restore the infrastructure.
Note that at this point not all the UAPI disintegration parts have been merged,
so it is likely that more empty Kbuild files will turn up.
It is probably necessary to make the files non-empty to prevent the patch
program from automatically deleting them when it reduces them to nothing.
Signed-off-by: David Howells <dhowells@redhat.com>
Abstract out the common part of private data shared between MMC
and SPI. These shall later allow to use common clock configuration
function.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
