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ARM: remove sirf prima2/atlas platforms

Browse Source 
The SiRF Prima2 and Atlas platform code was contributed by Cambridge
Silicon Radio (CSR) after aquiring the original SiRF company, and
maintained by Barry Song. CSR was subsequently acquired by Qualcomm,
who no longer have an interest in maintaining the SoC platform but
instead have released more recent SoCs for the same market in the
Snapdragon family.

As Barry is no longer working for the company, nobody else there
wants to maintain it, and there are no third-party users, the
best way forward seems to be to completely remove it.

Thanks to Barry for maintaining the platform for the past ten years.

Cc: Barry Song <baohua@kernel.org>
Link: https://lore.kernel.org/lkml/c969392572604b98bcb3be44048c3165@hisilicon.com/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2021-01-18 12:53:11 +01:00
parent a579fcfa8e
commit f3a732843a
27 changed files with 2 additions and 4960 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
Documentation/devicetree/bindings/arm/sirf.yaml
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@@ -1,30 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sirf.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CSR SiRFprimaII and SiRFmarco device tree bindings.
maintainers:
- Binghua Duan <binghua.duan@csr.com>
- Barry Song <Baohua.Song@csr.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- const: sirf,atlas6-cb
- const: sirf,atlas6
- items:
- const: sirf,atlas7-cb
- const: sirf,atlas7
- items:
- const: sirf,prima2-cb
- const: sirf,prima2
additionalProperties: true
...

42
Documentation/devicetree/bindings/reset/sirf,rstc.txt
View File

@@ -1,42 +0,0 @@
CSR SiRFSoC Reset Controller
======================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
example:
rstc: reset-controller@88010000 {
compatible = "sirf,prima2-rstc";
reg = <0x88010000 0x1000>;
#reset-cells = <1>;
};
Specifying reset lines connected to IP modules
==============================================
The reset controller(rstc) manages various reset sources. This module provides
reset signals for most blocks in system. Those device nodes should specify the
reset line on the rstc in their resets property, containing a phandle to the
rstc device node and a RESET_INDEX specifying which module to reset, as described
in reset.txt.
For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.
For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose
rest_bit is in SW_RST1, its RESET_INDEX is 32~63.
example:
vpp@90020000 {
compatible = "sirf,prima2-vpp";
reg = <0x90020000 0x10000>;
interrupts = <31>;
clocks = <&clks 35>;
resets = <&rstc 6>;
};

13
MAINTAINERS
View File

@@ -1779,19 +1779,6 @@ F: drivers/net/ethernet/cortina/
F: drivers/pinctrl/pinctrl-gemini.c
F: drivers/rtc/rtc-ftrtc010.c
ARM/CSR SIRFPRIMA2 MACHINE SUPPORT
M: Barry Song <baohua@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux.git
F: arch/arm/boot/dts/prima2*
F: arch/arm/mach-prima2/
F: drivers/clk/sirf/
F: drivers/clocksource/timer-atlas7.c
F: drivers/clocksource/timer-prima2.c
X: drivers/gnss
N: [^a-z]sirf
ARM/CZ.NIC TURRIS MOX SUPPORT
M: Marek Behun <marek.behun@nic.cz>
S: Maintained

2
arch/arm/Kconfig
View File

@@ -671,8 +671,6 @@ source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-oxnas/Kconfig"
source "arch/arm/mach-prima2/Kconfig"
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"

41
arch/arm/Kconfig.debug
View File

@@ -1142,32 +1142,6 @@ choice
Say Y here if you want kernel low-level debugging support
on Allwinner A31/A23 based platforms on the R_UART.
config DEBUG_SIRFPRIMA2_UART1
bool "Kernel low-level debugging messages via SiRFprimaII UART1"
depends on ARCH_PRIMA2
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart1 port on SiRFprimaII devices.
config DEBUG_SIRFATLAS7_UART0
bool "Kernel low-level debugging messages via SiRFatlas7 UART0"
depends on ARCH_ATLAS7
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart0 port on SiRFATLAS7 devices.The uart0
is used on SiRFATLAS7 as a extra debug port.sometimes an extra
debug port can be very useful.
config DEBUG_SIRFATLAS7_UART1
bool "Kernel low-level debugging messages via SiRFatlas7 UART1"
depends on ARCH_ATLAS7
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart1 port on SiRFATLAS7 devices.
config DEBUG_SPEAR3XX
bool "Kernel low-level debugging messages via ST SPEAr 3xx/6xx UART"
depends on ARCH_SPEAR3XX || ARCH_SPEAR6XX
@@ -1538,10 +1512,6 @@ config DEBUG_STM32_UART
bool
depends on ARCH_STM32
config DEBUG_SIRFSOC_UART
bool
depends on ARCH_SIRF
config DEBUG_UART_FLOW_CONTROL
bool "Enable flow control (CTS) for the debug UART"
depends on DEBUG_LL
@@ -1596,7 +1566,6 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART || DEBUG_S3C64XX_UART
default "debug/s5pv210.S" if DEBUG_S5PV210_UART
default "debug/sirf.S" if DEBUG_SIRFSOC_UART
default "debug/sti.S" if DEBUG_STI_UART
default "debug/stm32.S" if DEBUG_STM32_UART
default "debug/tegra.S" if DEBUG_TEGRA_UART
@@ -1648,8 +1617,6 @@ config DEBUG_UART_PHYS
default 0x1600d000 if DEBUG_SD5203_UART
default 0x18000300 if DEBUG_BCM_5301X
default 0x18000400 if DEBUG_BCM_HR2
default 0x18010000 if DEBUG_SIRFATLAS7_UART0
default 0x18020000 if DEBUG_SIRFATLAS7_UART1
default 0x18023000 if DEBUG_BCM_IPROC_UART3
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
default 0x20001000 if DEBUG_HIP01_UART
@@ -1695,7 +1662,6 @@ config DEBUG_UART_PHYS
default 0x80074000 if DEBUG_IMX28_UART
default 0x808c0000 if DEBUG_EP93XX || ARCH_EP93XX
default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
default 0xb0060000 if DEBUG_SIRFPRIMA2_UART1
default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX
default 0xc0013000 if DEBUG_U300_UART
default 0xc8000000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
@@ -1754,7 +1720,7 @@ config DEBUG_UART_PHYS
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \
DEBUG_DIGICOLOR_UA0 || \
DEBUG_AT91_UART || DEBUG_STM32_UART
config DEBUG_UART_VIRT
@@ -1836,10 +1802,7 @@ config DEBUG_UART_VIRT
default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec10000 if DEBUG_SIRFATLAS7_UART0
default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
default 0xfec20000 if DEBUG_SIRFATLAS7_UART1
default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1
default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART
@@ -1863,7 +1826,7 @@ config DEBUG_UART_VIRT
DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \
DEBUG_DIGICOLOR_UA0 || \
DEBUG_AT91_UART || DEBUG_STM32_UART
config DEBUG_UART_8250_SHIFT

1
arch/arm/Makefile
View File

@@ -209,7 +209,6 @@ machine-$(CONFIG_PLAT_SAMSUNG) += s3c
machine-$(CONFIG_ARCH_S5PV210) += s5pv210
machine-$(CONFIG_ARCH_SA1100) += sa1100
machine-$(CONFIG_ARCH_RENESAS) += shmobile
machine-$(CONFIG_ARCH_SIRF) += prima2
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STI) += sti
machine-$(CONFIG_ARCH_STM32) += stm32

6
arch/arm/boot/dts/Makefile
View File

@@ -74,10 +74,6 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-sama5d4_xplained.dtb \
at91-sama5d4ek.dtb \
at91-vinco.dtb
dtb-$(CONFIG_ARCH_ATLAS6) += \
atlas6-evb.dtb
dtb-$(CONFIG_ARCH_ATLAS7) += \
atlas7-evb.dtb
dtb-$(CONFIG_ARCH_AXXIA) += \
axm5516-amarillo.dtb
dtb-$(CONFIG_ARCH_BCM2835) += \
@@ -886,8 +882,6 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \
owl-s500-labrador-base-m.dtb \
owl-s500-roseapplepi.dtb \
owl-s500-sparky.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
dtb-$(CONFIG_ARCH_PXA) += \
pxa300-raumfeld-connector.dtb \
pxa300-raumfeld-controller.dtb \

78
arch/arm/boot/dts/atlas6-evb.dts
View File

@@ -1,78 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for CSR SiRFatlas6 Evaluation Board
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
/dts-v1/;
/include/ "atlas6.dtsi"
/ {
model = "CSR SiRFatlas6 Evaluation Board";
compatible = "sirf,atlas6-cb", "sirf,atlas6";
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>;
};
axi {
peri-iobg {
uart@b0060000 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>;
};
spi@b00d0000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_a>;
spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
spi@b0170000 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
};
i2c0: i2c@b00e0000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
lcd@40 {
compatible = "sirf,lcd";
reg = <0x40>;
};
};
};
disp-iobg {
lcd@90010000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&lcd_24pins_a>;
};
};
};
display: display@0 {
panels {
panel0: panel@0 {
panel-name = "Innolux TFT";
hactive = <800>;
vactive = <480>;
left_margin = <20>;
right_margin = <234>;
upper_margin = <3>;
lower_margin = <41>;
hsync_len = <3>;
vsync_len = <2>;
pixclock = <33264000>;
sync = <3>;
timing = <0x88>;
};
};
};
};

800
arch/arm/boot/dts/atlas6.dtsi
View File

File diff suppressed because it is too large Load Diff

127
arch/arm/boot/dts/atlas7-evb.dts
View File

@@ -1,127 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for CSR SiRFatlas7 Evaluation Board
*
* Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
/dts-v1/;
/include/ "atlas7.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "CSR SiRFatlas7 Evaluation Board";
compatible = "sirf,atlas7-cb", "sirf,atlas7";
chosen {
bootargs = "console=ttySiRF1,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
vpp_reserved: vpp_mem@5e800000 {
compatible = "sirf,reserved-memory";
reg = <0x5e800000 0x800000>;
};
nanddisk_reserved: nanddisk@46000000 {
reg = <0x46000000 0x200000>;
no-map;
};
};
noc {
mediam {
nand@17050000 {
memory-region = <&nanddisk_reserved>;
};
};
gnssm {
spi1: spi@18200000 {
status = "okay";
spiflash: macronix@0{
status = "okay";
compatible = "macronix,mx25l6405d";
reg = <0>;
spi-max-frequency = <37500000>;
spi-cpha;
spi-cpol;
#address-cells = <1>;
#size-cells = <1>;
partitions@0 {
label = "myspiboot";
reg = <0x0 0x800000>;
};
};
};
};
btm {
uart6: uart@11000000 {
status = "okay";
uart-has-rtscts;
};
};
disp-iobg {
vpp@13110000 {
memory-region = <&vpp_reserved>;
};
};
display0: display@0 {
compatible = "lvds-panel";
source = "lvds.0";
bl-gpios = <&gpio_1 63 0>;
data-lines = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <60000000>;
hactive = <1024>;
vactive = <600>;
hfront-porch = <220>;
hback-porch = <100>;
hsync-len = <1>;
vback-porch = <10>;
vfront-porch = <25>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
gpio_keys {
compatible = "gpio-keys";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
rearview_key {
label = "rearview key";
linux,code = <KEY_CAMERA>;
gpios = <&gpio_1 3 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
};
};
};

1955
arch/arm/boot/dts/atlas7.dtsi
View File

File diff suppressed because it is too large Load Diff

37
arch/arm/boot/dts/prima2-evb.dts
View File

@@ -1,37 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for CSR SiRFprimaII Evaluation Board
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
/dts-v1/;
/include/ "prima2.dtsi"
/ {
model = "CSR SiRFprimaII Evaluation Board";
compatible = "sirf,prima2", "sirf,prima2-cb";
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>;
};
axi {
peri-iobg {
uart@b0060000 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>;
};
spi@b00d0000 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_a>;
};
spi@b0170000 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
};
};
};
};

838
arch/arm/boot/dts/prima2.dtsi
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File diff suppressed because it is too large Load Diff

72
arch/arm/configs/prima2_defconfig
View File

@@ -1,72 +0,0 @@
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_ARCH_SIRF=y
CONFIG_SMP=y
CONFIG_SCHED_MC=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_KEXEC=y
CONFIG_BINFMT_MISC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_INPUT_MISC=y
CONFIG_SERIAL_SIRFSOC=y
CONFIG_SERIAL_SIRFSOC_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_SIRF=y
CONFIG_SPI=y
CONFIG_SPI_SIRF=y
CONFIG_SPI_SPIDEV=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_USB_GADGET=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_SIRF=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_SIRFSOC=y
CONFIG_DMADEVICES=y
CONFIG_DMADEVICES_DEBUG=y
CONFIG_DMADEVICES_VDEBUG=y
CONFIG_SIRF_DMA=y
CONFIG_HWSPINLOCK_SIRF=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_CRC_CCITT=y

40
arch/arm/include/debug/sirf.S
View File

@@ -1,40 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* arch/arm/mach-prima2/include/mach/debug-macro.S
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#define SIRF_LLUART_TXFIFO_STATUS 0x0114
#define SIRF_LLUART_TXFIFO_DATA 0x0118
#define SIRF_LLUART_TXFIFO_FULL (1 << 5)
#ifdef CONFIG_DEBUG_SIRFATLAS7_UART0
#define SIRF_LLUART_TXFIFO_EMPTY (1 << 8)
#else
#define SIRF_LLUART_TXFIFO_EMPTY (1 << 6)
#endif
.macro addruart, rp, rv, tmp
ldr \rp, =CONFIG_DEBUG_UART_PHYS @ physical
ldr \rv, =CONFIG_DEBUG_UART_VIRT @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #SIRF_LLUART_TXFIFO_DATA]
.endm
.macro busyuart,rd,rx
.endm
.macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS]
tst \rd, #SIRF_LLUART_TXFIFO_EMPTY
beq 1001b
.endm

48
arch/arm/mach-prima2/Kconfig
View File

@@ -1,48 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_SIRF
bool "CSR SiRF"
depends on ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
select RESET_CONTROLLER
select GENERIC_IRQ_CHIP
select GPIOLIB
select NO_IOPORT_MAP
select REGMAP
select PINCTRL
select PINCTRL_SIRF
help
Support for CSR SiRFprimaII/Marco/Polo platforms
if ARCH_SIRF
comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features"
config ARCH_ATLAS6
bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
default y
select SIRF_IRQ
help
Support for CSR SiRFSoC ARM Cortex A9 Platform
config ARCH_ATLAS7
bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
default y
select ARM_GIC
select ATLAS7_TIMER
select HAVE_ARM_SCU if SMP
help
Support for CSR SiRFSoC ARM Cortex A7 Platform
config ARCH_PRIMA2
bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
default y
select SIRF_IRQ
select ZONE_DMA
select PRIMA2_TIMER
help
Support for CSR SiRFSoC ARM Cortex A9 Platform
config SIRF_IRQ
bool
endif

9
arch/arm/mach-prima2/Makefile
View File

@@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += rstc.o
obj-y += common.o
obj-y += rtciobrg.o
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
CFLAGS_hotplug.o += -march=armv7-a

64
arch/arm/mach-prima2/common.c
View File

@@ -1,64 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Defines machines for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sizes.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include "common.h"
static void __init __maybe_unused sirfsoc_init_late(void)
{
sirfsoc_pm_init();
}
#ifdef CONFIG_ARCH_ATLAS6
static const char *const atlas6_dt_match[] __initconst = {
"sirf,atlas6",
NULL
};
DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_late = sirfsoc_init_late,
.dt_compat = atlas6_dt_match,
MACHINE_END
#endif
#ifdef CONFIG_ARCH_PRIMA2
static const char *const prima2_dt_match[] __initconst = {
"sirf,prima2",
NULL
};
DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.dma_zone_size = SZ_256M,
.init_late = sirfsoc_init_late,
.dt_compat = prima2_dt_match,
MACHINE_END
#endif
#ifdef CONFIG_ARCH_ATLAS7
static const char *const atlas7_dt_match[] __initconst = {
"sirf,atlas7",
NULL
};
DT_MACHINE_START(ATLAS7_DT, "Generic ATLAS7 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.smp = smp_ops(sirfsoc_smp_ops),
.dt_compat = atlas7_dt_match,
MACHINE_END
#endif

32
arch/arm/mach-prima2/common.h
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@@ -1,32 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* This file contains common function prototypes to avoid externs in the c files.
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#ifndef __MACH_PRIMA2_COMMON_H__
#define __MACH_PRIMA2_COMMON_H__
#include <linux/init.h>
#include <linux/reboot.h>
#include <asm/mach/time.h>
#include <asm/exception.h>
extern volatile int prima2_pen_release;
extern const struct smp_operations sirfsoc_smp_ops;
extern void sirfsoc_secondary_startup(void);
extern void sirfsoc_cpu_die(unsigned int cpu);
extern void __init sirfsoc_of_irq_init(void);
extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
#ifdef CONFIG_SUSPEND
extern int sirfsoc_pm_init(void);
#else
static inline int sirfsoc_pm_init(void) { return 0; }
#endif
#endif

36
arch/arm/mach-prima2/headsmp.S
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@@ -1,36 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Entry of the second core for CSR Marco dual-core SMP SoCs
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/linkage.h>
#include <linux/init.h>
/*
* SIRFSOC specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
* ready for them to initialise.
*/
ENTRY(sirfsoc_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
adr r4, 1f
ldmia r4, {r5, r6}
sub r4, r4, r5
add r6, r6, r4
pen: ldr r7, [r6]
cmp r7, r0
bne pen
/*
* we've been released from the holding pen: secondary_stack
* should now contain the SVC stack for this core
*/
b secondary_startup
ENDPROC(sirfsoc_secondary_startup)
.align
1: .long .
.long prima2_pen_release

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