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Staging: IIO: DDS: AD9832 / AD9835 driver
This is a complete rewrite of the AD9832/35 driver. Purpose was to move this driver to the recently created API for such devices. Changes since V1: IIO: DDS: AD9832 / AD9835 driver: Apply review feedback Save a few bytes, use union for data allocated for spi buffers. Remove use of device IDs. Fix comments. Make master clock mclk always type unsigned long. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Acked-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Michael Hennerich
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
f9a7e9b2f0
commit
ea707584ba
@@ -15,7 +15,10 @@ config AD9832
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depends on SPI
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help
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Say yes here to build support for Analog Devices DDS chip
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ad9832 and ad9835, provides direct access via sysfs.
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AD9832 and AD9835, provides direct access via sysfs.
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To compile this driver as a module, choose M here: the
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module will be called ad9832.
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config AD9834
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tristate "Analog Devices ad9833/4/ driver"
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File diff suppressed because it is too large
Load Diff
128
drivers/staging/iio/dds/ad9832.h
Normal file
128
drivers/staging/iio/dds/ad9832.h
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@@ -0,0 +1,128 @@
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/*
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* AD9832 SPI DDS driver
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*
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* Copyright 2011 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef IIO_DDS_AD9832_H_
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#define IIO_DDS_AD9832_H_
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/* Registers */
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#define AD9832_FREQ0LL 0x0
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#define AD9832_FREQ0HL 0x1
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#define AD9832_FREQ0LM 0x2
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#define AD9832_FREQ0HM 0x3
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#define AD9832_FREQ1LL 0x4
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#define AD9832_FREQ1HL 0x5
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#define AD9832_FREQ1LM 0x6
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#define AD9832_FREQ1HM 0x7
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#define AD9832_PHASE0L 0x8
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#define AD9832_PHASE0H 0x9
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#define AD9832_PHASE1L 0xA
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#define AD9832_PHASE1H 0xB
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#define AD9832_PHASE2L 0xC
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#define AD9832_PHASE2H 0xD
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#define AD9832_PHASE3L 0xE
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#define AD9832_PHASE3H 0xF
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#define AD9832_PHASE_SYM 0x10
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#define AD9832_FREQ_SYM 0x11
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#define AD9832_PINCTRL_EN 0x12
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#define AD9832_OUTPUT_EN 0x13
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/* Command Control Bits */
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#define AD9832_CMD_PHA8BITSW 0x1
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#define AD9832_CMD_PHA16BITSW 0x0
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#define AD9832_CMD_FRE8BITSW 0x3
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#define AD9832_CMD_FRE16BITSW 0x2
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#define AD9832_CMD_FPSELECT 0x6
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#define AD9832_CMD_SYNCSELSRC 0x8
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#define AD9832_CMD_SLEEPRESCLR 0xC
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#define AD9832_FREQ (1 << 11)
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#define AD9832_PHASE(x) (((x) & 3) << 9)
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#define AD9832_SYNC (1 << 13)
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#define AD9832_SELSRC (1 << 12)
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#define AD9832_SLEEP (1 << 13)
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#define AD9832_RESET (1 << 12)
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#define AD9832_CLR (1 << 11)
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#define CMD_SHIFT 12
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#define ADD_SHIFT 8
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#define AD9832_FREQ_BITS 32
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#define AD9832_PHASE_BITS 12
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#define RES_MASK(bits) ((1 << (bits)) - 1)
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/**
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* struct ad9832_state - driver instance specific data
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* @indio_dev: the industrial I/O device
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* @spi: spi_device
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* @reg: supply regulator
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* @mclk: external master clock
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* @ctrl_fp: cached frequency/phase control word
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* @ctrl_ss: cached sync/selsrc control word
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* @ctrl_src: cached sleep/reset/clr word
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* @xfer: default spi transfer
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* @msg: default spi message
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* @freq_xfer: tuning word spi transfer
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* @freq_msg: tuning word spi message
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* @phase_xfer: tuning word spi transfer
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* @phase_msg: tuning word spi message
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* @data: spi transmit buffer
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* @phase_data: tuning word spi transmit buffer
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* @freq_data: tuning word spi transmit buffer
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*/
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struct ad9832_state {
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struct iio_dev *indio_dev;
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struct spi_device *spi;
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struct regulator *reg;
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unsigned long mclk;
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unsigned short ctrl_fp;
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unsigned short ctrl_ss;
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unsigned short ctrl_src;
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struct spi_transfer xfer;
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struct spi_message msg;
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struct spi_transfer freq_xfer[4];
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struct spi_message freq_msg;
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struct spi_transfer phase_xfer[2];
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struct spi_message phase_msg;
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/*
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* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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*/
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union {
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unsigned short freq_data[4]____cacheline_aligned;
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unsigned short phase_data[2];
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unsigned short data;
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};
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};
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/*
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* TODO: struct ad9832_platform_data needs to go into include/linux/iio
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*/
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/**
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* struct ad9832_platform_data - platform specific information
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* @mclk: master clock in Hz
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* @freq0: power up freq0 tuning word in Hz
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* @freq1: power up freq1 tuning word in Hz
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* @phase0: power up phase0 value [0..4095] correlates with 0..2PI
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* @phase1: power up phase1 value [0..4095] correlates with 0..2PI
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* @phase2: power up phase2 value [0..4095] correlates with 0..2PI
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* @phase3: power up phase3 value [0..4095] correlates with 0..2PI
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*/
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struct ad9832_platform_data {
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unsigned long mclk;
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unsigned long freq0;
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unsigned long freq1;
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unsigned short phase0;
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unsigned short phase1;
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unsigned short phase2;
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unsigned short phase3;
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};
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#endif /* IIO_DDS_AD9832_H_ */
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