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HSI: Introduce OMAP SSI driver

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Add OMAP SSI driver to the HSI subsystem.

The Synchronous Serial Interface (SSI) is a legacy version
of HSI. As in the case of HSI, it is mainly used to connect
Application engines (APE) with cellular modem engines (CMT)
in cellular handsets.

It provides a multichannel, full-duplex, multi-core communication
with no reference clock. The OMAP SSI block is capable of reaching
speeds of 110 Mbit/s.

Signed-off-by: Carlos Chinea <carlos.chinea@nokia.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Tested-By: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
This commit is contained in:
Sebastian Reichel
2013-12-15 23:38:58 +01:00
parent a2aa24734d
commit b209e047bc
8 changed files with 2388 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/hsi/Kconfig
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@@ -14,6 +14,7 @@ config HSI_BOARDINFO
bool
default y
source "drivers/hsi/controllers/Kconfig"
source "drivers/hsi/clients/Kconfig"
endif # HSI

1
drivers/hsi/Makefile
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@@ -3,4 +3,5 @@
#
obj-$(CONFIG_HSI_BOARDINFO) += hsi_boardinfo.o
obj-$(CONFIG_HSI) += hsi.o
obj-y += controllers/
obj-y += clients/

19
drivers/hsi/controllers/Kconfig Normal file
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@@ -0,0 +1,19 @@
#
# HSI controllers configuration
#
comment "HSI controllers"
config OMAP_SSI
tristate "OMAP SSI hardware driver"
depends on HSI && OF && (ARCH_OMAP3 || (ARM && COMPILE_TEST))
---help---
SSI is a legacy version of HSI. It is usually used to connect
an application engine with a cellular modem.
If you say Y here, you will enable the OMAP SSI hardware driver.
If unsure, say N.
config OMAP_SSI_PORT
tristate
default m if OMAP_SSI=m
default y if OMAP_SSI=y

6
drivers/hsi/controllers/Makefile Normal file
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@@ -0,0 +1,6 @@
#
# Makefile for HSI controllers drivers
#
obj-$(CONFIG_OMAP_SSI) += omap_ssi.o
obj-$(CONFIG_OMAP_SSI_PORT) += omap_ssi_port.o

625
drivers/hsi/controllers/omap_ssi.c Normal file
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166
drivers/hsi/controllers/omap_ssi.h Normal file
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@@ -0,0 +1,166 @@
/* OMAP SSI internal interface.
*
* Copyright (C) 2010 Nokia Corporation. All rights reserved.
* Copyright (C) 2013 Sebastian Reichel
*
* Contact: Carlos Chinea <carlos.chinea@nokia.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef __LINUX_HSI_OMAP_SSI_H__
#define __LINUX_HSI_OMAP_SSI_H__
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/hsi/hsi.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#define SSI_MAX_CHANNELS 8
#define SSI_MAX_GDD_LCH 8
#define SSI_BYTES_TO_FRAMES(x) ((((x) - 1) >> 2) + 1)
/**
* struct omap_ssm_ctx - OMAP synchronous serial module (TX/RX) context
* @mode: Bit transmission mode
* @channels: Number of channels
* @framesize: Frame size in bits
* @timeout: RX frame timeout
* @divisor: TX divider
* @arb_mode: Arbitration mode for TX frame (Round robin, priority)
*/
struct omap_ssm_ctx {
u32 mode;
u32 channels;
u32 frame_size;
union {
u32 timeout; /* Rx Only */
struct {
u32 arb_mode;
u32 divisor;
}; /* Tx only */
};
};
/**
* struct omap_ssi_port - OMAP SSI port data
* @dev: device associated to the port (HSI port)
* @pdev: platform device associated to the port
* @sst_dma: SSI transmitter physical base address
* @ssr_dma: SSI receiver physical base address
* @sst_base: SSI transmitter base address
* @ssr_base: SSI receiver base address
* @wk_lock: spin lock to serialize access to the wake lines
* @lock: Spin lock to serialize access to the SSI port
* @channels: Current number of channels configured (1,2,4 or 8)
* @txqueue: TX message queues
* @rxqueue: RX message queues
* @brkqueue: Queue of incoming HWBREAK requests (FRAME mode)
* @irq: IRQ number
* @wake_irq: IRQ number for incoming wake line (-1 if none)
* @wake_gpio: GPIO number for incoming wake line (-1 if none)
* @pio_tasklet: Bottom half for PIO transfers and events
* @wake_tasklet: Bottom half for incoming wake events
* @wkin_cken: Keep track of clock references due to the incoming wake line
* @wk_refcount: Reference count for output wake line
* @sys_mpu_enable: Context for the interrupt enable register for irq 0
* @sst: Context for the synchronous serial transmitter
* @ssr: Context for the synchronous serial receiver
*/
struct omap_ssi_port {
struct device *dev;
struct device *pdev;
dma_addr_t sst_dma;
dma_addr_t ssr_dma;
void __iomem *sst_base;
void __iomem *ssr_base;
spinlock_t wk_lock;
spinlock_t lock;
unsigned int channels;
struct list_head txqueue[SSI_MAX_CHANNELS];
struct list_head rxqueue[SSI_MAX_CHANNELS];
struct list_head brkqueue;
unsigned int irq;
int wake_irq;
int wake_gpio;
struct tasklet_struct pio_tasklet;
struct tasklet_struct wake_tasklet;
bool wktest:1; /* FIXME: HACK to be removed */
bool wkin_cken:1; /* Workaround */
unsigned int wk_refcount;
/* OMAP SSI port context */
u32 sys_mpu_enable; /* We use only one irq */
struct omap_ssm_ctx sst;
struct omap_ssm_ctx ssr;
u32 loss_count;
u32 port_id;
#ifdef CONFIG_DEBUG_FS
struct dentry *dir;
#endif
};
/**
* struct gdd_trn - GDD transaction data
* @msg: Pointer to the HSI message being served
* @sg: Pointer to the current sg entry being served
*/
struct gdd_trn {
struct hsi_msg *msg;
struct scatterlist *sg;
};
/**
* struct omap_ssi_controller - OMAP SSI controller data
* @dev: device associated to the controller (HSI controller)
* @sys: SSI I/O base address
* @gdd: GDD I/O base address
* @fck: SSI functional clock
* @gdd_irq: IRQ line for GDD
* @gdd_tasklet: bottom half for DMA transfers
* @gdd_trn: Array of GDD transaction data for ongoing GDD transfers
* @lock: lock to serialize access to GDD
* @loss_count: To follow if we need to restore context or not
* @max_speed: Maximum TX speed (Kb/s) set by the clients.
* @sysconfig: SSI controller saved context
* @gdd_gcr: SSI GDD saved context
* @get_loss: Pointer to omap_pm_get_dev_context_loss_count, if any
* @port: Array of pointers of the ports of the controller
* @dir: Debugfs SSI root directory
*/
struct omap_ssi_controller {
struct device *dev;
void __iomem *sys;
void __iomem *gdd;
struct clk *fck;
unsigned int gdd_irq;
struct tasklet_struct gdd_tasklet;
struct gdd_trn gdd_trn[SSI_MAX_GDD_LCH];
spinlock_t lock;
unsigned long fck_rate;
u32 loss_count;
u32 max_speed;
/* OMAP SSI Controller context */
u32 sysconfig;
u32 gdd_gcr;
int (*get_loss)(struct device *dev);
struct omap_ssi_port **port;
#ifdef CONFIG_DEBUG_FS
struct dentry *dir;
#endif
};
#endif /* __LINUX_HSI_OMAP_SSI_H__ */

1399
drivers/hsi/controllers/omap_ssi_port.c Normal file
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171
drivers/hsi/controllers/omap_ssi_regs.h Normal file
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@@ -0,0 +1,171 @@
/* Hardware definitions for SSI.
*
* Copyright (C) 2010 Nokia Corporation. All rights reserved.
*
* Contact: Carlos Chinea <carlos.chinea@nokia.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef __OMAP_SSI_REGS_H__
#define __OMAP_SSI_REGS_H__
/*
* SSI SYS registers
*/
#define SSI_REVISION_REG 0
# define SSI_REV_MAJOR 0xf0
# define SSI_REV_MINOR 0xf
#define SSI_SYSCONFIG_REG 0x10
# define SSI_AUTOIDLE (1 << 0)
# define SSI_SOFTRESET (1 << 1)
# define SSI_SIDLEMODE_FORCE 0
# define SSI_SIDLEMODE_NO (1 << 3)
# define SSI_SIDLEMODE_SMART (1 << 4)
# define SSI_SIDLEMODE_MASK 0x18
# define SSI_MIDLEMODE_FORCE 0
# define SSI_MIDLEMODE_NO (1 << 12)
# define SSI_MIDLEMODE_SMART (1 << 13)
# define SSI_MIDLEMODE_MASK 0x3000
#define SSI_SYSSTATUS_REG 0x14
# define SSI_RESETDONE 1
#define SSI_MPU_STATUS_REG(port, irq) (0x808 + ((port) * 0x10) + ((irq) * 2))
#define SSI_MPU_ENABLE_REG(port, irq) (0x80c + ((port) * 0x10) + ((irq) * 8))
# define SSI_DATAACCEPT(channel) (1 << (channel))
# define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8))
# define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16))
# define SSI_ERROROCCURED (1 << 24)
# define SSI_BREAKDETECTED (1 << 25)
#define SSI_GDD_MPU_IRQ_STATUS_REG 0x0800
#define SSI_GDD_MPU_IRQ_ENABLE_REG 0x0804
# define SSI_GDD_LCH(channel) (1 << (channel))
#define SSI_WAKE_REG(port) (0xc00 + ((port) * 0x10))
#define SSI_CLEAR_WAKE_REG(port) (0xc04 + ((port) * 0x10))
#define SSI_SET_WAKE_REG(port) (0xc08 + ((port) * 0x10))
# define SSI_WAKE(channel) (1 << (channel))
# define SSI_WAKE_MASK 0xff
/*
* SSI SST registers
*/
#define SSI_SST_ID_REG 0
#define SSI_SST_MODE_REG 4
# define SSI_MODE_VAL_MASK 3
# define SSI_MODE_SLEEP 0
# define SSI_MODE_STREAM 1
# define SSI_MODE_FRAME 2
# define SSI_MODE_MULTIPOINTS 3
#define SSI_SST_FRAMESIZE_REG 8
# define SSI_FRAMESIZE_DEFAULT 31
#define SSI_SST_TXSTATE_REG 0xc
# define SSI_TXSTATE_IDLE 0
#define SSI_SST_BUFSTATE_REG 0x10
# define SSI_FULL(channel) (1 << (channel))
#define SSI_SST_DIVISOR_REG 0x18
# define SSI_MAX_DIVISOR 127
#define SSI_SST_BREAK_REG 0x20
#define SSI_SST_CHANNELS_REG 0x24
# define SSI_CHANNELS_DEFAULT 4
#define SSI_SST_ARBMODE_REG 0x28
# define SSI_ARBMODE_ROUNDROBIN 0
# define SSI_ARBMODE_PRIORITY 1
#define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4))
#define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4))
/*
* SSI SSR registers
*/
#define SSI_SSR_ID_REG 0
#define SSI_SSR_MODE_REG 4
#define SSI_SSR_FRAMESIZE_REG 8
#define SSI_SSR_RXSTATE_REG 0xc
#define SSI_SSR_BUFSTATE_REG 0x10
# define SSI_NOTEMPTY(channel) (1 << (channel))
#define SSI_SSR_BREAK_REG 0x1c
#define SSI_SSR_ERROR_REG 0x20
#define SSI_SSR_ERRORACK_REG 0x24
#define SSI_SSR_OVERRUN_REG 0x2c
#define SSI_SSR_OVERRUNACK_REG 0x30
#define SSI_SSR_TIMEOUT_REG 0x34
# define SSI_TIMEOUT_DEFAULT 0
#define SSI_SSR_CHANNELS_REG 0x28
#define SSI_SSR_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4))
#define SSI_SSR_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4))
/*
* SSI GDD registers
*/
#define SSI_GDD_HW_ID_REG 0
#define SSI_GDD_PPORT_ID_REG 0x10
#define SSI_GDD_MPORT_ID_REG 0x14
#define SSI_GDD_PPORT_SR_REG 0x20
#define SSI_GDD_MPORT_SR_REG 0x24
# define SSI_ACTIVE_LCH_NUM_MASK 0xff
#define SSI_GDD_TEST_REG 0x40
# define SSI_TEST 1
#define SSI_GDD_GCR_REG 0x100
# define SSI_CLK_AUTOGATING_ON (1 << 3)
# define SSI_FREE (1 << 2)
# define SSI_SWITCH_OFF (1 << 0)
#define SSI_GDD_GRST_REG 0x200
# define SSI_SWRESET 1
#define SSI_GDD_CSDP_REG(channel) (0x800 + ((channel) * 0x40))
# define SSI_DST_BURST_EN_MASK 0xc000
# define SSI_DST_SINGLE_ACCESS0 0
# define SSI_DST_SINGLE_ACCESS (1 << 14)
# define SSI_DST_BURST_4x32_BIT (2 << 14)
# define SSI_DST_BURST_8x32_BIT (3 << 14)
# define SSI_DST_MASK 0x1e00
# define SSI_DST_MEMORY_PORT (8 << 9)
# define SSI_DST_PERIPHERAL_PORT (9 << 9)
# define SSI_SRC_BURST_EN_MASK 0x180
# define SSI_SRC_SINGLE_ACCESS0 0
# define SSI_SRC_SINGLE_ACCESS (1 << 7)
# define SSI_SRC_BURST_4x32_BIT (2 << 7)
# define SSI_SRC_BURST_8x32_BIT (3 << 7)
# define SSI_SRC_MASK 0x3c
# define SSI_SRC_MEMORY_PORT (8 << 2)
# define SSI_SRC_PERIPHERAL_PORT (9 << 2)
# define SSI_DATA_TYPE_MASK 3
# define SSI_DATA_TYPE_S32 2
#define SSI_GDD_CCR_REG(channel) (0x802 + ((channel) * 0x40))
# define SSI_DST_AMODE_MASK (3 << 14)
# define SSI_DST_AMODE_CONST 0
# define SSI_DST_AMODE_POSTINC (1 << 12)
# define SSI_SRC_AMODE_MASK (3 << 12)
# define SSI_SRC_AMODE_CONST 0
# define SSI_SRC_AMODE_POSTINC (1 << 12)
# define SSI_CCR_ENABLE (1 << 7)
# define SSI_CCR_SYNC_MASK 0x1f
#define SSI_GDD_CICR_REG(channel) (0x804 + ((channel) * 0x40))
# define SSI_BLOCK_IE (1 << 5)
# define SSI_HALF_IE (1 << 2)
# define SSI_TOUT_IE (1 << 0)
#define SSI_GDD_CSR_REG(channel) (0x806 + ((channel) * 0x40))
# define SSI_CSR_SYNC (1 << 6)
# define SSI_CSR_BLOCK (1 << 5)
# define SSI_CSR_HALF (1 << 2)
# define SSI_CSR_TOUR (1 << 0)
#define SSI_GDD_CSSA_REG(channel) (0x808 + ((channel) * 0x40))
#define SSI_GDD_CDSA_REG(channel) (0x80c + ((channel) * 0x40))
#define SSI_GDD_CEN_REG(channel) (0x810 + ((channel) * 0x40))
#define SSI_GDD_CSAC_REG(channel) (0x818 + ((channel) * 0x40))
#define SSI_GDD_CDAC_REG(channel) (0x81a + ((channel) * 0x40))
#define SSI_GDD_CLNK_CTRL_REG(channel) (0x828 + ((channel) * 0x40))
# define SSI_ENABLE_LNK (1 << 15)
# define SSI_STOP_LNK (1 << 14)
# define SSI_NEXT_CH_ID_MASK 0xf
#endif /* __OMAP_SSI_REGS_H__ */