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ARM: shmobile: Remove legacy board code for KZM-A9-GT
The KZM-A9-GT board is sufficiently supported by DT-based and board-less
SH-Mobile AG5 (sh73a0) multiplatform kernels. Hence remove the legacy
board code to reduce maintenance effort.
Lacking areas are:
- USB (it does't work in legacy, neither),
- LCDC (the LCDC is wired to the legacy INTC, which is not planned to
be supported with DT).
- DMAC/IPMMU (no DT bindings are planned).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven
committed by
Simon Horman
Simon Horman
parent
564ec12832
commit
30f8925a57
@@ -171,14 +171,6 @@ config MACH_MARZEN
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select USE_OF
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config MACH_KZM9G
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bool "KZM-A9-GT board"
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depends on ARCH_SH73A0
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select ARCH_REQUIRE_GPIOLIB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select SND_SOC_AK4642 if SND_SIMPLE_CARD
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select USE_OF
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comment "Renesas ARM SoCs System Configuration"
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config CPU_HAS_INTEVT
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@@ -58,7 +58,6 @@ obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
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obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
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obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
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obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
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obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o intc-sh73a0.o
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endif
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# Framework support
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@@ -3,7 +3,6 @@ loadaddr-y :=
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loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
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loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
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loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
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loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
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loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
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__ZRELADDR := $(sort $(loadaddr-y))
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File diff suppressed because it is too large
Load Diff
@@ -1,410 +0,0 @@
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LIST "KZM9G low-level initialization routine."
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LIST "Adapted from u-boot KZM9G support code."
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LIST "Copyright (C) 2013 Ulrich Hecht"
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LIST "This program is free software; you can redistribute it and/or modify"
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LIST "it under the terms of the GNU General Public License version 2 as"
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LIST "published by the Free Software Foundation."
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LIST "This program is distributed in the hope that it will be useful,"
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LIST "but WITHOUT ANY WARRANTY; without even the implied warranty of"
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LIST "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the"
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LIST "GNU General Public License for more details."
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LIST "Register definitions:"
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LIST "Secure control register"
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#define LIFEC_SEC_SRC (0xE6110008)
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LIST "RWDT"
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#define RWDT_BASE (0xE6020000)
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#define RWTCSRA0 (RWDT_BASE + 0x04)
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LIST "HPB Semaphore Control Registers"
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#define HPBSCR_BASE (0xE6000000)
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#define HPBCTRL6 (HPBSCR_BASE + 0x1030)
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#define SBSC1_BASE (0xFE400000)
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#define SDCR0A (SBSC1_BASE + 0x0008)
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#define SDCR1A (SBSC1_BASE + 0x000C)
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#define SDPCRA (SBSC1_BASE + 0x0010)
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#define SDCR0SA (SBSC1_BASE + 0x0018)
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#define SDCR1SA (SBSC1_BASE + 0x001C)
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#define RTCSRA (SBSC1_BASE + 0x0020)
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#define RTCORA (SBSC1_BASE + 0x0028)
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#define RTCORHA (SBSC1_BASE + 0x002C)
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#define SDWCRC0A (SBSC1_BASE + 0x0040)
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#define SDWCRC1A (SBSC1_BASE + 0x0044)
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#define SDWCR00A (SBSC1_BASE + 0x0048)
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#define SDWCR01A (SBSC1_BASE + 0x004C)
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#define SDWCR10A (SBSC1_BASE + 0x0050)
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#define SDWCR11A (SBSC1_BASE + 0x0054)
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#define SDWCR2A (SBSC1_BASE + 0x0060)
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#define SDWCRC2A (SBSC1_BASE + 0x0064)
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#define ZQCCRA (SBSC1_BASE + 0x0068)
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#define SDMRACR0A (SBSC1_BASE + 0x0084)
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#define SDMRTMPCRA (SBSC1_BASE + 0x008C)
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#define SDMRTMPMSKA (SBSC1_BASE + 0x0094)
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#define SDGENCNTA (SBSC1_BASE + 0x009C)
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#define SDDRVCR0A (SBSC1_BASE + 0x00B4)
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#define DLLCNT0A (SBSC1_BASE + 0x0354)
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#define SDMRA1 (0xFE500000)
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#define SDMRA2 (0xFE5C0000)
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#define SDMRA3 (0xFE504000)
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#define SBSC2_BASE (0xFB400000)
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#define SDCR0B (SBSC2_BASE + 0x0008)
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#define SDCR1B (SBSC2_BASE + 0x000C)
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#define SDPCRB (SBSC2_BASE + 0x0010)
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#define SDCR0SB (SBSC2_BASE + 0x0018)
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#define SDCR1SB (SBSC2_BASE + 0x001C)
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#define RTCSRB (SBSC2_BASE + 0x0020)
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#define RTCORB (SBSC2_BASE + 0x0028)
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#define RTCORHB (SBSC2_BASE + 0x002C)
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#define SDWCRC0B (SBSC2_BASE + 0x0040)
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#define SDWCRC1B (SBSC2_BASE + 0x0044)
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#define SDWCR00B (SBSC2_BASE + 0x0048)
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#define SDWCR01B (SBSC2_BASE + 0x004C)
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#define SDWCR10B (SBSC2_BASE + 0x0050)
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#define SDWCR11B (SBSC2_BASE + 0x0054)
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#define SDPDCR0B (SBSC2_BASE + 0x0058)
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#define SDWCR2B (SBSC2_BASE + 0x0060)
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#define SDWCRC2B (SBSC2_BASE + 0x0064)
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#define ZQCCRB (SBSC2_BASE + 0x0068)
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#define SDMRACR0B (SBSC2_BASE + 0x0084)
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#define SDMRTMPCRB (SBSC2_BASE + 0x008C)
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#define SDMRTMPMSKB (SBSC2_BASE + 0x0094)
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#define SDGENCNTB (SBSC2_BASE + 0x009C)
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#define DPHYCNT0B (SBSC2_BASE + 0x00A0)
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#define DPHYCNT1B (SBSC2_BASE + 0x00A4)
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#define DPHYCNT2B (SBSC2_BASE + 0x00A8)
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#define SDDRVCR0B (SBSC2_BASE + 0x00B4)
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#define DLLCNT0B (SBSC2_BASE + 0x0354)
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#define SDMRB1 (0xFB500000)
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#define SDMRB2 (0xFB5C0000)
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#define SDMRB3 (0xFB504000)
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#define CPG_BASE (0xE6150000)
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#define FRQCRA (CPG_BASE + 0x0000)
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#define FRQCRB (CPG_BASE + 0x0004)
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#define FRQCRD (CPG_BASE + 0x00E4)
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#define VCLKCR1 (CPG_BASE + 0x0008)
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#define VCLKCR2 (CPG_BASE + 0x000C)
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#define VCLKCR3 (CPG_BASE + 0x001C)
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#define ZBCKCR (CPG_BASE + 0x0010)
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#define FLCKCR (CPG_BASE + 0x0014)
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#define SD0CKCR (CPG_BASE + 0x0074)
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#define SD1CKCR (CPG_BASE + 0x0078)
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#define SD2CKCR (CPG_BASE + 0x007C)
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#define FSIACKCR (CPG_BASE + 0x0018)
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#define SUBCKCR (CPG_BASE + 0x0080)
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#define SPUACKCR (CPG_BASE + 0x0084)
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#define SPUVCKCR (CPG_BASE + 0x0094)
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#define MSUCKCR (CPG_BASE + 0x0088)
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#define HSICKCR (CPG_BASE + 0x008C)
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#define FSIBCKCR (CPG_BASE + 0x0090)
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#define MFCK1CR (CPG_BASE + 0x0098)
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#define MFCK2CR (CPG_BASE + 0x009C)
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#define DSITCKCR (CPG_BASE + 0x0060)
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#define DSI0PCKCR (CPG_BASE + 0x0064)
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#define DSI1PCKCR (CPG_BASE + 0x0068)
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#define DSI0PHYCR (CPG_BASE + 0x006C)
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#define DVFSCR3 (CPG_BASE + 0x0174)
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#define DVFSCR4 (CPG_BASE + 0x0178)
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#define DVFSCR5 (CPG_BASE + 0x017C)
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#define MPMODE (CPG_BASE + 0x00CC)
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#define PLLECR (CPG_BASE + 0x00D0)
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#define PLL0CR (CPG_BASE + 0x00D8)
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#define PLL1CR (CPG_BASE + 0x0028)
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#define PLL2CR (CPG_BASE + 0x002C)
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#define PLL3CR (CPG_BASE + 0x00DC)
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#define PLL0STPCR (CPG_BASE + 0x00F0)
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#define PLL1STPCR (CPG_BASE + 0x00C8)
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#define PLL2STPCR (CPG_BASE + 0x00F8)
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#define PLL3STPCR (CPG_BASE + 0x00FC)
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#define RMSTPCR0 (CPG_BASE + 0x0110)
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#define RMSTPCR1 (CPG_BASE + 0x0114)
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#define RMSTPCR2 (CPG_BASE + 0x0118)
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#define RMSTPCR3 (CPG_BASE + 0x011C)
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#define RMSTPCR4 (CPG_BASE + 0x0120)
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#define RMSTPCR5 (CPG_BASE + 0x0124)
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#define SMSTPCR0 (CPG_BASE + 0x0130)
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#define SMSTPCR2 (CPG_BASE + 0x0138)
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#define SMSTPCR3 (CPG_BASE + 0x013C)
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#define CPGXXCR4 (CPG_BASE + 0x0150)
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#define SRCR0 (CPG_BASE + 0x80A0)
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#define SRCR2 (CPG_BASE + 0x80B0)
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#define SRCR3 (CPG_BASE + 0x80A8)
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#define VREFCR (CPG_BASE + 0x00EC)
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#define PCLKCR (CPG_BASE + 0x1020)
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#define PORT32CR (0xE6051020)
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#define PORT33CR (0xE6051021)
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#define PORT34CR (0xE6051022)
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#define PORT35CR (0xE6051023)
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LIST "DRAM initialization code:"
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EW RWTCSRA0, 0xA507
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ED_AND LIFEC_SEC_SRC, 0xFFFF7FFF
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ED_AND SMSTPCR3,0xFFFF7FFF
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ED_AND SRCR3, 0xFFFF7FFF
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ED_AND SMSTPCR2,0xFFFBFFFF
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ED_AND SRCR2, 0xFFFBFFFF
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ED PLLECR, 0x00000000
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WAIT_MASK PLLECR, 0x00000F00, 0x00000000
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WAIT_MASK FRQCRB, 0x80000000, 0x00000000
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ED PLL0CR, 0x2D000000
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ED PLL1CR, 0x17100000
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ED FRQCRB, 0x96235880
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WAIT_MASK FRQCRB, 0x80000000, 0x00000000
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ED FLCKCR, 0x0000000B
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ED_AND SMSTPCR0, 0xFFFFFFFD
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ED_AND SRCR0, 0xFFFFFFFD
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ED 0xE6001628, 0x514
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ED 0xE6001648, 0x514
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ED 0xE6001658, 0x514
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ED 0xE6001678, 0x514
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ED DVFSCR4, 0x00092000
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ED DVFSCR5, 0x000000DC
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ED PLLECR, 0x00000000
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WAIT_MASK PLLECR, 0x00000F00, 0x00000000
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ED FRQCRA, 0x0012453C
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ED FRQCRB, 0x80431350
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WAIT_MASK FRQCRB, 0x80000000, 0x00000000
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ED FRQCRD, 0x00000B0B
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WAIT_MASK FRQCRD, 0x80000000, 0x00000000
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ED PCLKCR, 0x00000003
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ED VCLKCR1, 0x0000012F
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ED VCLKCR2, 0x00000119
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ED VCLKCR3, 0x00000119
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ED ZBCKCR, 0x00000002
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ED FLCKCR, 0x00000005
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ED SD0CKCR, 0x00000080
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ED SD1CKCR, 0x00000080
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ED SD2CKCR, 0x00000080
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ED FSIACKCR, 0x0000003F
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ED FSIBCKCR, 0x0000003F
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ED SUBCKCR, 0x00000080
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ED SPUACKCR, 0x0000000B
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ED SPUVCKCR, 0x0000000B
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ED MSUCKCR, 0x0000013F
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ED HSICKCR, 0x00000080
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ED MFCK1CR, 0x0000003F
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ED MFCK2CR, 0x0000003F
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ED DSITCKCR, 0x00000107
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ED DSI0PCKCR, 0x00000313
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ED DSI1PCKCR, 0x0000130D
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ED DSI0PHYCR, 0x2A800E0E
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ED PLL0CR, 0x1E000000
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ED PLL0CR, 0x2D000000
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ED PLL1CR, 0x17100000
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ED PLL2CR, 0x27000080
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ED PLL3CR, 0x1D000000
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ED PLL0STPCR, 0x00080000
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ED PLL1STPCR, 0x000120C0
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ED PLL2STPCR, 0x00012000
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ED PLL3STPCR, 0x00000030
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ED PLLECR, 0x0000000B
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WAIT_MASK PLLECR, 0x00000B00, 0x00000B00
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ED DVFSCR3, 0x000120F0
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ED MPMODE, 0x00000020
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ED VREFCR, 0x0000028A
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ED RMSTPCR0, 0xE4628087
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ED RMSTPCR1, 0xFFFFFFFF
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ED RMSTPCR2, 0x53FFFFFF
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ED RMSTPCR3, 0xFFFFFFFF
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ED RMSTPCR4, 0x00800D3D
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ED RMSTPCR5, 0xFFFFF3FF
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ED SMSTPCR2, 0x00000000
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ED SRCR2, 0x00040000
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ED_AND PLLECR, 0xFFFFFFF7
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WAIT_MASK PLLECR, 0x00000800, 0x00000000
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LIST "set SBSC operational"
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ED HPBCTRL6, 0x00000001
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WAIT_MASK HPBCTRL6, 0x00000001, 0x00000001
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LIST "set SBSC operating frequency"
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ED FRQCRD, 0x00001414
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WAIT_MASK FRQCRD, 0x80000000, 0x00000000
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ED PLL3CR, 0x1D000000
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ED_OR PLLECR, 0x00000008
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WAIT_MASK PLLECR, 0x00000800, 0x00000800
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LIST "enable DLL oscillation in DDRPHY"
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ED_OR DLLCNT0A, 0x00000002
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LIST "wait >= 100 ns"
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ED SDGENCNTA, 0x00000005
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WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
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LIST "target LPDDR2 device settings"
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ED SDCR0A, 0xACC90159
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ED SDCR1A, 0x00010059
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ED SDWCRC0A, 0x50874114
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ED SDWCRC1A, 0x33199B37
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ED SDWCRC2A, 0x008F2313
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ED SDWCR00A, 0x31020707
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ED SDWCR01A, 0x0017040A
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ED SDWCR10A, 0x31020707
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ED SDWCR11A, 0x0017040A
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ED SDDRVCR0A, 0x055557ff
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ED SDWCR2A, 0x30000000
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LIST "drive CKE high"
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ED_OR SDPCRA, 0x00000080
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WAIT_MASK SDPCRA, 0x00000080, 0x00000080
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LIST "wait >= 200 us"
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ED SDGENCNTA, 0x00002710
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WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
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LIST "issue reset command to LPDDR2 device"
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ED SDMRACR0A, 0x0000003F
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ED SDMRA1, 0x00000000
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LIST "wait >= 10 (or 1) us (docs inconsistent)"
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ED SDGENCNTA, 0x000001F4
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WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
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LIST "MRW ZS initialization calibration command"
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ED SDMRACR0A, 0x0000FF0A
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ED SDMRA3, 0x00000000
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LIST "wait >= 1 us"
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ED SDGENCNTA, 0x00000032
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WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
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LIST "specify operating mode in LPDDR2"
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ED SDMRACR0A, 0x00002201
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ED SDMRA1, 0x00000000
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ED SDMRACR0A, 0x00000402
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ED SDMRA1, 0x00000000
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ED SDMRACR0A, 0x00000203
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ED SDMRA1, 0x00000000
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LIST "initialize DDR interface"
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ED SDMRA2, 0x00000000
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LIST "temperature sensor control"
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ED SDMRTMPCRA, 0x88800004
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ED SDMRTMPMSKA,0x00000004
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LIST "auto-refreshing control"
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ED RTCORA, 0xA55A0032
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ED RTCORHA, 0xA55A000C
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ED RTCSRA, 0xA55A2048
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ED_OR SDCR0A, 0x00000800
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ED_OR SDCR1A, 0x00000400
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LIST "auto ZQ calibration control"
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ED ZQCCRA, 0xFFF20000
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ED_OR DLLCNT0B, 0x00000002
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ED SDGENCNTB, 0x00000005
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WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
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ED SDCR0B, 0xACC90159
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ED SDCR1B, 0x00010059
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ED SDWCRC0B, 0x50874114
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ED SDWCRC1B, 0x33199B37
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ED SDWCRC2B, 0x008F2313
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ED SDWCR00B, 0x31020707
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ED SDWCR01B, 0x0017040A
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ED SDWCR10B, 0x31020707
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ED SDWCR11B, 0x0017040A
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ED SDDRVCR0B, 0x055557ff
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ED SDWCR2B, 0x30000000
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ED_OR SDPCRB, 0x00000080
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WAIT_MASK SDPCRB, 0x00000080, 0x00000080
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ED SDGENCNTB, 0x00002710
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WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
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ED SDMRACR0B, 0x0000003F
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LIST "upstream u-boot writes to SDMRA1A for both SBSC 1 and 2, which does"
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LIST "not seem to make a lot of sense..."
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ED SDMRB1, 0x00000000
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ED SDGENCNTB, 0x000001F4
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WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
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ED SDMRACR0B, 0x0000FF0A
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ED SDMRB3, 0x00000000
|
||||
ED SDGENCNTB, 0x00000032
|
||||
WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
|
||||
|
||||
ED SDMRACR0B, 0x00002201
|
||||
ED SDMRB1, 0x00000000
|
||||
ED SDMRACR0B, 0x00000402
|
||||
ED SDMRB1, 0x00000000
|
||||
ED SDMRACR0B, 0x00000203
|
||||
ED SDMRB1, 0x00000000
|
||||
ED SDMRB2, 0x00000000
|
||||
ED SDMRTMPCRB, 0x88800004
|
||||
ED SDMRTMPMSKB, 0x00000004
|
||||
ED RTCORB, 0xA55A0032
|
||||
ED RTCORHB, 0xA55A000C
|
||||
ED RTCSRB, 0xA55A2048
|
||||
ED_OR SDCR0B, 0x00000800
|
||||
ED_OR SDCR1B, 0x00000400
|
||||
ED ZQCCRB, 0xFFF20000
|
||||
ED_OR SDPDCR0B, 0x00030000
|
||||
ED DPHYCNT1B, 0xA5390000
|
||||
ED DPHYCNT0B, 0x00001200
|
||||
ED DPHYCNT1B, 0x07CE0000
|
||||
ED DPHYCNT0B, 0x00001247
|
||||
WAIT_MASK DPHYCNT2B, 0xFFFFFFFF, 0x07CE0000
|
||||
|
||||
ED_AND SDPDCR0B, 0xFFFCFFFF
|
||||
|
||||
ED FRQCRD, 0x00000B0B
|
||||
WAIT_MASK FRQCRD, 0x80000000, 0x00000000
|
||||
|
||||
ED CPGXXCR4, 0xfffffffc
|
||||
|
||||
LIST "Setup SCIF4 / workaround"
|
||||
EB PORT32CR, 0x12
|
||||
EB PORT33CR, 0x22
|
||||
EB PORT34CR, 0x12
|
||||
EB PORT35CR, 0x22
|
||||
|
||||
EW 0xE6C80000, 0
|
||||
EB 0xE6C80004, 0x19
|
||||
EW 0xE6C80008, 0x0030
|
||||
EW 0xE6C80018, 0
|
||||
EW 0xE6C80030, 0x0014
|
||||
|
||||
LIST "Magic to avoid hangs and corruption on DRAM writes."
|
||||
|
||||
LIST "It has been observed that the system would most often hang while"
|
||||
LIST "decompressing the kernel, and if it didn't it would always write"
|
||||
LIST "a corrupt image to DRAM."
|
||||
LIST "This problem does not occur in u-boot, and the reason is that"
|
||||
LIST "u-boot performs an additional cache invalidation after setting up"
|
||||
LIST "the DRAM controller. Such an invalidation should not be necessary at"
|
||||
LIST "this point, and attempts at removing parts of the routine to arrive"
|
||||
LIST "at the minimal snippet of code necessary to avoid the DRAM stability"
|
||||
LIST "problem yielded the following:"
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 0
|
||||
MCR p15, 0, r0, c1, c0, 0
|
||||
@@ -9,11 +9,6 @@
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
#ifdef CONFIG_MACH_KZM9G
|
||||
#define MEMORY_START 0x43000000
|
||||
#include "mach/head-kzm9g.txt"
|
||||
#else
|
||||
#error "unsupported board."
|
||||
#endif
|
||||
|
||||
#endif /* ZBOOT_H */
|
||||
|
||||
@@ -1,337 +0,0 @@
|
||||
/*
|
||||
* sh73a0 processor support - INTC hardware block
|
||||
*
|
||||
* Copyright (C) 2010 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "intc.h"
|
||||
#include "irqs.h"
|
||||
#include "sh73a0.h"
|
||||
|
||||
enum {
|
||||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources INTCS */
|
||||
PINTCS_PINT1, PINTCS_PINT2,
|
||||
RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3,
|
||||
CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0,
|
||||
RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR,
|
||||
KEYSC_KEY, VINT, MSIOF,
|
||||
TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02,
|
||||
CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2,
|
||||
CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC,
|
||||
RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
|
||||
RTDMAC_3_DEI10, RTDMAC_3_DEI11,
|
||||
FRC, GCU, LCDC1, CSIRX,
|
||||
DSITX0_DSITX00, DSITX0_DSITX01,
|
||||
SPU2_SPU0, SPU2_SPU1, FSI,
|
||||
TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
|
||||
TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW,
|
||||
VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11,
|
||||
DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I,
|
||||
MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I,
|
||||
SPUV,
|
||||
|
||||
/* interrupt groups INTCS */
|
||||
RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3,
|
||||
DSITX0, SPU2, TMU1, MSU,
|
||||
};
|
||||
|
||||
static struct intc_vect intcs_vectors[] = {
|
||||
INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620),
|
||||
INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820),
|
||||
INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860),
|
||||
INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900),
|
||||
INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980),
|
||||
INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0),
|
||||
INTCS_VECT(_2DDMAC_2DDM0, 0x0a00),
|
||||
INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0),
|
||||
INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0),
|
||||
INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80),
|
||||
INTCS_VECT(MSIOF, 0x0d20),
|
||||
INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0),
|
||||
INTCS_VECT(TMU0_TUNI02, 0x0ec0),
|
||||
INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20),
|
||||
INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60),
|
||||
INTCS_VECT(MSUG, 0x0f80),
|
||||
INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0),
|
||||
INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440),
|
||||
INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0),
|
||||
INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560),
|
||||
INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0),
|
||||
INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320),
|
||||
INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360),
|
||||
INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0),
|
||||
INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760),
|
||||
INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0),
|
||||
INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0),
|
||||
INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820),
|
||||
INTCS_VECT(FSI, 0x1840),
|
||||
INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
|
||||
INTCS_VECT(TMU1_TUNI12, 0x1940),
|
||||
INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980),
|
||||
INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20),
|
||||
INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00),
|
||||
INTCS_VECT(SCUW, 0x1b40),
|
||||
INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80),
|
||||
INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0),
|
||||
INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20),
|
||||
INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60),
|
||||
INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0),
|
||||
INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0),
|
||||
INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20),
|
||||
INTCS_VECT(SPUV, 0x2300),
|
||||
};
|
||||
|
||||
static struct intc_group intcs_groups[] __initdata = {
|
||||
INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1,
|
||||
RTDMAC_0_DEI2, RTDMAC_0_DEI3),
|
||||
INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR),
|
||||
INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7,
|
||||
RTDMAC_2_DEI8, RTDMAC_2_DEI9),
|
||||
INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11),
|
||||
INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10),
|
||||
INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01),
|
||||
INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
|
||||
INTC_GROUP(MSU, MSU_MSU, MSU_MSU2),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg intcs_mask_registers[] = {
|
||||
{ 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
|
||||
{ 0, 0, 0, CEU,
|
||||
0, 0, 0, 0 } },
|
||||
{ 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
|
||||
{ 0, 0, 0, VPU,
|
||||
BBIF2, 0, 0, MFI } },
|
||||
{ 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
|
||||
{ 0, 0, 0, _2DDMAC_2DDM0,
|
||||
0, ASA, PEP, ICB } },
|
||||
{ 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
|
||||
{ 0, 0, 0, CTI,
|
||||
JPU_JPEG, 0, LCRC, LCDC } },
|
||||
{ 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
|
||||
{ KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4,
|
||||
RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } },
|
||||
{ 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
|
||||
{ 0, 0, MSIOF, 0,
|
||||
_3DG_SGX543, 0, 0, 0 } },
|
||||
{ 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
|
||||
{ 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00,
|
||||
0, 0, 0, 0 } },
|
||||
{ 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */
|
||||
{ 0, 0, 0, 0,
|
||||
0, MSU_MSU, MSU_MSU2, MSUG } },
|
||||
{ 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
|
||||
{ 0, RWDT0, CMT2, CMT0,
|
||||
0, 0, 0, 0 } },
|
||||
{ 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
|
||||
{ 0, 0, 0, 0,
|
||||
0, TSIF1, LMB, TSIF0 } },
|
||||
{ 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */
|
||||
{ 0, 0, 0, 0,
|
||||
0, 0, PINTCS_PINT2, PINTCS_PINT1 } },
|
||||
{ 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
|
||||
{ RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
|
||||
RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } },
|
||||
{ 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
|
||||
{ FRC, 0, 0, GCU,
|
||||
LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } },
|
||||
{ 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */
|
||||
{ SPU2_SPU0, SPU2_SPU1, FSI, 0,
|
||||
0, 0, 0, 0 } },
|
||||
{ 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
|
||||
{ TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0,
|
||||
TSIF2, CMT4, 0, 0 } },
|
||||
{ 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
|
||||
{ MFIS2, CPORTS2R, 0, 0,
|
||||
0, 0, 0, TSG } },
|
||||
{ 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */
|
||||
{ DMASCH1, 0, SCUW, VIO60,
|
||||
VIO61, CEU21, 0, CSI21 } },
|
||||
{ 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */
|
||||
{ DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV,
|
||||
EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } },
|
||||
{ 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */
|
||||
{ MSTIF0_MST00I, MSTIF0_MST01I, 0, 0,
|
||||
0, 0, 0, 0 } },
|
||||
{ 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */
|
||||
{ SPUV, 0, 0, 0,
|
||||
0, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
/* Priority is needed for INTCA to receive the INTCS interrupt */
|
||||
static struct intc_prio_reg intcs_prio_registers[] = {
|
||||
{ 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } },
|
||||
{ 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
|
||||
{ 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
|
||||
{ 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2,
|
||||
0, 0 } },
|
||||
{ 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } },
|
||||
{ 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1,
|
||||
CMT2, CMT0 } },
|
||||
{ 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01,
|
||||
TMU0_TUNI02, TSIF1 } },
|
||||
{ 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } },
|
||||
{ 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } },
|
||||
{ 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } },
|
||||
{ 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } },
|
||||
{ 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } },
|
||||
{ 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } },
|
||||
{ 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } },
|
||||
{ 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } },
|
||||
{ 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } },
|
||||
{ 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } },
|
||||
{ 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } },
|
||||
{ 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } },
|
||||
{ 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } },
|
||||
{ 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } },
|
||||
{ 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } },
|
||||
{ 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11,
|
||||
DISP, DSRV } },
|
||||
{ 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I,
|
||||
MSTIF0_MST00I, MSTIF0_MST01I } },
|
||||
{ 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I,
|
||||
0, 0 } },
|
||||
{ 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static struct resource intcs_resources[] __initdata = {
|
||||
[0] = {
|
||||
.start = 0xffd20000,
|
||||
.end = 0xffd201ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0xffd50000,
|
||||
.end = 0xffd501ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[2] = {
|
||||
.start = 0xffd60000,
|
||||
.end = 0xffd601ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct intc_desc intcs_desc __initdata = {
|
||||
.name = "sh73a0-intcs",
|
||||
.resource = intcs_resources,
|
||||
.num_resources = ARRAY_SIZE(intcs_resources),
|
||||
.hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
|
||||
intcs_prio_registers, NULL, NULL),
|
||||
};
|
||||
|
||||
static struct irqaction sh73a0_intcs_cascade;
|
||||
|
||||
static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
|
||||
{
|
||||
unsigned int evtcodeas = ioread32((void __iomem *)dev_id);
|
||||
|
||||
generic_handle_irq(intcs_evt2irq(evtcodeas));
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
#define PINTER0_PHYS 0xe69000a0
|
||||
#define PINTER1_PHYS 0xe69000a4
|
||||
#define PINTER0_VIRT IOMEM(0xe69000a0)
|
||||
#define PINTER1_VIRT IOMEM(0xe69000a4)
|
||||
#define PINTRR0 IOMEM(0xe69000d0)
|
||||
#define PINTRR1 IOMEM(0xe69000d4)
|
||||
|
||||
#define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
|
||||
#define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
|
||||
#define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16))
|
||||
#define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
|
||||
#define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
|
||||
|
||||
INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0", \
|
||||
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
|
||||
INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \
|
||||
INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \
|
||||
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
|
||||
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
|
||||
|
||||
INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1", \
|
||||
INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
|
||||
INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \
|
||||
INTC_PINT_V_NONE, INTC_PINT_V_NONE, \
|
||||
INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \
|
||||
INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE);
|
||||
|
||||
static struct irqaction sh73a0_pint0_cascade;
|
||||
static struct irqaction sh73a0_pint1_cascade;
|
||||
|
||||
static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq)
|
||||
{
|
||||
unsigned long value = ioread32(rr) & ioread32(er);
|
||||
int k;
|
||||
|
||||
for (k = 0; k < 32; k++) {
|
||||
if (value & (1 << (31 - k))) {
|
||||
generic_handle_irq(base_irq + k);
|
||||
iowrite32(~(1 << (31 - k)), rr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
|
||||
{
|
||||
pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0));
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
|
||||
{
|
||||
pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0));
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
void __init sh73a0_init_irq(void)
|
||||
{
|
||||
void __iomem *gic_dist_base = IOMEM(0xf0001000);
|
||||
void __iomem *gic_cpu_base = IOMEM(0xf0000100);
|
||||
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
|
||||
|
||||
gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
|
||||
register_intc_controller(&intcs_desc);
|
||||
register_intc_controller(&intc_pint0_desc);
|
||||
register_intc_controller(&intc_pint1_desc);
|
||||
|
||||
/* demux using INTEVTSA */
|
||||
sh73a0_intcs_cascade.name = "INTCS cascade";
|
||||
sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
|
||||
sh73a0_intcs_cascade.dev_id = intevtsa;
|
||||
setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
|
||||
|
||||
/* PINT pins are sanely tied to the GIC as SPI */
|
||||
sh73a0_pint0_cascade.name = "PINT0 cascade";
|
||||
sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
|
||||
setup_irq(gic_spi(33), &sh73a0_pint0_cascade);
|
||||
|
||||
sh73a0_pint1_cascade.name = "PINT1 cascade";
|
||||
sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
|
||||
setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
|
||||
}
|
||||
Reference in New Issue
Block a user