From 42cd31fec4e5bfb5c96d386a065175d383241b1c Mon Sep 17 00:00:00 2001 From: Mecid Date: Wed, 19 Nov 2025 09:08:54 +0100 Subject: [PATCH] Rock5B-Plus and Rock5T: Use upstream u-boot (#8918) --- config/boards/rock-5b-plus.conf | 15 +- config/boards/rock-5t.conf | 39 +- .../0000-Prior-Upstream-DT-hacks.patch | 2871 +++++++++++++++++ .../0001-Add-Rock5T-dt-modifications.patch | 2176 +++++++++++++ .../0002-Add-Rock5T-dts-to-upstream-dir.patch | 124 + .../0003-Add-Rock5T-support.patch | 323 ++ .../0001-Set-NET_PREFER_ROM_MAC_ADDR.patch | 20 + .../0002-Add-ROCK-5BPlus-support.patch | 96 + 8 files changed, 5653 insertions(+), 11 deletions(-) create mode 100644 patch/u-boot/v2025.04/board_rock-5t/0000-Prior-Upstream-DT-hacks.patch create mode 100644 patch/u-boot/v2025.04/board_rock-5t/0001-Add-Rock5T-dt-modifications.patch create mode 100644 patch/u-boot/v2025.04/board_rock-5t/0002-Add-Rock5T-dts-to-upstream-dir.patch create mode 100644 patch/u-boot/v2025.04/board_rock-5t/0003-Add-Rock5T-support.patch create mode 100644 patch/u-boot/v2025.10/board_rock-5b-plus/0001-Set-NET_PREFER_ROM_MAC_ADDR.patch create mode 100644 patch/u-boot/v2025.10/board_rock-5b-plus/0002-Add-ROCK-5BPlus-support.patch diff --git a/config/boards/rock-5b-plus.conf b/config/boards/rock-5b-plus.conf index 8d328a82c..653d89c7a 100644 --- a/config/boards/rock-5b-plus.conf +++ b/config/boards/rock-5b-plus.conf @@ -27,18 +27,16 @@ function post_family_tweaks__rock5b_naming_audios() { return 0 } -# Mainline u-boot tree -# see rock-5b.conf and https://github.com/armbian/build/pull/7135 -function post_family_config_branch_edge__rock-5b_use_mainline_uboot() { - display_alert "$BOARD" "mainline (next branch) u-boot overrides for $BOARD / $BRANCH" "info" +# Mainline u-boot tree - use post_family_config hook to override family config +function post_family_config__rock5b_plus_use_mainline_uboot() { + display_alert "$BOARD" "Mainline U-Boot overrides for $BOARD - $BRANCH" "info" - # temporary override until DT in armbian/rockchip-linux is renamed declare -g BOOT_FDT_FILE="rockchip/rk3588-rock-5b-plus.dtb" declare -g BOOTCONFIG="rock5b-rk3588_defconfig" declare -g BOOTDELAY=1 declare -g BOOTSOURCE="https://github.com/u-boot/u-boot.git" - declare -g BOOTBRANCH="tag:v2025.04" - declare -g BOOTPATCHDIR="v2025.04" + declare -g BOOTBRANCH="tag:v2025.10" + declare -g BOOTPATCHDIR="v2025.10" declare -g BOOTDIR="u-boot-${BOARD}" declare -g UBOOT_TARGET_MAP="BL31=${RKBIN_DIR}/${BL31_BLOB} ROCKCHIP_TPL=${RKBIN_DIR}/${DDR_BLOB};;u-boot-rockchip.bin u-boot-rockchip-spi.bin" unset uboot_custom_postprocess write_uboot_platform write_uboot_platform_mtd # disable stuff from rockchip64_common; we're using binman here which does all the work already @@ -53,9 +51,8 @@ function post_family_config_branch_edge__rock-5b_use_mainline_uboot() { } } -function post_config_uboot_target__extra_configs_for_rock5b_mainline_environment_in_spi() { - [[ "${BRANCH}" != "edge" ]] && return 0 +function post_config_uboot_target__extra_configs_for_rock5b_mainline_environment_in_spi() { display_alert "$BOARD" "u-boot configs for ${BOOTBRANCH} u-boot config BRANCH=${BRANCH}" "info" run_host_command_logged scripts/config --set-val CONFIG_ENV_IS_NOWHERE "n" run_host_command_logged scripts/config --set-val CONFIG_ENV_IS_IN_SPI_FLASH "y" diff --git a/config/boards/rock-5t.conf b/config/boards/rock-5t.conf index 600aba21a..76c8345f8 100644 --- a/config/boards/rock-5t.conf +++ b/config/boards/rock-5t.conf @@ -15,7 +15,7 @@ IMAGE_PARTITION_TABLE="gpt" declare -g UEFI_EDK2_BOARD_ID="rock-5t" # This _only_ used for uefi-edk2-rk3588 extension function post_family_tweaks__rock5b_naming_audios() { - display_alert "$BOARD" "Renaming rock5b audios" "info" + display_alert "$BOARD" "Renaming rock5t audios" "info" mkdir -p $SDCARD/etc/udev/rules.d/ echo 'SUBSYSTEM=="sound", ENV{ID_PATH}=="platform-hdmi1-sound", ENV{SOUND_DESCRIPTION}="HDMI1 Audio"' >> $SDCARD/etc/udev/rules.d/90-naming-audios.rules @@ -25,4 +25,39 @@ function post_family_tweaks__rock5b_naming_audios() { echo 'SUBSYSTEM=="sound", ENV{ID_PATH}=="platform-es8316-sound", ENV{SOUND_DESCRIPTION}="ES8316 Audio"' >> $SDCARD/etc/udev/rules.d/90-naming-audios.rules return 0 -} \ No newline at end of file +} + +# Mainline u-boot tree - use post_family_config hook to override family config +function post_family_config__rock5t_use_mainline_uboot() { + display_alert "$BOARD" "Mainline U-Boot overrides for $BOARD - $BRANCH" "info" + + declare -g BOOT_FDT_FILE="rockchip/rk3588-rock-5t.dtb" + declare -g BOOTCONFIG="rock5t-rk3588_defconfig" + declare -g BOOTDELAY=1 + declare -g BOOTSOURCE="https://github.com/u-boot/u-boot.git" + declare -g BOOTBRANCH="tag:v2025.04" + declare -g BOOTPATCHDIR="v2025.04" + declare -g BOOTDIR="u-boot-${BOARD}" + declare -g UBOOT_TARGET_MAP="BL31=${RKBIN_DIR}/${BL31_BLOB} ROCKCHIP_TPL=${RKBIN_DIR}/${DDR_BLOB};;u-boot-rockchip.bin u-boot-rockchip-spi.bin" + unset uboot_custom_postprocess write_uboot_platform write_uboot_platform_mtd # disable stuff from rockchip64_common; we're using binman here which does all the work already + + # Just use the binman-provided u-boot-rockchip.bin, which is ready-to-go + function write_uboot_platform() { + dd "if=$1/u-boot-rockchip.bin" "of=$2" bs=32k seek=1 conv=notrunc status=none + } + + function write_uboot_platform_mtd() { + flashcp -v -p "$1/u-boot-rockchip-spi.bin" /dev/mtd0 + } +} + + +function post_config_uboot_target__extra_configs_for_rock5b_mainline_environment_in_spi() { + display_alert "$BOARD" "u-boot configs for ${BOOTBRANCH} u-boot config BRANCH=${BRANCH}" "info" + run_host_command_logged scripts/config --set-val CONFIG_ENV_IS_NOWHERE "n" + run_host_command_logged scripts/config --set-val CONFIG_ENV_IS_IN_SPI_FLASH "y" + run_host_command_logged scripts/config --set-val CONFIG_ENV_SECT_SIZE_AUTO "y" + run_host_command_logged scripts/config --set-val CONFIG_ENV_OVERWRITE "y" + run_host_command_logged scripts/config --set-val CONFIG_ENV_SIZE "0x20000" + run_host_command_logged scripts/config --set-val CONFIG_ENV_OFFSET "0xc00000" +} diff --git a/patch/u-boot/v2025.04/board_rock-5t/0000-Prior-Upstream-DT-hacks.patch b/patch/u-boot/v2025.04/board_rock-5t/0000-Prior-Upstream-DT-hacks.patch new file mode 100644 index 000000000..13f0a2939 --- /dev/null +++ b/patch/u-boot/v2025.04/board_rock-5t/0000-Prior-Upstream-DT-hacks.patch @@ -0,0 +1,2871 @@ +From a7dfe216ceb5718a6a02b7f0ac7cedbe33f8923d Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Wed, 2 Apr 2025 19:48:45 +0200 +Subject: [PATCH] [HACK] arm64: dts: rockchip: Copy recent DT for Rock 5B+ + +This is a simple copy of the latest RK3588 DT from upstream +Linux including the ROCK 5B+ devicetree, which I'm currently +working on. The goal is a combined U-Boot image, which works +on the ROCK 5B and the ROCK 5B+ and chooses the correct DT +file at runtime. + +Signed-off-by: Sebastian Reichel +--- + .../src/arm64/rockchip/rk3588-base.dtsi | 293 ++++- + .../src/arm64/rockchip/rk3588-extra.dtsi | 189 +++ + .../arm64/rockchip/rk3588-rock-5b-plus.dts | 113 ++ + .../src/arm64/rockchip/rk3588-rock-5b.dts | 875 +------------ + .../src/arm64/rockchip/rk3588-rock-5b.dtsi | 1088 +++++++++++++++++ + 5 files changed, 1671 insertions(+), 887 deletions(-) + create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts + create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi +index a337f3fb837..bb77d5987e7 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi +@@ -358,11 +358,6 @@ + }; + + firmware { +- optee: optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; +@@ -382,6 +377,22 @@ + }; + }; + ++ hdmi0_sound: hdmi0-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <128>; ++ simple-audio-card,name = "hdmi0"; ++ status = "disabled"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi0>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s5_8ch>; ++ }; ++ }; ++ + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; +@@ -549,22 +560,21 @@ + mmu600_pcie: iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfc900000 0x0 0x200000>; +- interrupts = , +- , +- , +- ; ++ interrupts = , ++ , ++ , ++ ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; +- status = "disabled"; + }; + + mmu600_php: iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfcb00000 0x0 0x200000>; +- interrupts = , +- , +- , +- ; ++ interrupts = , ++ , ++ , ++ ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; +@@ -580,6 +590,16 @@ + reg = <0x0 0xfd58c000 0x0 0x1000>; + }; + ++ mipidcphy0_grf: syscon@fd5e8000 { ++ compatible = "rockchip,rk3588-dcphy-grf", "syscon"; ++ reg = <0x0 0xfd5e8000 0x0 0x4000>; ++ }; ++ ++ mipidcphy1_grf: syscon@fd5ec000 { ++ compatible = "rockchip,rk3588-dcphy-grf", "syscon"; ++ reg = <0x0 0xfd5ec000 0x0 0x4000>; ++ }; ++ + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; +@@ -865,7 +885,7 @@ + }; + }; + /* These power domains are grouped by VD_GPU */ +- power-domain@RK3588_PD_GPU { ++ pd_gpu: power-domain@RK3588_PD_GPU { + reg = ; + clocks = <&cru CLK_GPU>, + <&cru CLK_GPU_COREGROUP>, +@@ -1238,6 +1258,44 @@ + #iommu-cells = <0>; + }; + ++ vdec0: video-decoder@fdc38000 { ++ compatible = "rockchip,rk3588-vdec"; ++ reg = <0x0 0xfdc38000 0x0 0x100>, <0x0 0xfdc38100 0x0 0x500>, <0x0 0xfdc38600 0x0 0x100>; ++ reg-names = "link", "function", "cache"; ++ interrupts = ; ++ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, ++ <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; ++ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, ++ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; ++ assigned-clock-rates = <800000000>, <600000000>, ++ <600000000>, <1000000000>; ++ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, ++ <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; ++ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ power-domains = <&power RK3588_PD_RKVDEC0>; ++ sram = <&vdec0_sram>; ++ }; ++ ++ vdec1: video-decoder@fdc40000 { ++ compatible = "rockchip,rk3588-vdec"; ++ reg = <0x0 0xfdc40000 0x0 0x100>, <0x0 0xfdc40100 0x0 0x500>, <0x0 0xfdc40600 0x0 0x100>; ++ reg-names = "link", "function", "cache"; ++ interrupts = ; ++ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, ++ <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; ++ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, ++ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; ++ assigned-clock-rates = <800000000>, <600000000>, ++ <600000000>, <1000000000>; ++ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, ++ <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; ++ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ power-domains = <&power RK3588_PD_RKVDEC1>; ++ sram = <&vdec1_sram>; ++ }; ++ + av1d: video-codec@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; +@@ -1262,16 +1320,30 @@ + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, +- <&cru PCLK_VOP_ROOT>; ++ <&cru PCLK_VOP_ROOT>, ++ <&hdptxphy0>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", +- "pclk_vop"; ++ "pclk_vop", ++ "pll_hdmiphy0"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; ++ resets = <&cru SRST_A_VOP>, ++ <&cru SRST_H_VOP>, ++ <&cru SRST_D_VOP0>, ++ <&cru SRST_D_VOP1>, ++ <&cru SRST_D_VOP2>, ++ <&cru SRST_D_VOP3>; ++ reset-names = "aclk", ++ "hclk", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2", ++ "dclk_vp3"; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; +@@ -1319,6 +1391,21 @@ + status = "disabled"; + }; + ++ spdif_tx2: spdif-tx@fddb0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfddb0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; ++ dma-names = "tx"; ++ dmas = <&dmac1 6>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO0>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; +@@ -1336,6 +1423,21 @@ + status = "disabled"; + }; + ++ spdif_tx3: spdif-tx@fdde0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfdde0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF3_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; ++ dma-names = "tx"; ++ dmas = <&dmac1 7>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO1>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; +@@ -1370,6 +1472,62 @@ + status = "disabled"; + }; + ++ dsi0: dsi@fde20000 { ++ compatible = "rockchip,rk3588-mipi-dsi2"; ++ reg = <0x0 0xfde20000 0x0 0x10000>; ++ interrupts = ; ++ clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; ++ clock-names = "pclk", "sys"; ++ resets = <&cru SRST_P_DSIHOST0>; ++ reset-names = "apb"; ++ power-domains = <&power RK3588_PD_VOP>; ++ phys = <&mipidcphy0>; ++ phy-names = "dcphy"; ++ rockchip,grf = <&vop_grf>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dsi0_in: port@0 { ++ reg = <0>; ++ }; ++ ++ dsi0_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ ++ dsi1: dsi@fde30000 { ++ compatible = "rockchip,rk3588-mipi-dsi2"; ++ reg = <0x0 0xfde30000 0x0 0x10000>; ++ interrupts = ; ++ clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>; ++ clock-names = "pclk", "sys"; ++ resets = <&cru SRST_P_DSIHOST1>; ++ reset-names = "apb"; ++ power-domains = <&power RK3588_PD_VOP>; ++ phys = <&mipidcphy1>; ++ phy-names = "dcphy"; ++ rockchip,grf = <&vop_grf>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dsi1_in: port@0 { ++ reg = <0>; ++ }; ++ ++ dsi1_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ + hdmi0: hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi-qp"; + reg = <0x0 0xfde80000 0x0 0x20000>; +@@ -1386,7 +1544,7 @@ + , + ; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; +- phys = <&hdptxphy_hdmi0>; ++ phys = <&hdptxphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda>; +@@ -1395,6 +1553,7 @@ + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; ++ #sound-dai-cells = <0>; + status = "disabled"; + + ports { +@@ -1686,6 +1845,7 @@ + linux,pci-domain = <3>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; ++ iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; +@@ -1737,6 +1897,7 @@ + linux,pci-domain = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; ++ iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; +@@ -1920,6 +2081,14 @@ + status = "disabled"; + }; + ++ rng@fe378000 { ++ compatible = "rockchip,rk3588-rng"; ++ reg = <0x0 0xfe378000 0x0 0x200>; ++ interrupts = ; ++ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; ++ resets = <&scmi_reset 48>; ++ }; ++ + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; +@@ -2015,12 +2184,47 @@ + status = "disabled"; + }; + ++ spdif_tx0: spdif-tx@fe4e0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfe4e0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF0_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; ++ dma-names = "tx"; ++ dmas = <&dmac0 5>; ++ interrupts = ; ++ pinctrl-0 = <&spdif0m0_tx>; ++ pinctrl-names = "default"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spdif_tx1: spdif-tx@fe4f0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfe4f0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF1_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; ++ dma-names = "tx"; ++ dmas = <&dmac1 5>; ++ interrupts = ; ++ pinctrl-0 = <&spdif1m0_tx>; ++ pinctrl-names = "default"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts = ; + interrupt-controller; ++ dma-noncoherent; + mbi-alias = <0x0 0xfe610000>; + mbi-ranges = <424 56>; + msi-controller; +@@ -2032,6 +2236,7 @@ + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; ++ dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; +@@ -2039,6 +2244,7 @@ + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; ++ dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; +@@ -2667,9 +2873,9 @@ + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ +- pinctrl-0 = <&tsadc_gpio_func>; +- pinctrl-1 = <&tsadc_shut>; +- pinctrl-names = "gpio", "otpout"; ++ pinctrl-0 = <&tsadc_shut_org>; ++ pinctrl-1 = <&tsadc_gpio_func>; ++ pinctrl-names = "default", "sleep"; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; +@@ -2806,11 +3012,12 @@ + #dma-cells = <1>; + }; + +- hdptxphy_hdmi0: phy@fed60000 { ++ hdptxphy0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; ++ #clock-cells = <0>; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, +@@ -2844,6 +3051,38 @@ + status = "disabled"; + }; + ++ mipidcphy0: phy@feda0000 { ++ compatible = "rockchip,rk3588-mipi-dcphy"; ++ reg = <0x0 0xfeda0000 0x0 0x10000>; ++ rockchip,grf = <&mipidcphy0_grf>; ++ clocks = <&cru PCLK_MIPI_DCPHY0>, ++ <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; ++ clock-names = "pclk", "ref"; ++ resets = <&cru SRST_M_MIPI_DCPHY0>, ++ <&cru SRST_P_MIPI_DCPHY0>, ++ <&cru SRST_P_MIPI_DCPHY0_GRF>, ++ <&cru SRST_S_MIPI_DCPHY0>; ++ reset-names = "m_phy", "apb", "grf", "s_phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ mipidcphy1: phy@fedb0000 { ++ compatible = "rockchip,rk3588-mipi-dcphy"; ++ reg = <0x0 0xfedb0000 0x0 0x10000>; ++ rockchip,grf = <&mipidcphy1_grf>; ++ clocks = <&cru PCLK_MIPI_DCPHY1>, ++ <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; ++ clock-names = "pclk", "ref"; ++ resets = <&cru SRST_M_MIPI_DCPHY1>, ++ <&cru SRST_P_MIPI_DCPHY1>, ++ <&cru SRST_P_MIPI_DCPHY1_GRF>, ++ <&cru SRST_S_MIPI_DCPHY1>; ++ reset-names = "m_phy", "apb", "grf", "s_phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; +@@ -2882,6 +3121,16 @@ + ranges = <0x0 0x0 0xff001000 0xef000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ vdec0_sram: codec-sram@0 { ++ reg = <0x0 0x78000>; ++ pool; ++ }; ++ ++ vdec1_sram: codec-sram@78000 { ++ reg = <0x78000 0x77000>; ++ pool; ++ }; + }; + + pinctrl: pinctrl { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi +index 0ce0934ec6b..099edb3fd0f 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi +@@ -7,6 +7,46 @@ + #include "rk3588-extra-pinctrl.dtsi" + + / { ++ hdmi1_sound: hdmi1-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <128>; ++ simple-audio-card,name = "hdmi1"; ++ status = "disabled"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi1>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s6_8ch>; ++ }; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* ++ * The 4k HDMI capture controller works only with 32bit ++ * phys addresses and doesn't support IOMMU. HDMI RX CMA ++ * must be reserved below 4GB. ++ * The size of 160MB was determined as follows: ++ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB ++ * To ensure sufficient support for practical use-cases, ++ * we doubled the 66MB value. ++ */ ++ hdmi_receiver_cma: hdmi-receiver-cma { ++ compatible = "shared-dma-pool"; ++ alloc-ranges = <0x0 0x0 0x0 0xffffffff>; ++ size = <0x0 (160 * 0x100000)>; /* 160MiB */ ++ alignment = <0x0 0x40000>; /* 64K */ ++ no-map; ++ status = "disabled"; ++ }; ++ }; ++ + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; +@@ -67,6 +107,26 @@ + }; + }; + ++ hdptxphy1_grf: syscon@fd5e4000 { ++ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; ++ reg = <0x0 0xfd5e4000 0x0 0x100>; ++ }; ++ ++ spdif_tx5: spdif-tx@fddb8000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfddb8000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; ++ dma-names = "tx"; ++ dmas = <&dmac1 22>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO0>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; +@@ -84,6 +144,21 @@ + status = "disabled"; + }; + ++ spdif_tx4: spdif-tx@fdde8000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfdde8000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF4_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; ++ dma-names = "tx"; ++ dmas = <&dmac1 8>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO1>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; +@@ -135,6 +210,79 @@ + status = "disabled"; + }; + ++ hdmi1: hdmi@fdea0000 { ++ compatible = "rockchip,rk3588-dw-hdmi-qp"; ++ reg = <0x0 0xfdea0000 0x0 0x20000>; ++ clocks = <&cru PCLK_HDMITX1>, ++ <&cru CLK_HDMITX1_EARC>, ++ <&cru CLK_HDMITX1_REF>, ++ <&cru MCLK_I2S6_8CH_TX>, ++ <&cru CLK_HDMIHDP1>, ++ <&cru HCLK_VO1>; ++ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "avp", "cec", "earc", "main", "hpd"; ++ phys = <&hdptxphy1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; ++ reset-names = "ref", "hdp"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vo-grf = <&vo1_grf>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi1_in: port@0 { ++ reg = <0>; ++ }; ++ ++ hdmi1_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ ++ hdmi_receiver: hdmi_receiver@fdee0000 { ++ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; ++ reg = <0x0 0xfdee0000 0x0 0x6000>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "cec", "hdmi", "dma"; ++ clocks = <&cru ACLK_HDMIRX>, ++ <&cru CLK_HDMIRX_AUD>, ++ <&cru CLK_CR_PARA>, ++ <&cru PCLK_HDMIRX>, ++ <&cru CLK_HDMIRX_REF>, ++ <&cru PCLK_S_HDMIRX>, ++ <&cru HCLK_VO1>; ++ clock-names = "aclk", ++ "audio", ++ "cr_para", ++ "pclk", ++ "ref", ++ "hclk_s_hdmirx", ++ "hclk_vo1"; ++ memory-region = <&hdmi_receiver_cma>; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, ++ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; ++ reset-names = "axi", "apb", "ref", "biu"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vo1-grf = <&vo1_grf>; ++ status = "disabled"; ++ }; ++ + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; +@@ -162,6 +310,7 @@ + linux,pci-domain = <0>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; ++ iommu-map = <0x0000 &mmu600_pcie 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; +@@ -248,6 +397,7 @@ + linux,pci-domain = <1>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; ++ iommu-map = <0x1000 &mmu600_pcie 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; +@@ -297,6 +447,7 @@ + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; ++ iommu-map = <0x2000 &mmu600_pcie 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; +@@ -395,6 +546,23 @@ + }; + }; + ++ hdptxphy1: phy@fed70000 { ++ compatible = "rockchip,rk3588-hdptx-phy"; ++ reg = <0x0 0xfed70000 0x0 0x2000>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; ++ clock-names = "ref", "apb"; ++ #clock-cells = <0>; ++ #phy-cells = <0>; ++ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, ++ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, ++ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, ++ <&cru SRST_HDPTX1_LCPLL>; ++ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", ++ "lcpll"; ++ rockchip,grf = <&hdptxphy1_grf>; ++ status = "disabled"; ++ }; ++ + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; +@@ -446,3 +614,24 @@ + status = "disabled"; + }; + }; ++ ++&vop { ++ clocks = <&cru ACLK_VOP>, ++ <&cru HCLK_VOP>, ++ <&cru DCLK_VOP0>, ++ <&cru DCLK_VOP1>, ++ <&cru DCLK_VOP2>, ++ <&cru DCLK_VOP3>, ++ <&cru PCLK_VOP_ROOT>, ++ <&hdptxphy0>, ++ <&hdptxphy1>; ++ clock-names = "aclk", ++ "hclk", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2", ++ "dclk_vp3", ++ "pclk_vop", ++ "pll_hdmiphy0", ++ "pll_hdmiphy1"; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts +new file mode 100644 +index 00000000000..74c7b6502e4 +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts +@@ -0,0 +1,113 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3588-rock-5b.dtsi" ++ ++/ { ++ model = "Radxa ROCK 5B+"; ++ compatible = "radxa,rock-5b-plus", "rockchip,rk3588"; ++ ++ rfkill-wwan { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-wwan"; ++ radio-type = "wwan"; ++ shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vcc3v3_4g: regulator-vcc3v3-4g { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ /* pinctrl for the GPIO is requested by vcc3v3_pcie2x1l0 */ ++ regulator-name = "vcc3v3_4g"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_wwan_pwr: regulator-vcc3v3-wwan { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wwan_power_en>; ++ regulator-name = "vcc3v3_wwan_pwr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_4g>; ++ }; ++}; ++ ++&gpio0 { ++ wwan-disable2-n-hog { ++ gpios = ; ++ output-low; ++ line-name = "M.2 B-key W_DISABLE2#"; ++ gpio-hog; ++ }; ++}; ++ ++&gpio2 { ++ wwan-reset-n-hog { ++ gpios = ; ++ output-low; ++ line-name = "M.2 B-key RESET#"; ++ gpio-hog; ++ }; ++ ++ wwan-wake-n-hog { ++ gpios = ; ++ input; ++ line-name = "M.2 B-key WoWWAN#"; ++ gpio-hog; ++ }; ++}; ++ ++&pcie30phy { ++ data-lanes = <1 1 2 2>; ++}; ++ ++&pcie3x2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3x2_rst>; ++ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ num-lanes = <2>; ++}; ++ ++&pinctrl { ++ wwan { ++ wwan_power_en: wwan-pwr-en { ++ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie3 { ++ pcie3x2_rst: pcie3x2-rst { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&vcc5v0_host { ++ enable-active-high; ++ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts +index d597112f1d5..9407a7c9910 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts +@@ -2,462 +2,11 @@ + + /dts-v1/; + +-#include +-#include +-#include +-#include "rk3588.dtsi" ++#include "rk3588-rock-5b.dtsi" + + / { + model = "Radxa ROCK 5B"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; +- +- aliases { +- mmc0 = &sdhci; +- mmc1 = &sdmmc; +- mmc2 = &sdio; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- +- analog-sound { +- compatible = "audio-graph-card"; +- label = "rk3588-es8316"; +- +- widgets = "Microphone", "Mic Jack", +- "Headphone", "Headphones"; +- +- routing = "MIC2", "Mic Jack", +- "Headphones", "HPOL", +- "Headphones", "HPOR"; +- +- dais = <&i2s0_8ch_p0>; +- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&hp_detect>; +- }; +- +- hdmi0-con { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi0_con_in: endpoint { +- remote-endpoint = <&hdmi0_out_con>; +- }; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&led_rgb_b>; +- +- led_rgb_b { +- function = LED_FUNCTION_STATUS; +- color = ; +- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; +- }; +- }; +- +- fan: pwm-fan { +- compatible = "pwm-fan"; +- cooling-levels = <0 120 150 180 210 240 255>; +- fan-supply = <&vcc5v0_sys>; +- pwms = <&pwm1 0 50000 0>; +- #cooling-cells = <2>; +- }; +- +- rfkill { +- compatible = "rfkill-gpio"; +- label = "rfkill-m2-wlan"; +- radio-type = "wlan"; +- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; +- }; +- +- rfkill-bt { +- compatible = "rfkill-gpio"; +- label = "rfkill-m2-bt"; +- radio-type = "bluetooth"; +- shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +- }; +- +- vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_0_vcc3v3_en>; +- regulator-name = "vcc3v3_pcie2x1l0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <50000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_pcie2x1l2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <5000>; +- vin-supply = <&vcc_3v3_s3>; +- }; +- +- vcc3v3_pcie30: regulator-vcc3v3-pcie30 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_vcc3v3_en>; +- regulator-name = "vcc3v3_pcie30"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <5000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_host: regulator-vcc5v0-host { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_host"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- enable-active-high; +- gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_sys: regulator-vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_1v1_nldo_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&combphy0_ps { +- status = "okay"; +-}; +- +-&combphy1_ps { +- status = "okay"; +-}; +- +-&combphy2_psu { +- status = "okay"; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_big0_s0>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_big0_s0>; +-}; +- +-&cpu_b2 { +- cpu-supply = <&vdd_cpu_big1_s0>; +-}; +- +-&cpu_b3 { +- cpu-supply = <&vdd_cpu_big1_s0>; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu_s0>; +- status = "okay"; +-}; +- +-&hdmi0 { +- status = "okay"; +-}; +- +-&hdmi0_in { +- hdmi0_in_vp0: endpoint { +- remote-endpoint = <&vp0_out_hdmi0>; +- }; +-}; +- +-&hdmi0_out { +- hdmi0_out_con: endpoint { +- remote-endpoint = <&hdmi0_con_in>; +- }; +-}; +- +-&hdptxphy_hdmi0 { +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0m2_xfer>; +- status = "okay"; +- +- vdd_cpu_big0_s0: regulator@42 { +- compatible = "rockchip,rk8602"; +- reg = <0x42>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_big0_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <1050000>; +- regulator-ramp-delay = <2300>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_big1_s0: regulator@43 { +- compatible = "rockchip,rk8603", "rockchip,rk8602"; +- reg = <0x43>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_big1_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <1050000>; +- regulator-ramp-delay = <2300>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- +- hym8563: rtc@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-output-names = "hym8563"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hym8563_int>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- wakeup-source; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- es8316: audio-codec@11 { +- compatible = "everest,es8316"; +- reg = <0x11>; +- clocks = <&cru I2S0_8CH_MCLKOUT>; +- clock-names = "mclk"; +- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +- assigned-clock-rates = <12288000>; +- #sound-dai-cells = <0>; +- +- port { +- es8316_p0_0: endpoint { +- remote-endpoint = <&i2s0_8ch_p0_0>; +- }; +- }; +- }; +-}; +- +-&i2s0_8ch { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_lrck +- &i2s0_mclk +- &i2s0_sclk +- &i2s0_sdi0 +- &i2s0_sdo0>; +- status = "okay"; +- +- i2s0_8ch_p0: port { +- i2s0_8ch_p0_0: endpoint { +- dai-format = "i2s"; +- mclk-fs = <256>; +- remote-endpoint = <&es8316_p0_0>; +- }; +- }; +-}; +- +-&package_thermal { +- polling-delay = <1000>; +- +- trips { +- package_fan0: package-fan0 { +- temperature = <55000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- package_fan1: package-fan1 { +- temperature = <65000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&package_fan0>; +- cooling-device = <&fan THERMAL_NO_LIMIT 1>; +- }; +- +- map1 { +- trip = <&package_fan1>; +- cooling-device = <&fan 2 THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&pcie2x1l0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_0_rst>; +- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; +- status = "okay"; +-}; +- +-&pcie2x1l2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_2_rst>; +- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; +- status = "okay"; +-}; +- +-&pcie30phy { +- status = "okay"; +-}; +- +-&pcie3x4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_rst>; +- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie30>; +- status = "okay"; +-}; +- +-&pinctrl { +- hym8563 { +- hym8563_int: hym8563-int { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- leds { +- led_rgb_b: led-rgb-b { +- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- sound { +- hp_detect: hp-detect { +- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pcie2 { +- pcie2_0_rst: pcie2-0-rst { +- rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie2_0_vcc3v3_en: pcie2-0-vcc-en { +- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie2_2_rst: pcie2-2-rst { +- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- pcie3 { +- pcie3_rst: pcie3-rst { +- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie3_vcc3v3_en: pcie3-vcc3v3-en { +- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb { +- vcc5v0_host_en: vcc5v0-host-en { +- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&avcc_1v8_s0>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- no-sdio; +- no-sd; +- non-removable; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- status = "okay"; +-}; +- +-&sdmmc { +- max-frequency = <200000000>; +- no-sdio; +- no-mmc; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; +- disable-wp; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc_3v3_s3>; +- vqmmc-supply = <&vccio_sd_s0>; +- status = "okay"; + }; + + &sdio { +@@ -481,427 +30,23 @@ + status = "okay"; + }; + +-&sfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&fspim2_pins>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- }; +-}; +- + &uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + status = "okay"; + }; + +-&spi2 { +- status = "okay"; +- assigned-clocks = <&cru CLK_SPI2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; +- num-cs = <1>; +- +- pmic@0 { +- compatible = "rockchip,rk806"; +- spi-max-frequency = <1000000>; +- reg = <0x0>; +- +- interrupt-parent = <&gpio0>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, +- <&rk806_dvs2_null>, <&rk806_dvs3_null>; +- +- system-power-controller; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc5-supply = <&vcc5v0_sys>; +- vcc6-supply = <&vcc5v0_sys>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc5v0_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- vcc10-supply = <&vcc5v0_sys>; +- vcc11-supply = <&vcc_2v0_pldo_s3>; +- vcc12-supply = <&vcc5v0_sys>; +- vcc13-supply = <&vcc_1v1_nldo_s3>; +- vcc14-supply = <&vcc_1v1_nldo_s3>; +- vcca-supply = <&vcc5v0_sys>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- rk806_dvs1_null: dvs1-null-pins { +- pins = "gpio_pwrctrl1"; +- function = "pin_fun0"; +- }; +- +- rk806_dvs2_null: dvs2-null-pins { +- pins = "gpio_pwrctrl2"; +- function = "pin_fun0"; +- }; +- +- rk806_dvs3_null: dvs3-null-pins { +- pins = "gpio_pwrctrl3"; +- function = "pin_fun0"; +- }; +- +- regulators { +- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_gpu_s0"; +- regulator-enable-ramp-delay = <400>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_cpu_lit_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_log_s0: dcdc-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <750000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_log_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <750000>; +- }; +- }; +- +- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_vdenc_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_ddr_s0: dcdc-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <900000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_ddr_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <850000>; +- }; +- }; +- +- vdd2_ddr_s3: dcdc-reg6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vdd2_ddr_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_2v0_pldo_s3: dcdc-reg7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_2v0_pldo_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <2000000>; +- }; +- }; +- +- vcc_3v3_s3: dcdc-reg8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_3v3_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vddq_ddr_s0: dcdc-reg9 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vddq_ddr_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v8_s3: dcdc-reg10 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_1v8_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- avcc_1v8_s0: pldo-reg1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "avcc_1v8_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v8_s0: pldo-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_1v8_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- avdd_1v2_s0: pldo-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "avdd_1v2_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v3_s0: pldo-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vcc_3v3_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vccio_sd_s0: pldo-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vccio_sd_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- pldo6_s3: pldo-reg6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "pldo6_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_0v75_s3: nldo-reg1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "vdd_0v75_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <750000>; +- }; +- }; +- +- vdd_ddr_pll_s0: nldo-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-name = "vdd_ddr_pll_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <850000>; +- }; +- }; +- +- avdd_0v75_s0: nldo-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "avdd_0v75_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_0v85_s0: nldo-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-name = "vdd_0v85_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_0v75_s0: nldo-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "vdd_0v75_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; ++&pinctrl { ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + +-&tsadc { +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-0 = <&uart2m0_xfer>; +- status = "okay"; +-}; +- +-&u2phy1 { +- status = "okay"; +-}; +- +-&u2phy1_otg { +- status = "okay"; +-}; +- +-&u2phy2 { +- status = "okay"; +-}; +- +-&u2phy2_host { +- /* connected to USB hub, which is powered by vcc5v0_sys */ +- phy-supply = <&vcc5v0_sys>; +- status = "okay"; +-}; +- +-&u2phy3 { +- status = "okay"; +-}; +- +-&u2phy3_host { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +-}; +- +-&usbdp_phy1 { +- status = "okay"; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usb_host1_xhci { +- dr_mode = "host"; +- status = "okay"; +-}; +- +-&usb_host2_xhci { +- status = "okay"; +-}; +- +-&vop_mmu { +- status = "okay"; +-}; +- +-&vop { +- status = "okay"; +-}; +- +-&vp0 { +- vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { +- reg = ; +- remote-endpoint = <&hdmi0_in_vp0>; +- }; ++&vcc5v0_host { ++ enable-active-high; ++ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi +new file mode 100644 +index 00000000000..4bdc16ea36a +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi +@@ -0,0 +1,1088 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include "rk3588.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ mmc2 = &sdio; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ analog-sound { ++ compatible = "audio-graph-card"; ++ label = "rk3588-es8316"; ++ ++ widgets = "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ ++ routing = "MIC2", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR"; ++ ++ dais = <&i2s0_8ch_p0>; ++ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_detect>; ++ }; ++ ++ hdmi0-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi0_con_in: endpoint { ++ remote-endpoint = <&hdmi0_out_con>; ++ }; ++ }; ++ }; ++ ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_rgb_b>; ++ ++ led_rgb_b { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ cooling-levels = <0 120 150 180 210 240 255>; ++ fan-supply = <&vcc5v0_sys>; ++ pwms = <&pwm1 0 50000 0>; ++ #cooling-cells = <2>; ++ }; ++ ++ rfkill { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-wlan"; ++ radio-type = "wlan"; ++ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ rfkill-bt { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-bt"; ++ radio-type = "bluetooth"; ++ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ ++ vbus5v0_typec: vbus5v0-typec { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vbus5v0_typec_en>; ++ regulator-name = "vbus5v0_typec"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc12v_dcin: regulator-vcc12v-dcin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_vcc3v3_en>; ++ regulator-name = "vcc3v3_pcie2x1l0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie2x1l2"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc3v3_pcie30: regulator-vcc3v3-pcie30 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_vcc3v3_en>; ++ regulator-name = "vcc3v3_pcie30"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_host: regulator-vcc5v0-host { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_host"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: regulator-vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++ ++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy1_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdmi0_out { ++ hdmi0_out_con: endpoint { ++ remote-endpoint = <&hdmi0_con_in>; ++ }; ++}; ++ ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdmi1 { ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdmi1_sound { ++ status = "okay"; ++}; ++ ++&hdmi_receiver_cma { ++ status = "okay"; ++}; ++ ++&hdmi_receiver { ++ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c3 { ++ status = "okay"; ++}; ++ ++&i2c4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4m1_xfer>; ++ status = "okay"; ++ ++ usbc0: usb-typec@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio3>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usbc0_int>; ++ vbus-supply = <&vcc12v_dcin>; ++ /* ++ * When the board is starting to send power-delivery messages ++ * too late (5 seconds according to the specification), the ++ * power-supply reacts with a hard-reset. That removes the ++ * power from VBUS for some time, which resets te whole board. ++ */ ++ status = "fail"; ++ ++ usb_con: connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ data-role = "dual"; ++ power-role = "sink"; ++ try-power-role = "sink"; ++ op-sink-microwatt = <1000000>; ++ sink-pdos = ++ , ++ ; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usbc0_role_sw: endpoint { ++ remote-endpoint = <&dwc3_0_role_switch>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ usbc0_orien_sw: endpoint { ++ remote-endpoint = <&usbdp_phy0_orientation_switch>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ dp_altmode_mux: endpoint { ++ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ wakeup-source; ++ }; ++}; ++ ++&i2c7 { ++ status = "okay"; ++ ++ es8316: audio-codec@11 { ++ compatible = "everest,es8316"; ++ reg = <0x11>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ clock-names = "mclk"; ++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clock-rates = <12288000>; ++ #sound-dai-cells = <0>; ++ ++ port { ++ es8316_p0_0: endpoint { ++ remote-endpoint = <&i2s0_8ch_p0_0>; ++ }; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_mclk ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdo0>; ++ status = "okay"; ++ ++ i2s0_8ch_p0: port { ++ i2s0_8ch_p0_0: endpoint { ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ remote-endpoint = <&es8316_p0_0>; ++ }; ++ }; ++}; ++ ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ ++&package_thermal { ++ polling-delay = <1000>; ++ ++ trips { ++ package_fan0: package-fan0 { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ package_fan1: package-fan1 { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&package_fan0>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map1 { ++ trip = <&package_fan1>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ ++&pcie2x1l0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_rst>; ++ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; ++ status = "okay"; ++}; ++ ++&pcie2x1l2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_2_rst>; ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_rst>; ++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ ++&pinctrl { ++ hdmirx { ++ hdmirx_hpd: hdmirx-5v-detection { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led_rgb_b: led-rgb-b { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sound { ++ hp_detect: hp-detect { ++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie2 { ++ pcie2_0_rst: pcie2-0-rst { ++ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2_2_rst: pcie2-2-rst { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie3 { ++ pcie3_rst: pcie3-rst { ++ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie3_vcc3v3_en: pcie3-vcc3v3-en { ++ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ usbc0_int: usbc0-int { ++ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vbus5v0_typec_en: vbus5v0-typec-en { ++ rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ max-frequency = <150000000>; ++ mmc-hs200-1_8v; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ max-frequency = <200000000>; ++ no-sdio; ++ no-mmc; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_s3>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&sfc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fspim2_pins>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <104000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ ++&spi2 { ++ status = "okay"; ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ num-cs = <1>; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ spi-max-frequency = <1000000>; ++ reg = <0x0>; ++ ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ ++ system-power-controller; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc5v0_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc5v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc5v0_sys>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vccio_sd_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ /* connected to USB hub, which is powered by vcc5v0_sys */ ++ phy-supply = <&vcc5v0_sys>; ++ status = "okay"; ++}; ++ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usbdp_phy1 { ++ status = "okay"; ++}; ++ ++&usbdp_phy0 { ++ mode-switch; ++ orientation-switch; ++ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; ++ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usbdp_phy0_orientation_switch: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_orien_sw>; ++ }; ++ ++ usbdp_phy0_dp_altmode_mux: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&dp_altmode_mux>; ++ }; ++ }; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dwc3_0_role_switch: endpoint { ++ remote-endpoint = <&usbc0_role_sw>; ++ }; ++ }; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host2_xhci { ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +-- +GitLab diff --git a/patch/u-boot/v2025.04/board_rock-5t/0001-Add-Rock5T-dt-modifications.patch b/patch/u-boot/v2025.04/board_rock-5t/0001-Add-Rock5T-dt-modifications.patch new file mode 100644 index 000000000..580c18c9b --- /dev/null +++ b/patch/u-boot/v2025.04/board_rock-5t/0001-Add-Rock5T-dt-modifications.patch @@ -0,0 +1,2176 @@ +From ffa17de2c8f161181e22d42930aacaa8fbc490e0 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Fri, 9 May 2025 11:34:30 +0200 +Subject: [PATCH] [HACK] add upstream DTS modifications for ROCK 5T + +Signed-off-by: Nicolas Frattaroli +--- + .../arm64/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 1012 ++++++++++++++++ + .../arm64/rockchip/rk3588-rock-5b-plus.dts | 16 + + .../src/arm64/rockchip/rk3588-rock-5b.dts | 12 + + .../src/arm64/rockchip/rk3588-rock-5b.dtsi | 1018 +---------------- + 4 files changed, 1048 insertions(+), 1010 deletions(-) + create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-rock-5b-5bp-5t.dtsi + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-5bp-5t.dtsi +new file mode 100644 +index 00000000000..f086f0ff9f6 +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-5bp-5t.dtsi +@@ -0,0 +1,1012 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include "rk3588.dtsi" ++ ++/ { ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ mmc2 = &sdio; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi0-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi0_con_in: endpoint { ++ remote-endpoint = <&hdmi0_out_con>; ++ }; ++ }; ++ }; ++ ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ cooling-levels = <0 120 150 180 210 240 255>; ++ fan-supply = <&vcc5v0_sys>; ++ pwms = <&pwm1 0 50000 0>; ++ #cooling-cells = <2>; ++ }; ++ ++ rfkill-bt { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-bt"; ++ radio-type = "bluetooth"; ++ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vcc12v_dcin: regulator-vcc12v-dcin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ regulator-name = "vcc3v3_pcie2x1l0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc5v0_sys>; ++ status = "disabled"; ++ }; ++ ++ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie2x1l2"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc3v3_pcie30: regulator-vcc3v3-pcie30 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_vcc3v3_en>; ++ regulator-name = "vcc3v3_pcie30"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_host: regulator-vcc5v0-host { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_host"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: regulator-vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++ ++ vbus5v0_typec: vbus5v0-typec { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vbus5v0_typec_en>; ++ regulator-name = "vbus5v0_typec"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy1_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdmi0_out { ++ hdmi0_out_con: endpoint { ++ remote-endpoint = <&hdmi0_con_in>; ++ }; ++}; ++ ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdmi1 { ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdmi1_sound { ++ status = "okay"; ++}; ++ ++&hdmi_receiver_cma { ++ status = "okay"; ++}; ++ ++&hdmi_receiver { ++ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; ++ pinctrl-names = "default"; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4m1_xfer>; ++ status = "okay"; ++ ++ usbc0: usb-typec@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio3>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usbc0_int>; ++ vbus-supply = <&vbus5v0_typec>; ++ /* ++ * When the board is starting to send power-delivery messages ++ * too late (5 seconds according to the specification), the ++ * power-supply reacts with a hard-reset. That removes the ++ * power from VBUS for some time, which resets te whole board. ++ */ ++ status = "fail"; ++ ++ usb_con: connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ data-role = "dual"; ++ power-role = "sink"; ++ try-power-role = "sink"; ++ op-sink-microwatt = <1000000>; ++ sink-pdos = ++ , ++ ; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usbc0_role_sw: endpoint { ++ remote-endpoint = <&dwc3_0_role_switch>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ usbc0_orien_sw: endpoint { ++ remote-endpoint = <&usbdp_phy0_orientation_switch>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ dp_altmode_mux: endpoint { ++ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ wakeup-source; ++ }; ++}; ++ ++&i2c7 { ++ status = "okay"; ++ ++ es8316: audio-codec@11 { ++ compatible = "everest,es8316"; ++ reg = <0x11>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ clock-names = "mclk"; ++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clock-rates = <12288000>; ++ #sound-dai-cells = <0>; ++ ++ port { ++ es8316_p0_0: endpoint { ++ remote-endpoint = <&i2s0_8ch_p0_0>; ++ }; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_mclk ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdo0>; ++ status = "okay"; ++ ++ i2s0_8ch_p0: port { ++ i2s0_8ch_p0_0: endpoint { ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ remote-endpoint = <&es8316_p0_0>; ++ }; ++ }; ++}; ++ ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ ++&package_thermal { ++ polling-delay = <1000>; ++ ++ trips { ++ package_fan0: package-fan0 { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ package_fan1: package-fan1 { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&package_fan0>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map1 { ++ trip = <&package_fan1>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ ++&pcie2x1l0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_rst>; ++ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; ++ status = "okay"; ++}; ++ ++&pcie2x1l2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_2_rst>; ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_rst>; ++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ ++&pinctrl { ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie2 { ++ pcie2_0_rst: pcie2-0-rst { ++ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2_2_rst: pcie2-2-rst { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie3 { ++ pcie3_rst: pcie3-rst { ++ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie3_vcc3v3_en: pcie3-vcc3v3-en { ++ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ usbc0_int: usbc0-int { ++ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vbus5v0_typec_en: vbus5v0-typec-en { ++ rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ max-frequency = <200000000>; ++ no-sdio; ++ no-mmc; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_s3>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&sfc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fspim2_pins>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <104000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ vcc-supply = <&vcc_3v3_s3>; ++ }; ++}; ++ ++&spi2 { ++ status = "okay"; ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ num-cs = <1>; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ spi-max-frequency = <1000000>; ++ reg = <0x0>; ++ ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ ++ system-power-controller; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc5v0_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc5v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc5v0_sys>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vccio_sd_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ /* connected to USB hub, which is powered by vcc5v0_sys */ ++ phy-supply = <&vcc5v0_sys>; ++ status = "okay"; ++}; ++ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usbdp_phy0 { ++ mode-switch; ++ orientation-switch; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usbdp_phy0_orientation_switch: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_orien_sw>; ++ }; ++ ++ usbdp_phy0_dp_altmode_mux: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&dp_altmode_mux>; ++ }; ++ }; ++}; ++ ++&usbdp_phy1 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ dwc3_0_role_switch: endpoint { ++ remote-endpoint = <&usbc0_role_sw>; ++ }; ++ }; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts +index 74c7b6502e4..4096cd853f9 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts +@@ -99,12 +99,28 @@ + }; + + usb { ++ usbc_sbu_dc: usbc-sbu-dc { ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, ++ <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + ++&usbc0 { ++ status = "okay"; ++}; ++ ++&usbdp_phy0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usbc_sbu_dc>; ++ sbu1-dc-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; ++ sbu2-dc-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++}; ++ + &vcc5v0_host { + enable-active-high; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts +index 9407a7c9910..ca354a1b0e6 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts +@@ -36,8 +36,20 @@ + status = "okay"; + }; + ++&usbdp_phy0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usbc_sbu_dc>; ++ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; ++ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; ++}; ++ + &pinctrl { + usb { ++ usbc_sbu_dc: usbc-sbu-dc { ++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, ++ <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi +index 4bdc16ea36a..e5c474e4d02 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi +@@ -2,23 +2,9 @@ + + /dts-v1/; + +-#include +-#include +-#include +-#include +-#include "rk3588.dtsi" ++#include "rk3588-rock-5b-5bp-5t.dtsi" + + / { +- aliases { +- mmc0 = &sdhci; +- mmc1 = &sdmmc; +- mmc2 = &sdio; +- }; +- +- chosen { +- stdout-path = "serial2:1500000n8"; +- }; +- + analog-sound { + compatible = "audio-graph-card"; + label = "rk3588-es8316"; +@@ -36,28 +22,6 @@ + pinctrl-0 = <&hp_detect>; + }; + +- hdmi0-con { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi0_con_in: endpoint { +- remote-endpoint = <&hdmi0_out_con>; +- }; +- }; +- }; +- +- hdmi1-con { +- compatible = "hdmi-connector"; +- type = "a"; +- +- port { +- hdmi1_con_in: endpoint { +- remote-endpoint = <&hdmi1_out_con>; +- }; +- }; +- }; +- + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -71,457 +35,19 @@ + }; + }; + +- fan: pwm-fan { +- compatible = "pwm-fan"; +- cooling-levels = <0 120 150 180 210 240 255>; +- fan-supply = <&vcc5v0_sys>; +- pwms = <&pwm1 0 50000 0>; +- #cooling-cells = <2>; +- }; +- + rfkill { + compatible = "rfkill-gpio"; + label = "rfkill-m2-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + }; +- +- rfkill-bt { +- compatible = "rfkill-gpio"; +- label = "rfkill-m2-bt"; +- radio-type = "bluetooth"; +- shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +- }; +- +- +- vbus5v0_typec: vbus5v0-typec { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vbus5v0_typec_en>; +- regulator-name = "vbus5v0_typec"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc12v_dcin: regulator-vcc12v-dcin { +- compatible = "regulator-fixed"; +- regulator-name = "vcc12v_dcin"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- }; +- +- vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_0_vcc3v3_en>; +- regulator-name = "vcc3v3_pcie2x1l0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <50000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3_pcie2x1l2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <5000>; +- vin-supply = <&vcc_3v3_s3>; +- }; +- +- vcc3v3_pcie30: regulator-vcc3v3-pcie30 { +- compatible = "regulator-fixed"; +- enable-active-high; +- gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_vcc3v3_en>; +- regulator-name = "vcc3v3_pcie30"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- startup-delay-us = <5000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_host: regulator-vcc5v0-host { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_host"; +- regulator-boot-on; +- regulator-always-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v0_sys>; +- }; +- +- vcc5v0_sys: regulator-vcc5v0-sys { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc12v_dcin>; +- }; +- +- vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc_1v1_nldo_s3"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; +- vin-supply = <&vcc5v0_sys>; +- }; +-}; +- +-&combphy0_ps { +- status = "okay"; +-}; +- +-&combphy1_ps { +- status = "okay"; +-}; +- +-&combphy2_psu { +- status = "okay"; +-}; +- +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_big0_s0>; +-}; +- +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_big0_s0>; +-}; +- +-&cpu_b2 { +- cpu-supply = <&vdd_cpu_big1_s0>; +-}; +- +-&cpu_b3 { +- cpu-supply = <&vdd_cpu_big1_s0>; +-}; +- +-&cpu_l0 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l1 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l2 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&cpu_l3 { +- cpu-supply = <&vdd_cpu_lit_s0>; +-}; +- +-&gpu { +- mali-supply = <&vdd_gpu_s0>; +- status = "okay"; +-}; +- +-&hdmi0 { +- status = "okay"; +-}; +- +-&hdmi0_in { +- hdmi0_in_vp0: endpoint { +- remote-endpoint = <&vp0_out_hdmi0>; +- }; +-}; +- +-&hdmi0_out { +- hdmi0_out_con: endpoint { +- remote-endpoint = <&hdmi0_con_in>; +- }; +-}; +- +-&hdmi0_sound { +- status = "okay"; +-}; +- +-&hdmi1 { +- pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd +- &hdmim1_tx1_scl &hdmim1_tx1_sda>; +- status = "okay"; +-}; +- +-&hdmi1_in { +- hdmi1_in_vp1: endpoint { +- remote-endpoint = <&vp1_out_hdmi1>; +- }; +-}; +- +-&hdmi1_out { +- hdmi1_out_con: endpoint { +- remote-endpoint = <&hdmi1_con_in>; +- }; +-}; +- +-&hdmi1_sound { +- status = "okay"; +-}; +- +-&hdmi_receiver_cma { +- status = "okay"; + }; + + &hdmi_receiver { + hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&hdptxphy0 { +- status = "okay"; +-}; +- +-&hdptxphy1 { +- status = "okay"; +-}; +- +-&i2c0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0m2_xfer>; +- status = "okay"; +- +- vdd_cpu_big0_s0: regulator@42 { +- compatible = "rockchip,rk8602"; +- reg = <0x42>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_big0_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <1050000>; +- regulator-ramp-delay = <2300>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_big1_s0: regulator@43 { +- compatible = "rockchip,rk8603", "rockchip,rk8602"; +- reg = <0x43>; +- fcs,suspend-voltage-selector = <1>; +- regulator-name = "vdd_cpu_big1_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <1050000>; +- regulator-ramp-delay = <2300>; +- vin-supply = <&vcc5v0_sys>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +-}; +- +-&i2c3 { +- status = "okay"; +-}; +- +-&i2c4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c4m1_xfer>; +- status = "okay"; +- +- usbc0: usb-typec@22 { +- compatible = "fcs,fusb302"; +- reg = <0x22>; +- interrupt-parent = <&gpio3>; +- interrupts = ; +- pinctrl-names = "default"; +- pinctrl-0 = <&usbc0_int>; +- vbus-supply = <&vcc12v_dcin>; +- /* +- * When the board is starting to send power-delivery messages +- * too late (5 seconds according to the specification), the +- * power-supply reacts with a hard-reset. That removes the +- * power from VBUS for some time, which resets te whole board. +- */ +- status = "fail"; +- +- usb_con: connector { +- compatible = "usb-c-connector"; +- label = "USB-C"; +- data-role = "dual"; +- power-role = "sink"; +- try-power-role = "sink"; +- op-sink-microwatt = <1000000>; +- sink-pdos = +- , +- ; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- usbc0_role_sw: endpoint { +- remote-endpoint = <&dwc3_0_role_switch>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- usbc0_orien_sw: endpoint { +- remote-endpoint = <&usbdp_phy0_orientation_switch>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- dp_altmode_mux: endpoint { +- remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; +- }; +- }; +- }; +- }; +- }; +-}; +- +-&i2c6 { +- status = "okay"; +- +- hym8563: rtc@51 { +- compatible = "haoyu,hym8563"; +- reg = <0x51>; +- #clock-cells = <0>; +- clock-output-names = "hym8563"; +- pinctrl-names = "default"; +- pinctrl-0 = <&hym8563_int>; +- interrupt-parent = <&gpio0>; +- interrupts = ; +- wakeup-source; +- }; +-}; +- +-&i2c7 { +- status = "okay"; +- +- es8316: audio-codec@11 { +- compatible = "everest,es8316"; +- reg = <0x11>; +- clocks = <&cru I2S0_8CH_MCLKOUT>; +- clock-names = "mclk"; +- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +- assigned-clock-rates = <12288000>; +- #sound-dai-cells = <0>; +- +- port { +- es8316_p0_0: endpoint { +- remote-endpoint = <&i2s0_8ch_p0_0>; +- }; +- }; +- }; +-}; +- +-&i2s0_8ch { +- pinctrl-names = "default"; +- pinctrl-0 = <&i2s0_lrck +- &i2s0_mclk +- &i2s0_sclk +- &i2s0_sdi0 +- &i2s0_sdo0>; +- status = "okay"; +- +- i2s0_8ch_p0: port { +- i2s0_8ch_p0_0: endpoint { +- dai-format = "i2s"; +- mclk-fs = <256>; +- remote-endpoint = <&es8316_p0_0>; +- }; +- }; +-}; +- +-&i2s5_8ch { +- status = "okay"; +-}; +- +-&i2s6_8ch { +- status = "okay"; +-}; +- +-&package_thermal { +- polling-delay = <1000>; +- +- trips { +- package_fan0: package-fan0 { +- temperature = <55000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- package_fan1: package-fan1 { +- temperature = <65000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map0 { +- trip = <&package_fan0>; +- cooling-device = <&fan THERMAL_NO_LIMIT 1>; +- }; +- +- map1 { +- trip = <&package_fan1>; +- cooling-device = <&fan 2 THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&pcie2x1l0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_0_rst>; +- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; +- status = "okay"; +-}; +- +-&pcie2x1l2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie2_2_rst>; +- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; +- status = "okay"; +-}; +- +-&pcie30phy { +- status = "okay"; +-}; +- +-&pcie3x4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_rst>; +- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; +- vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; + }; + +-&pd_gpu { +- domain-supply = <&vdd_gpu_s0>; +-}; +- + &pinctrl { + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { +@@ -529,560 +55,32 @@ + }; + }; + +- hym8563 { +- hym8563_int: hym8563-int { +- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- + leds { + led_rgb_b: led-rgb-b { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +- sound { +- hp_detect: hp-detect { +- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- + pcie2 { +- pcie2_0_rst: pcie2-0-rst { +- rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- + pcie2_0_vcc3v3_en: pcie2-0-vcc-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; +- +- pcie2_2_rst: pcie2-2-rst { +- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +- }; + }; + +- pcie3 { +- pcie3_rst: pcie3-rst { +- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- pcie3_vcc3v3_en: pcie3-vcc3v3-en { +- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +- +- usb { +- usbc0_int: usbc0-int { +- rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- vbus5v0_typec_en: vbus5v0-typec-en { +- rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- }; +-}; +- +-&pwm1 { +- status = "okay"; +-}; +- +-&saradc { +- vref-supply = <&avcc_1v8_s0>; +- status = "okay"; +-}; +- +-&sdhci { +- bus-width = <8>; +- no-sdio; +- no-sd; +- non-removable; +- max-frequency = <150000000>; +- mmc-hs200-1_8v; +- status = "okay"; +-}; +- +-&sdmmc { +- max-frequency = <200000000>; +- no-sdio; +- no-mmc; +- bus-width = <4>; +- cap-mmc-highspeed; +- cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; +- disable-wp; +- sd-uhs-sdr104; +- vmmc-supply = <&vcc_3v3_s3>; +- vqmmc-supply = <&vccio_sd_s0>; +- status = "okay"; +-}; +- +-&sfc { +- pinctrl-names = "default"; +- pinctrl-0 = <&fspim2_pins>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <104000000>; +- spi-rx-bus-width = <4>; +- spi-tx-bus-width = <1>; +- }; +-}; +- +-&spi2 { +- status = "okay"; +- assigned-clocks = <&cru CLK_SPI2>; +- assigned-clock-rates = <200000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; +- num-cs = <1>; +- +- pmic@0 { +- compatible = "rockchip,rk806"; +- spi-max-frequency = <1000000>; +- reg = <0x0>; +- +- interrupt-parent = <&gpio0>; +- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, +- <&rk806_dvs2_null>, <&rk806_dvs3_null>; +- +- system-power-controller; +- +- vcc1-supply = <&vcc5v0_sys>; +- vcc2-supply = <&vcc5v0_sys>; +- vcc3-supply = <&vcc5v0_sys>; +- vcc4-supply = <&vcc5v0_sys>; +- vcc5-supply = <&vcc5v0_sys>; +- vcc6-supply = <&vcc5v0_sys>; +- vcc7-supply = <&vcc5v0_sys>; +- vcc8-supply = <&vcc5v0_sys>; +- vcc9-supply = <&vcc5v0_sys>; +- vcc10-supply = <&vcc5v0_sys>; +- vcc11-supply = <&vcc_2v0_pldo_s3>; +- vcc12-supply = <&vcc5v0_sys>; +- vcc13-supply = <&vcc_1v1_nldo_s3>; +- vcc14-supply = <&vcc_1v1_nldo_s3>; +- vcca-supply = <&vcc5v0_sys>; +- +- gpio-controller; +- #gpio-cells = <2>; +- +- rk806_dvs1_null: dvs1-null-pins { +- pins = "gpio_pwrctrl1"; +- function = "pin_fun0"; +- }; +- +- rk806_dvs2_null: dvs2-null-pins { +- pins = "gpio_pwrctrl2"; +- function = "pin_fun0"; +- }; +- +- rk806_dvs3_null: dvs3-null-pins { +- pins = "gpio_pwrctrl3"; +- function = "pin_fun0"; +- }; +- +- regulators { +- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_gpu_s0"; +- regulator-enable-ramp-delay = <400>; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_cpu_lit_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_log_s0: dcdc-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <750000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_log_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <750000>; +- }; +- }; +- +- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <550000>; +- regulator-max-microvolt = <950000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_vdenc_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_ddr_s0: dcdc-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <675000>; +- regulator-max-microvolt = <900000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_ddr_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <850000>; +- }; +- }; +- +- vdd2_ddr_s3: dcdc-reg6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vdd2_ddr_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- }; +- }; +- +- vcc_2v0_pldo_s3: dcdc-reg7 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <2000000>; +- regulator-max-microvolt = <2000000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vdd_2v0_pldo_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <2000000>; +- }; +- }; +- +- vcc_3v3_s3: dcdc-reg8 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-name = "vcc_3v3_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; +- }; +- }; +- +- vddq_ddr_s0: dcdc-reg9 { +- regulator-always-on; +- regulator-boot-on; +- regulator-name = "vddq_ddr_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v8_s3: dcdc-reg10 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_1v8_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- avcc_1v8_s0: pldo-reg1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "avcc_1v8_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_1v8_s0: pldo-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "vcc_1v8_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- avdd_1v2_s0: pldo-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1200000>; +- regulator-max-microvolt = <1200000>; +- regulator-name = "avdd_1v2_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vcc_3v3_s0: pldo-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vcc_3v3_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vccio_sd_s0: pldo-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-ramp-delay = <12500>; +- regulator-name = "vccio_sd_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- pldo6_s3: pldo-reg6 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- regulator-name = "pldo6_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1800000>; +- }; +- }; +- +- vdd_0v75_s3: nldo-reg1 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "vdd_0v75_s3"; +- +- regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <750000>; +- }; +- }; +- +- vdd_ddr_pll_s0: nldo-reg2 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-name = "vdd_ddr_pll_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- regulator-suspend-microvolt = <850000>; +- }; +- }; +- +- avdd_0v75_s0: nldo-reg3 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "avdd_0v75_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_0v85_s0: nldo-reg4 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <850000>; +- regulator-max-microvolt = <850000>; +- regulator-name = "vdd_0v85_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- +- vdd_0v75_s0: nldo-reg5 { +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <750000>; +- regulator-max-microvolt = <750000>; +- regulator-name = "vdd_0v75_s0"; +- +- regulator-state-mem { +- regulator-off-in-suspend; +- }; +- }; +- }; +- }; +-}; +- +-&tsadc { +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-0 = <&uart2m0_xfer>; +- status = "okay"; +-}; +- +-&u2phy0 { +- status = "okay"; +-}; +- +-&u2phy0_otg { +- status = "okay"; +-}; +- +-&u2phy1 { +- status = "okay"; +-}; +- +-&u2phy1_otg { +- status = "okay"; +-}; +- +-&u2phy2 { +- status = "okay"; +-}; +- +-&u2phy2_host { +- /* connected to USB hub, which is powered by vcc5v0_sys */ +- phy-supply = <&vcc5v0_sys>; +- status = "okay"; +-}; +- +-&u2phy3 { +- status = "okay"; +-}; +- +-&u2phy3_host { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +-}; +- +-&usbdp_phy1 { +- status = "okay"; +-}; +- +-&usbdp_phy0 { +- mode-switch; +- orientation-switch; +- sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; +- sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; +- status = "okay"; +- +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- usbdp_phy0_orientation_switch: endpoint@0 { +- reg = <0>; +- remote-endpoint = <&usbc0_orien_sw>; +- }; +- +- usbdp_phy0_dp_altmode_mux: endpoint@1 { +- reg = <1>; +- remote-endpoint = <&dp_altmode_mux>; +- }; +- }; +-}; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- +-&usb_host0_xhci { +- usb-role-switch; +- status = "okay"; +- +- port { +- #address-cells = <1>; +- #size-cells = <0>; +- +- dwc3_0_role_switch: endpoint { +- remote-endpoint = <&usbc0_role_sw>; ++ sound { ++ hp_detect: hp-detect { ++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- +-&usb_host1_xhci { +- dr_mode = "host"; +- status = "okay"; +-}; +- + &usb_host2_xhci { + status = "okay"; + }; + +-&vop { +- status = "okay"; +-}; +- +-&vop_mmu { ++&vcc3v3_pcie2x1l0 { ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_vcc3v3_en>; + status = "okay"; + }; +- +-&vp0 { +- vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { +- reg = ; +- remote-endpoint = <&hdmi0_in_vp0>; +- }; +-}; +- +-&vp1 { +- vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { +- reg = ; +- remote-endpoint = <&hdmi1_in_vp1>; +- }; +-}; +-- +GitLab diff --git a/patch/u-boot/v2025.04/board_rock-5t/0002-Add-Rock5T-dts-to-upstream-dir.patch b/patch/u-boot/v2025.04/board_rock-5t/0002-Add-Rock5T-dts-to-upstream-dir.patch new file mode 100644 index 000000000..adb627951 --- /dev/null +++ b/patch/u-boot/v2025.04/board_rock-5t/0002-Add-Rock5T-dts-to-upstream-dir.patch @@ -0,0 +1,124 @@ +From 72217a692f1b47375c47c749897e63d4a188c03a Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Fri, 9 May 2025 11:35:13 +0200 +Subject: [PATCH] [HACK] add ROCK 5T dts to upstream dir + +Signed-off-by: Nicolas Frattaroli +--- + .../src/arm64/rockchip/rk3588-rock-5t.dts | 105 ++++++++++++++++++ + 1 file changed, 105 insertions(+) + create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-rock-5t.dts + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5t.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5t.dts +new file mode 100644 +index 00000000000..258c7400301 +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5t.dts +@@ -0,0 +1,105 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3588-rock-5b-5bp-5t.dtsi" ++ ++/ { ++ model = "Radxa ROCK 5T"; ++ compatible = "radxa,rock-5t", "rockchip,rk3588"; ++ ++ analog-sound { ++ compatible = "audio-graph-card"; ++ label = "rk3588-es8316"; ++ ++ widgets = "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ ++ routing = "MIC2", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR"; ++ ++ dais = <&i2s0_8ch_p0>; ++ hp-det-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_detect>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_rgb_b>; ++ ++ led_rgb_b { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ rfkill { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-m2-wlan"; ++ radio-type = "wlan"; ++ shutdown-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vcc3v3_pcie2x1l1: regulator-vcc3v3-pcie2x1l2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie2x1l1"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++}; ++ ++&hdmi_receiver { ++ hpd-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pcie2x1l1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_1_rst>; ++ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l1>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ hdmirx { ++ hdmirx_hpd: hdmirx-5v-detection { ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ leds { ++ led_rgb_b: led-rgb-b { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie2 { ++ pcie2_1_rst: pcie2-1-rst { ++ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { ++ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sound { ++ hp_detect: hp-detect { ++ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&vcc3v3_pcie2x1l0 { ++ gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_vcc3v3_en>; ++ status = "okay"; ++}; +-- +GitLab diff --git a/patch/u-boot/v2025.04/board_rock-5t/0003-Add-Rock5T-support.patch b/patch/u-boot/v2025.04/board_rock-5t/0003-Add-Rock5T-support.patch new file mode 100644 index 000000000..644718ef6 --- /dev/null +++ b/patch/u-boot/v2025.04/board_rock-5t/0003-Add-Rock5T-support.patch @@ -0,0 +1,323 @@ +From 79954f1b4f1291431bdf8e175eac60154938a089 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Fri, 9 May 2025 11:37:46 +0200 +Subject: [PATCH] board: radxa: add ROCK 5T support + +The ROCK 5T is quite similar to the ROCK 5B+. Since we can't tell it +apart from the ROCK 5B+ based on memory type, as both always ship with +LPDDR5, add it as its own separate board without the auto FDT detection. + +Signed-off-by: Nicolas Frattaroli +--- + arch/arm/dts/rk3588-rock-5t-u-boot.dtsi | 77 ++++++++++++++++ + arch/arm/mach-rockchip/rk3588/Kconfig | 28 ++++++ + board/radxa/rock5t-rk3588/Kconfig | 12 +++ + board/radxa/rock5t-rk3588/MAINTAINERS | 7 ++ + configs/rock5t-rk3588_defconfig | 111 ++++++++++++++++++++++++ + include/configs/rock5t-rk3588.h | 14 +++ + 6 files changed, 249 insertions(+) + create mode 100644 arch/arm/dts/rk3588-rock-5t-u-boot.dtsi + create mode 100644 board/radxa/rock5t-rk3588/Kconfig + create mode 100644 board/radxa/rock5t-rk3588/MAINTAINERS + create mode 100644 configs/rock5t-rk3588_defconfig + create mode 100644 include/configs/rock5t-rk3588.h + +diff --git a/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi +new file mode 100644 +index 00000000000..c9440382587 +--- /dev/null ++++ b/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi +@@ -0,0 +1,77 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2025 Collabora Ltd. ++ */ ++ ++#include ++#include "rk3588-u-boot.dtsi" ++ ++/ { ++ leds { ++ led_rgb_b { ++ default-state = "on"; ++ }; ++ }; ++}; ++ ++&fspim2_pins { ++ bootph-pre-ram; ++ bootph-some-ram; ++}; ++ ++&i2c4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4m1_xfer>; ++ status = "okay"; ++ ++ usbc0: usb-typec@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio3>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ usb_con: connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ data-role = "dual"; ++ power-role = "sink"; ++ try-power-role = "sink"; ++ op-sink-microwatt = <1000000>; ++ sink-pdos = ++ , ++ ; ++ }; ++ }; ++}; ++ ++&sdhci { ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++}; ++ ++&sfc { ++ flash@0 { ++ bootph-pre-ram; ++ bootph-some-ram; ++ }; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&usbdp_phy0 { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "peripheral"; ++ maximum-speed = "high-speed"; ++ status = "okay"; ++}; +diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig +index 155b8f00ca2..1deb7597bb2 100644 +--- a/arch/arm/mach-rockchip/rk3588/Kconfig ++++ b/arch/arm/mach-rockchip/rk3588/Kconfig +@@ -302,6 +302,33 @@ config TARGET_ROCK_5C_RK3588S + 2x USB 2.0 Type-A HOST port + 1x USB Type-C 5V power port + ++config TARGET_ROCK5T_RK3588 ++ bool "Radxa ROCK5T RK3588 board" ++ select BOARD_LATE_INIT ++ help ++ Radxa ROCK5T is a Rockchip RK3588 based SBC (Single Board Computer) ++ by Radxa. ++ ++ Specification: ++ ++ Rockchip Rk3588 SoC ++ 4x ARM Cortex-A76, 4x ARM Cortex-A55 ++ 4/8/16/24/32GB memory LPDDR5 ++ Mali G610MC4 GPU ++ 2x 4-lane or 4x 2-lane MIPI CSI input ++ soldered eMMC (optional) ++ SPI flash for bootloader ++ uSD slot ++ 2x USB 2.0 Type-A, 2x USB 3.1 Gen1 Type-A, 1x USB 3.1 Gen1 Type-C ++ 2x HDMI 2.1 output, 1x HDMI input ++ 2x 2.5 Gbps Ethernet port ++ 2x M.2 M-key connector, PCIe 3 2-lanes each ++ On-board PCIe Wi-Fi/BT module ++ 40-pin IO header including UART, SPI, I2C and 5V DC power in ++ USB PD over USB Type-C ++ 5.5mm OD x 2.5mm ID barrel jack power input ++ Size: 110mm x 82mm ++ + config TARGET_SIGE7_RK3588 + bool "ArmSoM Sige7 RK3588 board" + select BOARD_LATE_INIT +@@ -440,6 +467,7 @@ source "board/pine64/quartzpro64-rk3588/Kconfig" + source "board/turing/turing-rk1-rk3588/Kconfig" + source "board/radxa/rock5a-rk3588s/Kconfig" + source "board/radxa/rock5b-rk3588/Kconfig" ++source "board/radxa/rock5t-rk3588/Kconfig" + source "board/radxa/rock-5-itx-rk3588/Kconfig" + source "board/radxa/rock-5c-rk3588s/Kconfig" + source "board/rockchip/evb_rk3588/Kconfig" +diff --git a/board/radxa/rock5t-rk3588/Kconfig b/board/radxa/rock5t-rk3588/Kconfig +new file mode 100644 +index 00000000000..82613ab3c2e +--- /dev/null ++++ b/board/radxa/rock5t-rk3588/Kconfig +@@ -0,0 +1,12 @@ ++if TARGET_ROCK5T_RK3588 ++ ++config SYS_BOARD ++ default "rock5t-rk3588" ++ ++config SYS_VENDOR ++ default "radxa" ++ ++config SYS_CONFIG_NAME ++ default "rock5t-rk3588" ++ ++endif +diff --git a/board/radxa/rock5t-rk3588/MAINTAINERS b/board/radxa/rock5t-rk3588/MAINTAINERS +new file mode 100644 +index 00000000000..677fe7d971b +--- /dev/null ++++ b/board/radxa/rock5t-rk3588/MAINTAINERS +@@ -0,0 +1,7 @@ ++ROCK5T-RK3588 ++M: Nicolas Frattaroli ++S: Maintained ++F: board/radxa/rock5t-rk3588 ++F: include/configs/rock5t-rk3588.h ++F: configs/rock5t-rk3588_defconfig ++F: arch/arm/dts/rk3588-rock-5t-u-boot.dtsi +diff --git a/configs/rock5t-rk3588_defconfig b/configs/rock5t-rk3588_defconfig +new file mode 100644 +index 00000000000..fa27c549758 +--- /dev/null ++++ b/configs/rock5t-rk3588_defconfig +@@ -0,0 +1,111 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=24000000 ++CONFIG_SF_DEFAULT_MODE=0x2000 ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-rock-5t" ++CONFIG_ROCKCHIP_RK3588=y ++CONFIG_ROCKCHIP_SPI_IMAGE=y ++CONFIG_SPL_SERIAL=y ++CONFIG_TARGET_ROCK5T_RK3588=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_SF_DEFAULT_BUS=5 ++CONFIG_DEBUG_UART_BASE=0xFEB50000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_AHCI=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5t.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 ++CONFIG_SPL_ATF=y ++CONFIG_CMD_TCPM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_ROCKUSB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_AHCI_PCI=y ++CONFIG_DWC_AHCI=y ++CONFIG_SPL_CLK=y ++# CONFIG_USB_FUNCTION_FASTBOOT is not set ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_XTX=y ++CONFIG_PHYLIB=y ++CONFIG_RTL8169=y ++CONFIG_NVME_PCI=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_PHY_ROCKCHIP_USBDP=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_SCSI=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SFC=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_SPL_USB_DWC3_GENERIC=y ++CONFIG_TYPEC_TCPM=y ++CONFIG_TYPEC_FUSB302=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_LAN75XX=y ++CONFIG_USB_ETHER_LAN78XX=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_USB_FUNCTION_ROCKUSB=y ++CONFIG_ERRNO_STR=y ++CONFIG_NET_PREFER_ROM_MAC_ADDR=y +diff --git a/include/configs/rock5t-rk3588.h b/include/configs/rock5t-rk3588.h +new file mode 100644 +index 00000000000..a0e2e84e9ff +--- /dev/null ++++ b/include/configs/rock5t-rk3588.h +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0+ ++ * Copyright (c) 2025 Collabora Ltd. ++ */ ++ ++#ifndef __ROCK5T_RK3588_H ++#define __ROCK5T_RK3588_H ++ ++#define ROCKCHIP_DEVICE_SETTINGS \ ++ "stdout=serial,vidconsole\0" \ ++ "stderr=serial,vidconsole\0" ++ ++#include ++ ++#endif /* __ROCK5T_RK3588_H */ +-- +GitLab diff --git a/patch/u-boot/v2025.10/board_rock-5b-plus/0001-Set-NET_PREFER_ROM_MAC_ADDR.patch b/patch/u-boot/v2025.10/board_rock-5b-plus/0001-Set-NET_PREFER_ROM_MAC_ADDR.patch new file mode 100644 index 000000000..ce55032cc --- /dev/null +++ b/patch/u-boot/v2025.10/board_rock-5b-plus/0001-Set-NET_PREFER_ROM_MAC_ADDR.patch @@ -0,0 +1,20 @@ +From 4491dae1a3408161be4d665e986aa2d5987c9251 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Mon, 22 Apr 2024 09:56:19 -0400 +Subject: [PATCH] configs/rock5b: Set NET_PREFER_ROM_MAC_ADDR to y + +--- + configs/rock5b-rk3588_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig +index 6349e879145..9c1e5df0924 100644 +--- a/configs/rock5b-rk3588_defconfig ++++ b/configs/rock5b-rk3588_defconfig +@@ -108,3 +108,4 @@ CONFIG_USB_GADGET=y + CONFIG_USB_GADGET_DOWNLOAD=y + CONFIG_USB_FUNCTION_ROCKUSB=y + CONFIG_ERRNO_STR=y ++CONFIG_NET_PREFER_ROM_MAC_ADDR=y +-- +GitLab diff --git a/patch/u-boot/v2025.10/board_rock-5b-plus/0002-Add-ROCK-5BPlus-support.patch b/patch/u-boot/v2025.10/board_rock-5b-plus/0002-Add-ROCK-5BPlus-support.patch new file mode 100644 index 000000000..22003ed87 --- /dev/null +++ b/patch/u-boot/v2025.10/board_rock-5b-plus/0002-Add-ROCK-5BPlus-support.patch @@ -0,0 +1,96 @@ +From 698bf35ed797f2a9ffdbeea5e83ea4ad7ed5a7b2 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Wed, 2 Apr 2025 19:54:47 +0200 +Subject: [PATCH] board: rock5b-rk3588: add ROCK 5B+ support + +The ROCK 5B and ROCK 5B+ are quite similar, but there are also a +few changes, which require a different device tree. Most of the +changes are not easily detectable at runtime, but it is possible +to tell the boards apart by checking the memory type. All ROCK +5B models use LPDDR4 and all ROCK 5B+ models use LPDDR5. + +Signed-off-by: Sebastian Reichel +--- + board/radxa/rock5b-rk3588/rock5b-rk3588.c | 65 +++++++++++++++++++++++ + 1 file changed, 65 insertions(+) + +diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c +index fc2f69db224..afe10ca0d16 100644 +--- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c ++++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c +@@ -5,6 +5,10 @@ + + #include + #include ++#include ++#include ++#include ++#include + + #ifdef CONFIG_OF_BOARD_SETUP + int ft_board_setup(void *blob, struct bd_info *bd) +@@ -14,3 +18,64 @@ int ft_board_setup(void *blob, struct bd_info *bd) + return 0; + } + #endif ++ ++enum { ++ ROCKCHIP_DDR4 = 0, ++ ROCKCHIP_DDR2 = 2, ++ ROCKCHIP_DDR3 = 3, ++ ROCKCHIP_LPDDR2 = 5, ++ ROCKCHIP_LPDDR3 = 6, ++ ROCKCHIP_LPDDR4 = 7, ++ ROCKCHIP_LPDDR4X = 8, ++ ROCKCHIP_LPDDR5 = 9, ++ ROCKCHIP_DDR5 = 10, ++ ROCKCHIP_UNUSED = 0xFF ++}; ++ ++#define RK3588_PMUGRF_BASE_ADDR 0xfd58a000 ++#define RK3588_PMUGRF_OS_REG2 0x208 ++#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13) ++#define RK3588_PMUGRF_OS_REG3 0x20c ++#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28) ++#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12) ++ ++static int rk3588_get_memory_type(void) ++{ ++ u32 reg2 = readl(RK3588_PMUGRF_BASE_ADDR + RK3588_PMUGRF_OS_REG2); ++ u32 reg3 = readl(RK3588_PMUGRF_BASE_ADDR + RK3588_PMUGRF_OS_REG3); ++ u32 ddr_type; ++ ++ /* lower 3 bits of the DDR type */ ++ ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2); ++ ++ /* ++ * For version three and higher the upper two bits of the DDR type are ++ * in RK3588_PMUGRF_OS_REG3 ++ */ ++ if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3) ++ ddr_type |= FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3; ++ ++ return ddr_type; ++} ++ ++static const char* rock5_get_model_devicetree(void) ++{ ++ switch (rk3588_get_memory_type()) { ++ case ROCKCHIP_LPDDR5: ++ return "rockchip/rk3588-rock-5b-plus.dtb"; ++ case ROCKCHIP_LPDDR4: ++ default: ++ return "rockchip/rk3588-rock-5b.dtb"; ++ } ++} ++ ++int board_fit_config_name_match(const char *name) ++{ ++ return strcmp(name, rock5_get_model_devicetree()); ++} ++ ++int rk_board_late_init(void) ++{ ++ env_set("fdtfile", rock5_get_model_devicetree()); ++ return 0; ++}