From 41709dd756ce72a0933a049237ab174d318b4c43 Mon Sep 17 00:00:00 2001 From: hzyitc Date: Wed, 22 Feb 2023 16:24:41 +0800 Subject: [PATCH] meson: bump current to v6.1 and edge to v6.2 (#4843) * meson: bump current to v6.1 and edge to v6.2 --- config/kernel/linux-meson-current.config | 1369 ++-- config/kernel/linux-meson-edge.config | 84 +- .../sources/families/include/meson_common.inc | 8 +- ...-clock-speed-before-sending-HS-CMD13.patch | 73 - .../board_odroidc1/dts-Enable-HDMI.patch | 121 - .../board_onecloud/0001-add-dts.patch | 431 -- .../0002-dts-Support-HDMI.patch | 92 - .../usb-disable-ACA-check.patch | 33 - .../generate-uImage-instand-of-zImage.patch | 27 - .../meson-5.15/m8-m8b-m8m2-Support-HDMI.patch | 5568 ----------------- patch/kernel/meson-current | 2 +- 11 files changed, 924 insertions(+), 6884 deletions(-) delete mode 100644 patch/kernel/archive/meson-5.15/Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch delete mode 100644 patch/kernel/archive/meson-5.15/board_odroidc1/dts-Enable-HDMI.patch delete mode 100644 patch/kernel/archive/meson-5.15/board_onecloud/0001-add-dts.patch delete mode 100644 patch/kernel/archive/meson-5.15/board_onecloud/0002-dts-Support-HDMI.patch delete mode 100644 patch/kernel/archive/meson-5.15/board_onecloud/usb-disable-ACA-check.patch delete mode 100644 patch/kernel/archive/meson-5.15/generate-uImage-instand-of-zImage.patch delete mode 100644 patch/kernel/archive/meson-5.15/m8-m8b-m8m2-Support-HDMI.patch diff --git a/config/kernel/linux-meson-current.config b/config/kernel/linux-meson-current.config index 7ba8fd1a5..400dba6e8 100644 --- a/config/kernel/linux-meson-current.config +++ b/config/kernel/linux-meson-current.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.15.68 Kernel Configuration +# Linux/arm 6.1.12 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0" CONFIG_CC_IS_GCC=y @@ -13,11 +13,12 @@ CONFIG_LD_VERSION=23200 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_PAHOLE_VERSION=122 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y # # General setup @@ -40,7 +41,6 @@ CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZ4 is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y @@ -67,7 +67,6 @@ CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_IRQ_IPI=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set @@ -78,6 +77,8 @@ CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -105,6 +106,7 @@ CONFIG_USERMODE_DRIVER=y # CONFIG_BPF_PRELOAD is not set # end of BPF subsystem +CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set @@ -156,10 +158,13 @@ CONFIG_GENERIC_SCHED_CLOCK=y # CONFIG_UCLAMP_TASK is not set # end of Scheduler features +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +CONFIG_CGROUP_FAVOR_DYNMODS=y CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y @@ -199,6 +204,7 @@ CONFIG_RD_LZO=y CONFIG_RD_LZ4=y CONFIG_RD_ZSTD=y # CONFIG_BOOT_CONFIG is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LD_ORPHAN_WARN=y @@ -217,7 +223,6 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y -CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -230,7 +235,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y @@ -247,24 +251,13 @@ CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y -CONFIG_COMPAT_BRK=y -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -CONFIG_SLAB_MERGE_DEFAULT=y -# CONFIG_SLAB_FREELIST_RANDOM is not set -# CONFIG_SLAB_FREELIST_HARDENED is not set -# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -CONFIG_SLUB_CPU_PARTIAL=y CONFIG_SYSTEM_DATA_VERIFICATION=y # CONFIG_PROFILING is not set CONFIG_TRACEPOINTS=y # end of General setup CONFIG_ARM=y -CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HAS_GROUP_RELOCS=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_HAVE_PROC_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -284,19 +277,9 @@ CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C24XX is not set -# CONFIG_ARCH_OMAP1 is not set # -# Multiple platform selection +# Platform selection # # @@ -305,9 +288,10 @@ CONFIG_ARCH_MULTIPLATFORM=y # CONFIG_ARCH_MULTI_V6 is not set CONFIG_ARCH_MULTI_V7=y CONFIG_ARCH_MULTI_V6_V7=y -# end of Multiple platform selection +# end of Platform selection # CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_AIROHA is not set # CONFIG_ARCH_ACTIONS is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_ARTPEC is not set @@ -316,9 +300,11 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_ARCH_BCM is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_DIGICOLOR is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_EXYNOS is not set # CONFIG_ARCH_HIGHBANK is not set # CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_HPE is not set # CONFIG_ARCH_MXC is not set # CONFIG_ARCH_KEYSTONE is not set # CONFIG_ARCH_MEDIATEK is not set @@ -345,7 +331,6 @@ CONFIG_MACH_MESON8=y # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_RDA is not set # CONFIG_ARCH_REALTEK is not set -# CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_RENESAS is not set @@ -353,10 +338,12 @@ CONFIG_MACH_MESON8=y # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set +# CONFIG_ARCH_SUNPLUS is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_WM8850 is not set # CONFIG_ARCH_ZYNQ is not set @@ -386,6 +373,8 @@ CONFIG_ARM_THUMB=y CONFIG_ARM_THUMBEE=y CONFIG_ARM_VIRT_EXT=y CONFIG_SWP_EMULATE=y +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_BIG_ENDIAN is not set # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set # CONFIG_CPU_BPREDICT_DISABLE is not set @@ -414,6 +403,7 @@ CONFIG_DEBUG_ALIGN_RODATA=y # CONFIG_ARM_ERRATA_754322 is not set # CONFIG_ARM_ERRATA_754327 is not set # CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_764319 is not set # CONFIG_ARM_ERRATA_775420 is not set # CONFIG_ARM_ERRATA_798181 is not set # CONFIG_ARM_ERRATA_773022 is not set @@ -438,6 +428,8 @@ CONFIG_ARM_ERRATA_814220=y CONFIG_HAVE_SMP=y CONFIG_SMP=y CONFIG_SMP_ON_UP=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y +CONFIG_IRQSTACKS=y CONFIG_ARM_CPU_TOPOLOGY=y # CONFIG_SCHED_MC is not set # CONFIG_SCHED_SMT is not set @@ -475,9 +467,8 @@ CONFIG_HIGHMEM=y CONFIG_HIGHPTE=y CONFIG_CPU_SW_DOMAIN_PAN=y CONFIG_HW_PERF_EVENTS=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ARM_MODULE_PLTS=y -CONFIG_FORCE_MAX_ZONEORDER=12 +CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_ALIGNMENT_TRAP=y # CONFIG_UACCESS_WITH_MEMCPY is not set # CONFIG_PARAVIRT is not set @@ -491,6 +482,7 @@ CONFIG_STACKPROTECTOR_PER_TASK=y # CONFIG_USE_OF=y CONFIG_ATAGS=y +# CONFIG_UNUSED_BOARD_FILES is not set # CONFIG_DEPRECATED_PARAM_STRUCT is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 @@ -583,6 +575,7 @@ CONFIG_SUSPEND_FREEZER=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -599,25 +592,6 @@ CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y # end of Power management options -CONFIG_ARM_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM=m -CONFIG_CRYPTO_SHA1_ARM_NEON=m -CONFIG_CRYPTO_SHA1_ARM_CE=m -CONFIG_CRYPTO_SHA2_ARM_CE=m -CONFIG_CRYPTO_SHA256_ARM=m -CONFIG_CRYPTO_SHA512_ARM=m -CONFIG_CRYPTO_BLAKE2S_ARM=y -CONFIG_CRYPTO_BLAKE2B_NEON=m -CONFIG_CRYPTO_AES_ARM=m -CONFIG_CRYPTO_AES_ARM_BS=m -CONFIG_CRYPTO_AES_ARM_CE=m -CONFIG_CRYPTO_GHASH_ARM_CE=m -# CONFIG_CRYPTO_CRCT10DIF_ARM_CE is not set -CONFIG_CRYPTO_CRC32_ARM_CE=m -CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_POLY1305_ARM=m -CONFIG_CRYPTO_NHPOLY1305_NEON=m -CONFIG_CRYPTO_CURVE25519_NEON=m CONFIG_AS_VFP_VMRS_FPINST=y # @@ -663,27 +637,33 @@ CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_LTO_NONE=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_HAVE_ARCH_PFN_VALID=y @@ -697,9 +677,7 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y CONFIG_HAVE_GCC_PLUGINS=y CONFIG_GCC_PLUGINS=y -# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set -# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set CONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK=y # end of General architecture-dependent options @@ -710,6 +688,7 @@ CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_MODULE_SIG=y @@ -730,8 +709,10 @@ CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BLK_DEV_INTEGRITY_T10=y @@ -774,6 +755,7 @@ CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y CONFIG_BLK_PM=y CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLK_MQ_STACKING=y # # IO Schedulers @@ -817,6 +799,26 @@ CONFIG_COREDUMP=y # # Memory Management options # +CONFIG_SWAP=y +# CONFIG_ZSWAP is not set +CONFIG_ZSMALLOC=m +# CONFIG_ZSMALLOC_STAT is not set + +# +# SLAB allocator options +# +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SLUB_STATS is not set +CONFIG_SLUB_CPU_PARTIAL=y +# end of SLAB allocator options + +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_COMPAT_BRK=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set @@ -825,30 +827,30 @@ CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 # CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_BOUNCE=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 -CONFIG_ZPOOL=m -CONFIG_ZBUD=m -CONFIG_Z3FOLD=m -CONFIG_ZSMALLOC=m -# CONFIG_ZSMALLOC_STAT is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_VM_EVENT_COUNTERS=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set CONFIG_KMAP_LOCAL=y CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +# CONFIG_ANON_VMA_NAME is not set +# CONFIG_USERFAULTFD is not set +# CONFIG_LRU_GEN is not set # # Data Access Monitoring @@ -923,6 +925,7 @@ CONFIG_INET_ESP=m CONFIG_INET_ESP_OFFLOAD=m CONFIG_INET_ESPINTCP=y CONFIG_INET_IPCOMP=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 CONFIG_INET_XFRM_TUNNEL=m CONFIG_INET_TUNNEL=m CONFIG_INET_DIAG=m @@ -995,6 +998,8 @@ CONFIG_BRIDGE_NETFILTER=m # Core Netfilter Configuration # CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_SKIP_EGRESS=y CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_FAMILY_BRIDGE=y CONFIG_NETFILTER_FAMILY_ARP=y @@ -1048,7 +1053,6 @@ CONFIG_NF_TABLES_NETDEV=y CONFIG_NFT_NUMGEN=m CONFIG_NFT_CT=m CONFIG_NFT_FLOW_OFFLOAD=m -# CONFIG_NFT_COUNTER is not set CONFIG_NFT_CONNLIMIT=m CONFIG_NFT_LOG=m CONFIG_NFT_LIMIT=m @@ -1077,6 +1081,7 @@ CONFIG_NFT_FIB_NETDEV=m CONFIG_NFT_REJECT_NETDEV=m CONFIG_NF_FLOW_TABLE_INET=m CONFIG_NF_FLOW_TABLE=m +CONFIG_NF_FLOW_TABLE_PROCFS=y CONFIG_NETFILTER_XTABLES=m # @@ -1247,7 +1252,6 @@ CONFIG_NFT_REJECT_IPV4=m CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y -# CONFIG_NF_FLOW_TABLE_IPV4 is not set CONFIG_NF_DUP_IPV4=m CONFIG_NF_LOG_ARP=m CONFIG_NF_LOG_IPV4=m @@ -1286,7 +1290,6 @@ CONFIG_NF_TABLES_IPV6=y CONFIG_NFT_REJECT_IPV6=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m -# CONFIG_NF_FLOW_TABLE_IPV6 is not set CONFIG_NF_DUP_IPV6=m CONFIG_NF_REJECT_IPV6=m CONFIG_NF_LOG_IPV6=m @@ -1313,13 +1316,6 @@ CONFIG_IP6_NF_TARGET_NPT=m # end of IPv6: Netfilter Configuration CONFIG_NF_DEFRAG_IPV6=m - -# -# DECnet: Netfilter Configuration -# -CONFIG_DECNET_NF_GRABULATOR=m -# end of DECnet: Netfilter Configuration - CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m @@ -1404,8 +1400,6 @@ CONFIG_BRIDGE_CFM=y CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y -CONFIG_DECNET=m -CONFIG_DECNET_ROUTER=y CONFIG_LLC=m CONFIG_LLC2=m CONFIG_ATALK=m @@ -1617,6 +1611,7 @@ CONFIG_BT_INTEL=m CONFIG_BT_BCM=m CONFIG_BT_RTL=m CONFIG_BT_QCA=m +CONFIG_BT_MTK=m CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y CONFIG_BT_HCIBTUSB_BCM=y @@ -1705,6 +1700,7 @@ CONFIG_NET_SELFTESTS=y CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y +# CONFIG_PAGE_POOL_STATS is not set CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y @@ -1734,6 +1730,7 @@ CONFIG_PCIE_BUS_DEFAULT=y # CONFIG_PCIE_BUS_SAFE is not set # CONFIG_PCIE_BUS_PERFORMANCE is not set # CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_VGA_ARB is not set # CONFIG_HOTPLUG_PCI is not set # @@ -1791,6 +1788,7 @@ CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y @@ -1799,11 +1797,15 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" CONFIG_FW_LOADER_USER_HELPER=y # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +# CONFIG_FW_LOADER_COMPRESS_ZSTD is not set CONFIG_FW_CACHE=y +# CONFIG_FW_UPLOAD is not set # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y @@ -1832,6 +1834,7 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # CONFIG_MOXTET is not set CONFIG_VEXPRESS_CONFIG=y # CONFIG_MHI_BUS is not set +# CONFIG_MHI_BUS_EP is not set # end of Bus devices CONFIG_CONNECTOR=m @@ -1848,8 +1851,10 @@ CONFIG_ARM_SCMI_HAVE_TRANSPORT=y CONFIG_ARM_SCMI_HAVE_SHMEM=y CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y CONFIG_ARM_SCMI_TRANSPORT_SMC=y +CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set CONFIG_ARM_SCMI_POWER_DOMAIN=m +CONFIG_ARM_SCMI_POWER_CONTROL=m # end of ARM System Control and Management Interface Protocol # CONFIG_ARM_SCPI_PROTOCOL is not set @@ -1857,7 +1862,6 @@ CONFIG_ARM_SCMI_POWER_DOMAIN=m CONFIG_DMIID=y # CONFIG_DMI_SYSFS is not set # CONFIG_FW_CFG_SYSFS is not set -CONFIG_SYSFB=y # CONFIG_SYSFB_SIMPLEFB is not set # CONFIG_TRUSTED_FOUNDATIONS is not set # CONFIG_GOOGLE_FIRMWARE is not set @@ -1878,6 +1882,8 @@ CONFIG_EFI_CAPSULE_LOADER=m # CONFIG_EFI_TEST is not set # CONFIG_RESET_ATTACK_MITIGATION is not set # CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +# CONFIG_EFI_COCO_SECRET is not set # end of EFI (Extensible Firmware Interface) Support CONFIG_ARM_PSCI_FW=y @@ -1924,11 +1930,9 @@ CONFIG_ZRAM_WRITEBACK=y CONFIG_ZRAM_MEMORY_TRACKING=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -# CONFIG_BLK_DEV_CRYPTOLOOP is not set CONFIG_BLK_DEV_DRBD=m CONFIG_DRBD_FAULT_INJECTION=y CONFIG_BLK_DEV_NBD=m -# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=65536 @@ -1936,7 +1940,7 @@ CONFIG_BLK_DEV_RAM_SIZE=65536 CONFIG_ATA_OVER_ETH=m # CONFIG_VIRTIO_BLK is not set CONFIG_BLK_DEV_RBD=m -# CONFIG_BLK_DEV_RSXX is not set +CONFIG_BLK_DEV_UBLK=m # # NVME Support @@ -1975,6 +1979,8 @@ CONFIG_SRAM_EXEC=y # CONFIG_XILINX_SDFEC is not set CONFIG_MISC_RTSX=m # CONFIG_HISI_HIKEY_USB is not set +# CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_C2PORT is not set # @@ -2008,6 +2014,7 @@ CONFIG_EEPROM_93CX6=m CONFIG_MISC_RTSX_USB=m # CONFIG_HABANA_AI is not set # CONFIG_PVPANIC is not set +# CONFIG_GP_PCI1XXXX is not set # end of Misc devices # @@ -2075,8 +2082,8 @@ CONFIG_ISCSI_BOOT_SYSFS=m # CONFIG_SCSI_MPT2SAS is not set # CONFIG_SCSI_MPI3MR is not set # CONFIG_SCSI_SMARTPQI is not set -# CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_MYRB is not set # CONFIG_SCSI_MYRS is not set # CONFIG_LIBFC is not set @@ -2118,6 +2125,7 @@ CONFIG_SATA_PMP=y CONFIG_SATA_AHCI=y CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_AHCI_DWC is not set # CONFIG_AHCI_CEVA is not set # CONFIG_AHCI_QORIQ is not set # CONFIG_SATA_INIC162X is not set @@ -2192,7 +2200,7 @@ CONFIG_SATA_MV=y # CONFIG_PATA_MPIIX is not set # CONFIG_PATA_NS87410 is not set # CONFIG_PATA_OPTI is not set -# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_OF_PLATFORM is not set # CONFIG_PATA_RZ1000 is not set # @@ -2251,6 +2259,7 @@ CONFIG_DM_VERITY_FEC=y CONFIG_DM_SWITCH=m CONFIG_DM_LOG_WRITES=m CONFIG_DM_INTEGRITY=m +CONFIG_DM_AUDIT=y # CONFIG_TARGET_CORE is not set # CONFIG_FUSION is not set @@ -2286,6 +2295,7 @@ CONFIG_VXLAN=m CONFIG_GENEVE=m CONFIG_BAREUDP=m CONFIG_GTP=m +CONFIG_AMT=m CONFIG_MACSEC=m CONFIG_NETCONSOLE=m CONFIG_NETCONSOLE_DYNAMIC=y @@ -2312,6 +2322,7 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_AMD is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ASIX is not set # CONFIG_NET_VENDOR_ATHEROS is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CADENCE is not set @@ -2320,18 +2331,22 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_CIRRUS is not set # CONFIG_NET_VENDOR_CISCO is not set # CONFIG_NET_VENDOR_CORTINA is not set -# CONFIG_DM9000 is not set +# CONFIG_NET_VENDOR_DAVICOM is not set # CONFIG_DNET is not set # CONFIG_NET_VENDOR_DEC is not set # CONFIG_NET_VENDOR_DLINK is not set # CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set # CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set # CONFIG_NET_VENDOR_GOOGLE is not set # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_JME is not set +# CONFIG_NET_VENDOR_ADI is not set # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set @@ -2378,6 +2393,7 @@ CONFIG_DWMAC_MESON=y # CONFIG_NET_VENDOR_SYNOPSYS is not set # CONFIG_NET_VENDOR_TEHUTI is not set # CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set @@ -2396,6 +2412,7 @@ CONFIG_FIXED_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_MESON_GXL_PHY is not set # CONFIG_ADIN_PHY is not set +# CONFIG_ADIN1100_PHY is not set # CONFIG_AQUANTIA_PHY is not set CONFIG_AX88796B_PHY=m # CONFIG_BROADCOM_PHY is not set @@ -2436,9 +2453,11 @@ CONFIG_SMSC_PHY=m # CONFIG_DP83848_PHY is not set # CONFIG_DP83867_PHY is not set # CONFIG_DP83869_PHY is not set +# CONFIG_DP83TD510_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set +# CONFIG_PSE_CONTROLLER is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y CONFIG_FWNODE_MDIO=y @@ -2574,12 +2593,17 @@ CONFIG_MT7663_USB_SDIO_COMMON=m CONFIG_MT7663U=m CONFIG_MT7663S=m # CONFIG_MT7915E is not set +CONFIG_MT7921_COMMON=m # CONFIG_MT7921E is not set +CONFIG_MT7921S=m +CONFIG_MT7921U=m CONFIG_WLAN_VENDOR_MICROCHIP=y CONFIG_WILC1000=m CONFIG_WILC1000_SDIO=m # CONFIG_WILC1000_SPI is not set # CONFIG_WILC1000_HW_OOB_INTR is not set +CONFIG_WLAN_VENDOR_PURELIFI=y +# CONFIG_PLFXLC is not set CONFIG_WLAN_VENDOR_RALINK=y CONFIG_RT2X00=m # CONFIG_RT2400PCI is not set @@ -2624,7 +2648,10 @@ CONFIG_RTL8192C_COMMON=m CONFIG_RTL8XXXU=m CONFIG_RTL8XXXU_UNTESTED=y # CONFIG_RTW88 is not set +# CONFIG_RTW89 is not set # CONFIG_WLAN_VENDOR_RSI is not set +CONFIG_WLAN_VENDOR_SILABS=y +# CONFIG_WFX is not set # CONFIG_WLAN_VENDOR_ST is not set # CONFIG_WLAN_VENDOR_TI is not set CONFIG_WLAN_VENDOR_ZYDAS=y @@ -2666,6 +2693,7 @@ CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_SPARSEKMAP is not set # CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_VIVALDIFMAP=y # # Userland interfaces @@ -2703,6 +2731,7 @@ CONFIG_KEYBOARD_GPIO_POLLED=y # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set # CONFIG_KEYBOARD_SAMSUNG is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set @@ -2711,6 +2740,7 @@ CONFIG_KEYBOARD_GPIO_POLLED=y # CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_CAP11XX is not set # CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CYPRESS_SF is not set CONFIG_INPUT_MOUSE=y # CONFIG_MOUSE_PS2 is not set # CONFIG_MOUSE_SERIAL is not set @@ -2782,7 +2812,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_SIFIVE is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set -# CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_XILINX_PS_UART is not set @@ -2801,6 +2830,7 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_NULL_TTY is not set CONFIG_HVC_DRIVER=y # CONFIG_HVC_DCC is not set +# CONFIG_RPMSG_TTY is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y CONFIG_TTY_PRINTK=y @@ -2822,6 +2852,7 @@ CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y CONFIG_RANDOM_TRUST_BOOTLOADER=y # end of Character devices @@ -2896,6 +2927,7 @@ CONFIG_I2C_MESON=y # # CONFIG_I2C_DIOLAN_U2C is not set # CONFIG_I2C_CP2615 is not set +# CONFIG_I2C_PCI1XXXX is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2929,12 +2961,15 @@ CONFIG_SPI_MEM=y CONFIG_SPI_BITBANG=m # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CADENCE_XSPI is not set # CONFIG_SPI_DESIGNWARE is not set # CONFIG_SPI_NXP_FLEXSPI is not set CONFIG_SPI_GPIO=m # CONFIG_SPI_FSL_SPI is not set CONFIG_SPI_MESON_SPICC=y CONFIG_SPI_MESON_SPIFC=y +# CONFIG_SPI_MICROCHIP_CORE is not set +# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PXA2XX is not set # CONFIG_SPI_ROCKCHIP is not set @@ -2993,22 +3028,23 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_MCP23S08 is not set -CONFIG_PINCTRL_SINGLE=y -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_STMFX is not set -# CONFIG_PINCTRL_OCELOT is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_SINGLE=y +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_SX150X is not set +CONFIG_PINCTRL_MESON=y +CONFIG_PINCTRL_MESON8=y +CONFIG_PINCTRL_MESON8B=y +CONFIG_PINCTRL_MESON8_PMX=y # # Renesas pinctrl drivers # # end of Renesas pinctrl drivers -CONFIG_PINCTRL_MESON=y -CONFIG_PINCTRL_MESON8=y -CONFIG_PINCTRL_MESON8B=y -CONFIG_PINCTRL_MESON8_PMX=y CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 @@ -3033,7 +3069,6 @@ CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_MPC8XXX is not set -# CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y # CONFIG_GPIO_XILINX is not set @@ -3044,7 +3079,6 @@ CONFIG_GPIO_SYSCON=y # # I2C GPIO expanders # -# CONFIG_GPIO_ADP5588 is not set # CONFIG_GPIO_ADNP is not set # CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set @@ -3092,6 +3126,7 @@ CONFIG_GPIO_SYSCON=y # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -3115,12 +3150,14 @@ CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_HWMON is not set # CONFIG_PDA_POWER is not set # CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_IP5XXX_POWER is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set # CONFIG_BATTERY_CW2015 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set # CONFIG_CHARGER_SBS is not set # CONFIG_MANAGER_SBS is not set @@ -3135,6 +3172,7 @@ CONFIG_POWER_SUPPLY=y # CONFIG_CHARGER_LT3651 is not set # CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_MAX77976 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -3150,6 +3188,7 @@ CONFIG_POWER_SUPPLY=y # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set +# CONFIG_BATTERY_UG3105 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -3178,7 +3217,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set CONFIG_SENSORS_ARM_SCMI=m -# CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_CORSAIR_PSU is not set @@ -3220,6 +3258,8 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_MAX197 is not set # CONFIG_SENSORS_MAX31722 is not set # CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX31760 is not set +# CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set # CONFIG_SENSORS_MAX6642 is not set @@ -3252,10 +3292,12 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_NTC_THERMISTOR is not set # CONFIG_SENSORS_NCT6683 is not set # CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT6775_I2C is not set # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set @@ -3271,6 +3313,7 @@ CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_EMC1403 is not set # CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC2305 is not set # CONFIG_SENSORS_EMC6W201 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set @@ -3285,6 +3328,7 @@ CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set # CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set @@ -3293,6 +3337,7 @@ CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP464 is not set # CONFIG_SENSORS_TMP513 is not set # CONFIG_SENSORS_VEXPRESS is not set # CONFIG_SENSORS_VIA686A is not set @@ -3408,7 +3453,6 @@ CONFIG_MFD_CORE=m # CONFIG_HTC_I2CPLD is not set # CONFIG_LPC_ICH is not set # CONFIG_LPC_SCH is not set -# CONFIG_MFD_INTEL_PMT is not set # CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set @@ -3420,14 +3464,17 @@ CONFIG_MFD_CORE=m # CONFIG_MFD_MAX77650 is not set # CONFIG_MFD_MAX77686 is not set # CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77714 is not set # CONFIG_MFD_MAX77843 is not set # CONFIG_MFD_MAX8907 is not set # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set # CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6370 is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_OCELOT is not set # CONFIG_EZX_PCAP is not set # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_VIPERBOARD is not set @@ -3435,9 +3482,11 @@ CONFIG_MFD_CORE=m # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_PM8XXX is not set +# CONFIG_MFD_SY7636A is not set # CONFIG_MFD_RDC321X is not set # CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RT5120 is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RK808 is not set # CONFIG_MFD_RN5T618 is not set @@ -3465,7 +3514,6 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_TPS65910 is not set # CONFIG_MFD_TPS65912_I2C is not set # CONFIG_MFD_TPS65912_SPI is not set -# CONFIG_MFD_TPS80031 is not set # CONFIG_TWL4030_CORE is not set # CONFIG_TWL6040_CORE is not set # CONFIG_MFD_WL1273_CORE is not set @@ -3485,7 +3533,6 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set @@ -3529,6 +3576,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set # CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set @@ -3545,6 +3593,8 @@ CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set # CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT5190A is not set +# CONFIG_REGULATOR_RT5759 is not set # CONFIG_REGULATOR_RT6160 is not set # CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTQ2134 is not set @@ -3556,6 +3606,7 @@ CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_SY8827N is not set # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS6286X is not set # CONFIG_REGULATOR_TPS65023 is not set # CONFIG_REGULATOR_TPS6507X is not set # CONFIG_REGULATOR_TPS65132 is not set @@ -3563,50 +3614,55 @@ CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_VCTRL is not set # CONFIG_REGULATOR_VEXPRESS is not set CONFIG_RC_CORE=m -CONFIG_RC_MAP=m CONFIG_LIRC=y +CONFIG_RC_MAP=m CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m CONFIG_IR_NEC_DECODER=m CONFIG_IR_RC5_DECODER=m CONFIG_IR_RC6_DECODER=m -CONFIG_IR_JVC_DECODER=m -CONFIG_IR_SONY_DECODER=m +CONFIG_IR_RCMM_DECODER=m CONFIG_IR_SANYO_DECODER=m CONFIG_IR_SHARP_DECODER=m -CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_SONY_DECODER=m CONFIG_IR_XMP_DECODER=m -CONFIG_IR_IMON_DECODER=m -CONFIG_IR_RCMM_DECODER=m CONFIG_RC_DEVICES=y -CONFIG_RC_ATI_REMOTE=m +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m # CONFIG_IR_HIX5HD2 is not set +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m # CONFIG_IR_IMON is not set # CONFIG_IR_IMON_RAW is not set CONFIG_IR_MCEUSB=m CONFIG_IR_MESON=m CONFIG_IR_MESON_TX=m +# CONFIG_IR_PWM_TX is not set # CONFIG_IR_REDRAT3 is not set +# CONFIG_IR_SERIAL is not set # CONFIG_IR_SPI is not set # CONFIG_IR_STREAMZAP is not set -CONFIG_IR_IGORPLUGUSB=m -CONFIG_IR_IGUANA=m -CONFIG_IR_TTUSBIR=m -# CONFIG_RC_LOOPBACK is not set -CONFIG_IR_GPIO_CIR=m -CONFIG_IR_GPIO_TX=m -# CONFIG_IR_PWM_TX is not set -# CONFIG_IR_SERIAL is not set -# CONFIG_IR_SIR is not set -# CONFIG_RC_XBOX_DVD is not set # CONFIG_IR_TOY is not set +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +# CONFIG_RC_LOOPBACK is not set +# CONFIG_RC_XBOX_DVD is not set CONFIG_CEC_CORE=y CONFIG_CEC_NOTIFIER=y + +# +# CEC support +# CONFIG_MEDIA_CEC_SUPPORT=y # CONFIG_CEC_CH7322 is not set CONFIG_CEC_MESON_AO=y # CONFIG_CEC_MESON_G12A_AO is not set # CONFIG_USB_PULSE8_CEC is not set # CONFIG_USB_RAINSHADOW_CEC is not set +# end of CEC support + CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIA_SUPPORT_FILTER is not set CONFIG_MEDIA_SUBDRV_AUTOSELECT=y @@ -3634,7 +3690,6 @@ CONFIG_DVB_CORE=m # # Video4Linux options # -CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_I2C=y CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_ADV_DEBUG is not set @@ -3643,8 +3698,6 @@ CONFIG_VIDEO_TUNER=m CONFIG_V4L2_MEM2MEM_DEV=m CONFIG_V4L2_FWNODE=m CONFIG_V4L2_ASYNC=m -CONFIG_VIDEOBUF_GEN=m -CONFIG_VIDEOBUF_VMALLOC=m # end of Video4Linux options # @@ -3652,10 +3705,6 @@ CONFIG_VIDEOBUF_VMALLOC=m # CONFIG_MEDIA_CONTROLLER_DVB=y CONFIG_MEDIA_CONTROLLER_REQUEST_API=y - -# -# Please notice that the enabled Media controller Request API is EXPERIMENTAL -# # end of Media controller options # @@ -3669,6 +3718,10 @@ CONFIG_DVB_DYNAMIC_MINORS=y # CONFIG_DVB_ULE_DEBUG is not set # end of Digital TV options +# +# Media drivers +# + # # Media drivers # @@ -3677,12 +3730,7 @@ CONFIG_MEDIA_USB_SUPPORT=y # # Webcam devices # -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_GL860=m CONFIG_USB_GSPCA_BENQ=m CONFIG_USB_GSPCA_CONEX=m CONFIG_USB_GSPCA_CPIA1=m @@ -3707,13 +3755,13 @@ CONFIG_USB_GSPCA_SN9C2028=m CONFIG_USB_GSPCA_SN9C20X=m CONFIG_USB_GSPCA_SONIXB=m CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m CONFIG_USB_GSPCA_SPCA500=m CONFIG_USB_GSPCA_SPCA501=m CONFIG_USB_GSPCA_SPCA505=m CONFIG_USB_GSPCA_SPCA506=m CONFIG_USB_GSPCA_SPCA508=m CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SPCA1528=m CONFIG_USB_GSPCA_SQ905=m CONFIG_USB_GSPCA_SQ905C=m CONFIG_USB_GSPCA_SQ930X=m @@ -3729,29 +3777,31 @@ CONFIG_USB_GSPCA_VC032X=m CONFIG_USB_GSPCA_VICAM=m CONFIG_USB_GSPCA_XIRLINK_CIT=m CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m CONFIG_USB_PWC=m # CONFIG_USB_PWC_DEBUG is not set CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_VIDEO_CPIA2=m -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m CONFIG_USB_S2255=m CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y # # Analog TV USB devices # -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_STK1160_COMMON=m -CONFIG_VIDEO_STK1160=m CONFIG_VIDEO_GO7007=m CONFIG_VIDEO_GO7007_USB=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m # # Analog/digital TV USB devices @@ -3763,41 +3813,13 @@ CONFIG_VIDEO_CX231XX=m CONFIG_VIDEO_CX231XX_RC=y CONFIG_VIDEO_CX231XX_ALSA=m CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_TM6000=m -CONFIG_VIDEO_TM6000_ALSA=m -CONFIG_VIDEO_TM6000_DVB=m # # Digital TV USB devices # -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_DIB3000MC=m -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_CXUSB_ANALOG=y -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_PCTV452E=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AZ6027=m -CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set CONFIG_DVB_USB_V2=m CONFIG_DVB_USB_AF9015=m CONFIG_DVB_USB_AF9035=m @@ -3805,19 +3827,44 @@ CONFIG_DVB_USB_ANYSEE=m CONFIG_DVB_USB_AU6610=m CONFIG_DVB_USB_AZ6007=m CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m CONFIG_DVB_USB_EC168=m CONFIG_DVB_USB_GL861=m CONFIG_DVB_USB_LME2510=m CONFIG_DVB_USB_MXL111SF=m CONFIG_DVB_USB_RTL28XXU=m -CONFIG_DVB_USB_DVBSKY=m CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m CONFIG_DVB_TTUSB_BUDGET=m CONFIG_DVB_TTUSB_DEC=m -CONFIG_SMS_USB_DRV=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set -CONFIG_DVB_AS102=m # # Webcam, TV (analog/digital) USB devices @@ -3835,71 +3882,161 @@ CONFIG_USB_AIRSPY=m CONFIG_USB_HACKRF=m CONFIG_USB_MSI2500=m # CONFIG_MEDIA_PCI_SUPPORT is not set -CONFIG_RADIO_ADAPTERS=y +CONFIG_RADIO_ADAPTERS=m +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SAA7706H is not set +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m CONFIG_RADIO_TEA575X=m +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_USB_RAREMONO=m CONFIG_RADIO_SI470X=m CONFIG_USB_SI470X=m # CONFIG_I2C_SI470X is not set -CONFIG_RADIO_SI4713=m CONFIG_USB_SI4713=m # CONFIG_PLATFORM_SI4713 is not set CONFIG_I2C_SI4713=m -CONFIG_USB_MR800=m -CONFIG_USB_DSBR=m -# CONFIG_RADIO_MAXIRADIO is not set -CONFIG_RADIO_SHARK=m -CONFIG_RADIO_SHARK2=m -CONFIG_USB_KEENE=m -CONFIG_USB_RAREMONO=m -CONFIG_USB_MA901=m -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_SAA7706H is not set -# CONFIG_RADIO_TEF6862 is not set -# CONFIG_RADIO_WL1273 is not set -CONFIG_MEDIA_COMMON_OPTIONS=y - -# -# common driver options -# -CONFIG_VIDEO_CX2341X=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_TTPCI_EEPROM=m -CONFIG_CYPRESS_FIRMWARE=m -CONFIG_VIDEOBUF2_CORE=m -CONFIG_VIDEOBUF2_V4L2=m -CONFIG_VIDEOBUF2_MEMOPS=m -CONFIG_VIDEOBUF2_DMA_CONTIG=m -CONFIG_VIDEOBUF2_VMALLOC=m -CONFIG_VIDEOBUF2_DMA_SG=m -CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_SMS_SIANO_MDTV=m -CONFIG_SMS_SIANO_RC=y -CONFIG_VIDEO_V4L2_TPG=m +CONFIG_MEDIA_PLATFORM_DRIVERS=y CONFIG_V4L_PLATFORM_DRIVERS=y -# CONFIG_VIDEO_CAFE_CCIC is not set -# CONFIG_VIDEO_CADENCE is not set -# CONFIG_VIDEO_ASPEED is not set -CONFIG_VIDEO_MUX=m -# CONFIG_VIDEO_XILINX is not set +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_DVB_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m +CONFIG_VIDEO_MUX=m + +# +# Allegro DVT media platform drivers +# + +# +# Amlogic media platform drivers +# CONFIG_VIDEO_MESON_GE2D=m -CONFIG_DVB_PLATFORM_DRIVERS=y + +# +# Amphion drivers +# + +# +# Aspeed media platform drivers +# +# CONFIG_VIDEO_ASPEED is not set + +# +# Atmel media platform drivers +# + +# +# Cadence media platform drivers +# +# CONFIG_VIDEO_CADENCE_CSI2RX is not set +# CONFIG_VIDEO_CADENCE_CSI2TX is not set + +# +# Chips&Media media platform drivers +# + +# +# Intel media platform drivers +# + +# +# Marvell media platform drivers +# +# CONFIG_VIDEO_CAFE_CCIC is not set + +# +# Mediatek media platform drivers +# + +# +# NVidia media platform drivers +# + +# +# NXP media platform drivers +# + +# +# Qualcomm media platform drivers +# + +# +# Renesas media platform drivers +# + +# +# Rockchip media platform drivers +# + +# +# Samsung media platform drivers +# + +# +# STMicroelectronics media platform drivers +# # CONFIG_DVB_C8SECTPFE is not set -CONFIG_SDR_PLATFORM_DRIVERS=y + +# +# Sunxi media platform drivers +# + +# +# Texas Instruments drivers +# + +# +# Verisilicon media platform drivers +# + +# +# VIA media platform drivers +# + +# +# Xilinx media platform drivers +# +# CONFIG_VIDEO_XILINX is not set # # MMC/SDIO DVB adapters # # CONFIG_SMS_SDIO_DRV is not set CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIMC=m CONFIG_VIDEO_VIVID=m CONFIG_VIDEO_VIVID_CEC=y CONFIG_VIDEO_VIVID_MAX_DEVS=64 -CONFIG_VIDEO_VIM2M=m -CONFIG_VIDEO_VICODEC=m # CONFIG_DVB_TEST_DRIVERS is not set +CONFIG_MEDIA_COMMON_OPTIONS=y + +# +# common driver options +# +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_TTPCI_EEPROM=m +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +CONFIG_VIDEO_V4L2_TPG=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOBUF2_DMA_SG=m # end of Media drivers # @@ -3912,25 +4049,114 @@ CONFIG_MEDIA_ATTACH=y # CONFIG_VIDEO_IR_I2C=m +# +# Camera sensor devices +# +# CONFIG_VIDEO_AR0521 is not set +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_HI846 is not set +# CONFIG_VIDEO_HI847 is not set +# CONFIG_VIDEO_IMX208 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX290 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX334 is not set +# CONFIG_VIDEO_IMX335 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_IMX412 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9T112 is not set +CONFIG_VIDEO_MT9V011=m +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_OG01A1B is not set +# CONFIG_VIDEO_OV02A10 is not set +# CONFIG_VIDEO_OV08D10 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_OV13B10 is not set +CONFIG_VIDEO_OV2640=m +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV5648 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV6650 is not set +# CONFIG_VIDEO_OV7251 is not set +CONFIG_VIDEO_OV7640=m +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8865 is not set +# CONFIG_VIDEO_OV9282 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RDACM21 is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_S5C73M3 is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_ET8EK8 is not set +# CONFIG_VIDEO_M5MOLS is not set +# end of Camera sensor devices + +# +# Lens drivers +# +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9768 is not set +# CONFIG_VIDEO_DW9807_VCM is not set +# end of Lens drivers + +# +# Flash devices +# +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set +# end of Flash devices + # # Audio decoders, processors and mixers # -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA1997X is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -CONFIG_VIDEO_MSP3400=m # CONFIG_VIDEO_CS3308 is not set # CONFIG_VIDEO_CS5345 is not set CONFIG_VIDEO_CS53L32A=m -# CONFIG_VIDEO_TLV320AIC23B is not set -CONFIG_VIDEO_UDA1342=m -CONFIG_VIDEO_WM8775=m -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_VP27SMPX is not set +CONFIG_VIDEO_MSP3400=m CONFIG_VIDEO_SONY_BTF_MPX=m +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_TVAUDIO is not set +CONFIG_VIDEO_UDA1342=m +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_WM8739 is not set +CONFIG_VIDEO_WM8775=m # end of Audio decoders, processors and mixers # @@ -3950,7 +4176,9 @@ CONFIG_VIDEO_SONY_BTF_MPX=m # CONFIG_VIDEO_BT819 is not set # CONFIG_VIDEO_BT856 is not set # CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_ISL7998X is not set # CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_MAX9286 is not set # CONFIG_VIDEO_ML86V7667 is not set # CONFIG_VIDEO_SAA7110 is not set CONFIG_VIDEO_SAA711X=m @@ -3963,7 +4191,6 @@ CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m # CONFIG_VIDEO_TW9910 is not set # CONFIG_VIDEO_VPX3220 is not set -# CONFIG_VIDEO_MAX9286 is not set # # Video and audio decoders @@ -3975,15 +4202,15 @@ CONFIG_VIDEO_CX25840=m # # Video encoders # -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_AD9389B is not set # CONFIG_VIDEO_ADV7170 is not set # CONFIG_VIDEO_ADV7175 is not set # CONFIG_VIDEO_ADV7343 is not set # CONFIG_VIDEO_ADV7393 is not set # CONFIG_VIDEO_ADV7511 is not set -# CONFIG_VIDEO_AD9389B is not set # CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set # CONFIG_VIDEO_THS8200 is not set # end of Video encoders @@ -4009,104 +4236,17 @@ CONFIG_VIDEO_CX25840=m # # Miscellaneous helper chips # -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_ST_MIPID02 is not set +# CONFIG_VIDEO_THS7303 is not set # end of Miscellaneous helper chips -# -# Camera sensor devices -# -# CONFIG_VIDEO_HI556 is not set -# CONFIG_VIDEO_IMX208 is not set -# CONFIG_VIDEO_IMX214 is not set -# CONFIG_VIDEO_IMX219 is not set -# CONFIG_VIDEO_IMX258 is not set -# CONFIG_VIDEO_IMX274 is not set -# CONFIG_VIDEO_IMX290 is not set -# CONFIG_VIDEO_IMX319 is not set -# CONFIG_VIDEO_IMX334 is not set -# CONFIG_VIDEO_IMX335 is not set -# CONFIG_VIDEO_IMX355 is not set -# CONFIG_VIDEO_IMX412 is not set -# CONFIG_VIDEO_OV02A10 is not set -CONFIG_VIDEO_OV2640=m -# CONFIG_VIDEO_OV2659 is not set -# CONFIG_VIDEO_OV2680 is not set -# CONFIG_VIDEO_OV2685 is not set -# CONFIG_VIDEO_OV5640 is not set -# CONFIG_VIDEO_OV5645 is not set -# CONFIG_VIDEO_OV5647 is not set -# CONFIG_VIDEO_OV5648 is not set -# CONFIG_VIDEO_OV6650 is not set -# CONFIG_VIDEO_OV5670 is not set -# CONFIG_VIDEO_OV5675 is not set -# CONFIG_VIDEO_OV5695 is not set -# CONFIG_VIDEO_OV7251 is not set -# CONFIG_VIDEO_OV772X is not set -CONFIG_VIDEO_OV7640=m -# CONFIG_VIDEO_OV7670 is not set -# CONFIG_VIDEO_OV7740 is not set -# CONFIG_VIDEO_OV8856 is not set -# CONFIG_VIDEO_OV8865 is not set -# CONFIG_VIDEO_OV9282 is not set -# CONFIG_VIDEO_OV9640 is not set -# CONFIG_VIDEO_OV9650 is not set -# CONFIG_VIDEO_OV13858 is not set -# CONFIG_VIDEO_VS6624 is not set -# CONFIG_VIDEO_MT9M001 is not set -# CONFIG_VIDEO_MT9M032 is not set -# CONFIG_VIDEO_MT9M111 is not set -# CONFIG_VIDEO_MT9P031 is not set -# CONFIG_VIDEO_MT9T001 is not set -# CONFIG_VIDEO_MT9T112 is not set -CONFIG_VIDEO_MT9V011=m -# CONFIG_VIDEO_MT9V032 is not set -# CONFIG_VIDEO_MT9V111 is not set -# CONFIG_VIDEO_SR030PC30 is not set -# CONFIG_VIDEO_NOON010PC30 is not set -# CONFIG_VIDEO_M5MOLS is not set -# CONFIG_VIDEO_RDACM20 is not set -# CONFIG_VIDEO_RDACM21 is not set -# CONFIG_VIDEO_RJ54N1 is not set -# CONFIG_VIDEO_S5K6AA is not set -# CONFIG_VIDEO_S5K6A3 is not set -# CONFIG_VIDEO_S5K4ECGX is not set -# CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_CCS is not set -# CONFIG_VIDEO_ET8EK8 is not set -# CONFIG_VIDEO_S5C73M3 is not set -# end of Camera sensor devices - -# -# Lens drivers -# -# CONFIG_VIDEO_AD5820 is not set -# CONFIG_VIDEO_AK7375 is not set -# CONFIG_VIDEO_DW9714 is not set -# CONFIG_VIDEO_DW9768 is not set -# CONFIG_VIDEO_DW9807_VCM is not set -# end of Lens drivers - -# -# Flash devices -# -# CONFIG_VIDEO_ADP1653 is not set -# CONFIG_VIDEO_LM3560 is not set -# CONFIG_VIDEO_LM3646 is not set -# end of Flash devices - -# -# SPI helper chips -# -# CONFIG_VIDEO_GS1662 is not set -# end of SPI helper chips - # # Media SPI Adapters # # CONFIG_CXD2880_SPI_DRV is not set +# CONFIG_VIDEO_GS1662 is not set # end of Media SPI Adapters CONFIG_MEDIA_TUNER=m @@ -4114,43 +4254,43 @@ CONFIG_MEDIA_TUNER=m # # Customize TV tuners # -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA18250=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MSI001=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2063=m -CONFIG_MEDIA_TUNER_MT2266=m -# CONFIG_MEDIA_TUNER_MT2131 is not set -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_XC4000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_MEDIA_TUNER_MAX2165=m -CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC0011=m CONFIG_MEDIA_TUNER_FC0012=m CONFIG_MEDIA_TUNER_FC0013=m -CONFIG_MEDIA_TUNER_TDA18212=m -CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC2580=m -# CONFIG_MEDIA_TUNER_M88RS6000T is not set -CONFIG_MEDIA_TUNER_TUA9001=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_TUNER_IT913X=m -CONFIG_MEDIA_TUNER_R820T=m +# CONFIG_MEDIA_TUNER_M88RS6000T is not set +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +# CONFIG_MEDIA_TUNER_MT2131 is not set +CONFIG_MEDIA_TUNER_MT2266=m # CONFIG_MEDIA_TUNER_MXL301RF is not set -CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m # CONFIG_MEDIA_TUNER_QM1D1B0004 is not set +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m # end of Customize TV tuners # @@ -4160,126 +4300,126 @@ CONFIG_MEDIA_TUNER_QM1D1C0042=m # # Multistandard (satellite) frontends # +CONFIG_DVB_M88DS3103=m +# CONFIG_DVB_MXL5XX is not set CONFIG_DVB_STB0899=m CONFIG_DVB_STB6100=m CONFIG_DVB_STV090x=m # CONFIG_DVB_STV0910 is not set CONFIG_DVB_STV6110x=m # CONFIG_DVB_STV6111 is not set -# CONFIG_DVB_MXL5XX is not set -CONFIG_DVB_M88DS3103=m # # Multistandard (cable + terrestrial) frontends # CONFIG_DVB_DRXK=m -CONFIG_DVB_TDA18271C2DD=m -CONFIG_DVB_SI2165=m CONFIG_DVB_MN88472=m CONFIG_DVB_MN88473=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_TDA18271C2DD=m # # DVB-S (satellite) frontends # # CONFIG_DVB_CX24110 is not set -CONFIG_DVB_CX24123=m -CONFIG_DVB_MT312=m -# CONFIG_DVB_ZL10036 is not set -CONFIG_DVB_ZL10039=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_STV6110=m -CONFIG_DVB_STV0900=m -CONFIG_DVB_TDA8083=m -CONFIG_DVB_TDA10086=m -# CONFIG_DVB_TDA8261 is not set -# CONFIG_DVB_VES1X93 is not set -CONFIG_DVB_TUNER_ITD1000=m -CONFIG_DVB_TUNER_CX24113=m -CONFIG_DVB_TDA826X=m -# CONFIG_DVB_TUA6100 is not set CONFIG_DVB_CX24116=m # CONFIG_DVB_CX24117 is not set CONFIG_DVB_CX24120=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_TS2020=m +CONFIG_DVB_CX24123=m CONFIG_DVB_DS3000=m CONFIG_DVB_MB86A16=m +CONFIG_DVB_MT312=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV6110=m CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8083=m +# CONFIG_DVB_TDA8261 is not set +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TS2020=m +# CONFIG_DVB_TUA6100 is not set +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_ITD1000=m +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_ZL10036 is not set +CONFIG_DVB_ZL10039=m # # DVB-T (terrestrial) frontends # -# CONFIG_DVB_SP887X is not set +CONFIG_DVB_AF9013=m +CONFIG_DVB_AS102_FE=m CONFIG_DVB_CX22700=m CONFIG_DVB_CX22702=m -# CONFIG_DVB_S5H1432 is not set -CONFIG_DVB_DRXD=m -# CONFIG_DVB_L64781 is not set -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m CONFIG_DVB_DIB3000MB=m CONFIG_DVB_DIB3000MC=m CONFIG_DVB_DIB7000M=m CONFIG_DVB_DIB7000P=m # CONFIG_DVB_DIB9000 is not set -CONFIG_DVB_TDA10048=m -CONFIG_DVB_AF9013=m +CONFIG_DVB_DRXD=m CONFIG_DVB_EC100=m -# CONFIG_DVB_STV0367 is not set -CONFIG_DVB_CXD2820R=m -CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_GP8PSK_FE=m +# CONFIG_DVB_L64781 is not set +CONFIG_DVB_MT352=m +CONFIG_DVB_NXT6000=m CONFIG_DVB_RTL2830=m CONFIG_DVB_RTL2832=m CONFIG_DVB_RTL2832_SDR=m +# CONFIG_DVB_S5H1432 is not set CONFIG_DVB_SI2168=m -CONFIG_DVB_AS102_FE=m +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_STV0367 is not set +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m CONFIG_DVB_ZD1301_DEMOD=m -CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_ZL10353=m # CONFIG_DVB_CXD2880 is not set # # DVB-C (cable) frontends # -CONFIG_DVB_VES1820=m +CONFIG_DVB_STV0297=m # CONFIG_DVB_TDA10021 is not set CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m +CONFIG_DVB_VES1820=m # # ATSC (North American/Korean Terrestrial/Cable DTV) frontends # -CONFIG_DVB_NXT200X=m -# CONFIG_DVB_OR51211 is not set -# CONFIG_DVB_OR51132 is not set -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_LGDT3306A=m -CONFIG_DVB_LG2160=m -CONFIG_DVB_S5H1409=m CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m -CONFIG_DVB_S5H1411=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m CONFIG_DVB_MXL692=m +CONFIG_DVB_NXT200X=m +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_OR51211 is not set +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m # # ISDB-T (terrestrial) frontends # -CONFIG_DVB_S921=m CONFIG_DVB_DIB8000=m CONFIG_DVB_MB86A20S=m +CONFIG_DVB_S921=m # # ISDB-S (satellite) & ISDB-T (terrestrial) frontends # -CONFIG_DVB_TC90522=m # CONFIG_DVB_MN88443X is not set +CONFIG_DVB_TC90522=m # # Digital terrestrial only tuners/PLL @@ -4291,25 +4431,25 @@ CONFIG_DVB_TUNER_DIB0090=m # # SEC control devices for DVB-S # -CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9033=m +# CONFIG_DVB_ASCOT2E is not set +CONFIG_DVB_ATBM8830=m +# CONFIG_DVB_HELENE is not set +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ISL6405 is not set +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +# CONFIG_DVB_LGS8GL5 is not set +CONFIG_DVB_LGS8GXX=m # CONFIG_DVB_LNBH25 is not set # CONFIG_DVB_LNBH29 is not set CONFIG_DVB_LNBP21=m CONFIG_DVB_LNBP22=m -# CONFIG_DVB_ISL6405 is not set -CONFIG_DVB_ISL6421=m -CONFIG_DVB_ISL6423=m -CONFIG_DVB_A8293=m -# CONFIG_DVB_LGS8GL5 is not set -CONFIG_DVB_LGS8GXX=m -CONFIG_DVB_ATBM8830=m -# CONFIG_DVB_TDA665x is not set -CONFIG_DVB_IX2505V=m CONFIG_DVB_M88RS2000=m -CONFIG_DVB_AF9033=m -# CONFIG_DVB_HORUS3A is not set -# CONFIG_DVB_ASCOT2E is not set -# CONFIG_DVB_HELENE is not set +# CONFIG_DVB_TDA665x is not set +CONFIG_DVB_DRX39XYJ=m # # Common Interface (EN50221) controller drivers @@ -4327,21 +4467,22 @@ CONFIG_DVB_SP2=m # # Graphics support # -# CONFIG_VGA_ARB is not set +CONFIG_APERTURE_HELPERS=y # CONFIG_IMX_IPUV3_CORE is not set CONFIG_DRM=y -# CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DEBUG_MM is not set -# CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +CONFIG_DRM_DISPLAY_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DP_CEC is not set -CONFIG_DRM_GEM_CMA_HELPER=y -CONFIG_DRM_KMS_CMA_HELPER=y +CONFIG_DRM_GEM_DMA_HELPER=y CONFIG_DRM_GEM_SHMEM_HELPER=y CONFIG_DRM_SCHED=y @@ -4373,7 +4514,8 @@ CONFIG_DRM_MALI_DISPLAY=y # CONFIG_DRM_MGAG200 is not set # CONFIG_DRM_ARMADA is not set # CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set # CONFIG_DRM_OMAP is not set # CONFIG_DRM_TILCDC is not set # CONFIG_DRM_QXL is not set @@ -4388,6 +4530,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_EDP is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -4395,10 +4538,12 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set # CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set @@ -4422,7 +4567,9 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_CHIPONE_ICN6211 is not set # CONFIG_DRM_CHRONTEL_CH7033 is not set CONFIG_DRM_DISPLAY_CONNECTOR=y +# CONFIG_DRM_ITE_IT6505 is not set # CONFIG_DRM_LONTIUM_LT8912B is not set +# CONFIG_DRM_LONTIUM_LT9211 is not set # CONFIG_DRM_LONTIUM_LT9611 is not set # CONFIG_DRM_LONTIUM_LT9611UXC is not set # CONFIG_DRM_ITE_IT66121 is not set @@ -4442,6 +4589,7 @@ CONFIG_DRM_DISPLAY_CONNECTOR=y # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set @@ -4454,12 +4602,15 @@ CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_DW_HDMI=y # CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set # CONFIG_DRM_DW_HDMI_I2S_AUDIO is not set +# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set # CONFIG_DRM_DW_HDMI_CEC is not set # end of Display Interface Bridges # CONFIG_DRM_STI is not set # CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_IMX_LCDIF is not set CONFIG_DRM_MESON=y CONFIG_DRM_MESON_DW_HDMI=y CONFIG_DRM_MESON_TRANSWITCH_HDMI=y @@ -4467,8 +4618,10 @@ CONFIG_DRM_MESON_TRANSWITCH_HDMI=y # CONFIG_DRM_BOCHS is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_PANEL_MIPI_DBI is not set # CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set # CONFIG_TINYDRM_ILI9486 is not set @@ -4483,8 +4636,10 @@ CONFIG_DRM_LIMA=y # CONFIG_DRM_MCDE is not set # CONFIG_DRM_TIDSS is not set # CONFIG_DRM_GUD is not set +# CONFIG_DRM_SSD130X is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -4603,7 +4758,9 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set CONFIG_SND_VMASTER=y # CONFIG_SND_SEQUENCER is not set CONFIG_SND_DRIVERS=y @@ -4611,6 +4768,7 @@ CONFIG_SND_DRIVERS=y # CONFIG_SND_ALOOP is not set # CONFIG_SND_MTPAV is not set # CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_SERIAL_GENERIC is not set # CONFIG_SND_MPU401 is not set # CONFIG_SND_PCI is not set @@ -4639,6 +4797,7 @@ CONFIG_SND_USB_VARIAX=m CONFIG_SND_SOC=m # CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -4712,6 +4871,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=m # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set @@ -4719,6 +4879,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=m # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set # CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AW8738 is not set # CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set # CONFIG_SND_SOC_CS35L32 is not set @@ -4726,11 +4887,16 @@ CONFIG_SND_SOC_I2C_AND_SPI=m # CONFIG_SND_SOC_CS35L34 is not set # CONFIG_SND_SOC_CS35L35 is not set # CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS35L41_SPI is not set +# CONFIG_SND_SOC_CS35L41_I2C is not set +# CONFIG_SND_SOC_CS35L45_SPI is not set +# CONFIG_SND_SOC_CS35L45_I2C is not set # CONFIG_SND_SOC_CS42L42 is not set # CONFIG_SND_SOC_CS42L51_I2C is not set # CONFIG_SND_SOC_CS42L52 is not set # CONFIG_SND_SOC_CS42L56 is not set # CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42L83 is not set # CONFIG_SND_SOC_CS4234 is not set # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set @@ -4748,9 +4914,11 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set # CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set @@ -4758,8 +4926,10 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_MAX98504 is not set # CONFIG_SND_SOC_MAX9867 is not set # CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98520 is not set # CONFIG_SND_SOC_MAX98373_I2C is not set # CONFIG_SND_SOC_MAX98390 is not set +# CONFIG_SND_SOC_MAX98396 is not set # CONFIG_SND_SOC_MAX9860 is not set # CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set # CONFIG_SND_SOC_PCM1681 is not set @@ -4780,10 +4950,12 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5640 is not set # CONFIG_SND_SOC_RT5659 is not set +# CONFIG_SND_SOC_RT9120 is not set # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set # CONFIG_SND_SOC_SIMPLE_MUX is not set # CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SRC4XXX_I2C is not set # CONFIG_SND_SOC_SSM2305 is not set # CONFIG_SND_SOC_SSM2518 is not set # CONFIG_SND_SOC_SSM2602_SPI is not set @@ -4796,13 +4968,16 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_TAS2562 is not set # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS5805M is not set # CONFIG_SND_SOC_TAS6424 is not set # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set @@ -4821,7 +4996,8 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_WM8580 is not set # CONFIG_SND_SOC_WM8711 is not set # CONFIG_SND_SOC_WM8728 is not set -# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8731_I2C is not set +# CONFIG_SND_SOC_WM8731_SPI is not set # CONFIG_SND_SOC_WM8737 is not set # CONFIG_SND_SOC_WM8741 is not set # CONFIG_SND_SOC_WM8750 is not set @@ -4833,6 +5009,7 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_WM8804_SPI is not set # CONFIG_SND_SOC_WM8903 is not set # CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8940 is not set # CONFIG_SND_SOC_WM8960 is not set # CONFIG_SND_SOC_WM8962 is not set # CONFIG_SND_SOC_WM8974 is not set @@ -4846,6 +5023,7 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set # CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8821 is not set # CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set @@ -4858,6 +5036,8 @@ CONFIG_SND_SOC_HDMI_CODEC=m CONFIG_SND_SIMPLE_CARD_UTILS=m CONFIG_SND_SIMPLE_CARD=m CONFIG_SND_AUDIO_GRAPH_CARD=m +# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set +# CONFIG_SND_TEST_COMPONENT is not set # CONFIG_SND_VIRTIO is not set # @@ -4908,6 +5088,8 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_UCLOGIC is not set # CONFIG_HID_WALTOP is not set # CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_VRC2 is not set +# CONFIG_HID_XIAOMI is not set # CONFIG_HID_GYRATION is not set # CONFIG_HID_ICADE is not set # CONFIG_HID_ITE is not set @@ -4917,14 +5099,17 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_LCPOWER is not set # CONFIG_HID_LED is not set # CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set # CONFIG_HID_LOGITECH is not set # CONFIG_HID_MAGICMOUSE is not set # CONFIG_HID_MALTRON is not set # CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_MEGAWORLD_FF is not set # CONFIG_HID_REDRAGON is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set # CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NINTENDO is not set # CONFIG_HID_NTI is not set # CONFIG_HID_NTRIG is not set # CONFIG_HID_ORTEK is not set @@ -4933,13 +5118,15 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_PETALYNX is not set # CONFIG_HID_PICOLCD is not set # CONFIG_HID_PLANTRONICS is not set -# CONFIG_HID_PLAYSTATION is not set +# CONFIG_HID_PXRC is not set +# CONFIG_HID_RAZER is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set # CONFIG_HID_SAMSUNG is not set # CONFIG_HID_SEMITEK is not set +# CONFIG_HID_SIGMAMICRO is not set # CONFIG_HID_SONY is not set # CONFIG_HID_SPEEDLINK is not set # CONFIG_HID_STEAM is not set @@ -4950,6 +5137,7 @@ CONFIG_HID_GENERIC=y # CONFIG_HID_SMARTJOYPLUS is not set # CONFIG_HID_TIVO is not set # CONFIG_HID_TOPSEED is not set +# CONFIG_HID_TOPRE is not set # CONFIG_HID_THINGM is not set # CONFIG_HID_THRUSTMASTER is not set # CONFIG_HID_UDRAW_PS3 is not set @@ -4976,6 +5164,7 @@ CONFIG_USB_HID=y # I2C HID support # # CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -5175,6 +5364,7 @@ CONFIG_USB_EZUSB_FX2=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set # CONFIG_USB_ATM is not set # @@ -5322,6 +5512,7 @@ CONFIG_MMC_CQHCI=y CONFIG_MMC_HSQ=m # CONFIG_MMC_TOSHIBA_PCI is not set # CONFIG_MMC_MTK is not set +# CONFIG_SCSI_UFSHCD is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y @@ -5376,6 +5567,10 @@ CONFIG_LEDS_PWM=y # Flash and Torch LED drivers # +# +# RGB LED drivers +# + # # LED Triggers # @@ -5400,6 +5595,10 @@ CONFIG_LEDS_TRIGGER_NETDEV=y CONFIG_LEDS_TRIGGER_PATTERN=y CONFIG_LEDS_TRIGGER_AUDIO=y CONFIG_LEDS_TRIGGER_TTY=y + +# +# Simple LED drivers +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -5436,6 +5635,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_ISL12022 is not set @@ -5567,6 +5767,7 @@ CONFIG_SYNC_FILE=y # CONFIG_UIO is not set # CONFIG_VFIO is not set # CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=y # CONFIG_VIRTIO_MENU is not set # CONFIG_VDPA is not set @@ -5595,7 +5796,7 @@ CONFIG_COMMON_CLK=y # # Clock driver for ARM Reference designs # -# CONFIG_ICST is not set +# CONFIG_CLK_ICST is not set # CONFIG_CLK_SP810 is not set # CONFIG_CLK_VEXPRESS_OSC is not set # end of Clock driver for ARM Reference designs @@ -5613,7 +5814,9 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_CS2000_CP is not set # CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_RS9_PCIE is not set # CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_VC7 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set # @@ -5626,6 +5829,7 @@ CONFIG_COMMON_CLK_MESON8B=y # end of Clock support for Amlogic platforms # CONFIG_XILINX_VCU is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set CONFIG_HWSPINLOCK=y # @@ -5666,6 +5870,7 @@ CONFIG_IOMMU_DEBUGFS=y # CONFIG_REMOTEPROC=y CONFIG_REMOTEPROC_CDEV=y +CONFIG_MESON_MX_AO_ARC_REMOTEPROC=y # end of Remoteproc drivers # @@ -5673,6 +5878,7 @@ CONFIG_REMOTEPROC_CDEV=y # CONFIG_RPMSG=m # CONFIG_RPMSG_CHAR is not set +# CONFIG_RPMSG_CTRL is not set CONFIG_RPMSG_NS=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set CONFIG_RPMSG_VIRTIO=m @@ -5707,6 +5913,11 @@ CONFIG_MESON_MX_SOCINFO=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -5759,7 +5970,6 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y -# CONFIG_EXTCON_USBC_TUSB320 is not set CONFIG_MEMORY=y CONFIG_IIO=y CONFIG_IIO_BUFFER=y @@ -5781,8 +5991,14 @@ CONFIG_IIO_TRIGGERED_EVENT=m # # CONFIG_ADIS16201 is not set # CONFIG_ADIS16209 is not set +# CONFIG_ADXL313_I2C is not set +# CONFIG_ADXL313_SPI is not set # CONFIG_ADXL345_I2C is not set # CONFIG_ADXL345_SPI is not set +# CONFIG_ADXL355_I2C is not set +# CONFIG_ADXL355_SPI is not set +# CONFIG_ADXL367_SPI is not set +# CONFIG_ADXL367_I2C is not set # CONFIG_ADXL372_SPI is not set # CONFIG_ADXL372_I2C is not set # CONFIG_BMA180 is not set @@ -5807,6 +6023,7 @@ CONFIG_IIO_TRIGGERED_EVENT=m # CONFIG_MMA8452 is not set # CONFIG_MMA9551 is not set # CONFIG_MMA9553 is not set +# CONFIG_MSA311 is not set # CONFIG_MXC4005 is not set # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set @@ -5822,6 +6039,7 @@ CONFIG_IIO_TRIGGERED_EVENT=m # CONFIG_AD7124 is not set # CONFIG_AD7192 is not set # CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set # CONFIG_AD7291 is not set # CONFIG_AD7292 is not set # CONFIG_AD7298 is not set @@ -5850,6 +6068,7 @@ CONFIG_IIO_TRIGGERED_EVENT=m # CONFIG_MAX1027 is not set # CONFIG_MAX11100 is not set # CONFIG_MAX1118 is not set +# CONFIG_MAX11205 is not set # CONFIG_MAX1241 is not set # CONFIG_MAX1363 is not set # CONFIG_MAX9611 is not set @@ -5858,6 +6077,7 @@ CONFIG_IIO_TRIGGERED_EVENT=m # CONFIG_MCP3911 is not set CONFIG_MESON_SARADC=m # CONFIG_NAU7802 is not set +# CONFIG_RICHTEK_RTQ6056 is not set # CONFIG_SD_ADC_MODULATOR is not set # CONFIG_TI_ADC081C is not set # CONFIG_TI_ADC0832 is not set @@ -5878,6 +6098,12 @@ CONFIG_MESON_SARADC=m # CONFIG_XILINX_XADC is not set # end of Analog to digital converters +# +# Analog to digital and digital to analog converters +# +# CONFIG_AD74413R is not set +# end of Analog to digital and digital to analog converters + # # Analog Front Ends # @@ -5888,6 +6114,7 @@ CONFIG_MESON_SARADC=m # Amplifiers # # CONFIG_AD8366 is not set +# CONFIG_ADA4250 is not set # CONFIG_HMC425 is not set # end of Amplifiers @@ -5895,6 +6122,7 @@ CONFIG_MESON_SARADC=m # Capacitance to digital converters # # CONFIG_AD7150 is not set +# CONFIG_AD7746 is not set # end of Capacitance to digital converters # @@ -5907,10 +6135,12 @@ CONFIG_MESON_SARADC=m # CONFIG_IAQCORE is not set # CONFIG_PMS7003 is not set # CONFIG_SCD30_CORE is not set +# CONFIG_SCD4X is not set # CONFIG_SENSIRION_SGP30 is not set # CONFIG_SENSIRION_SGP40 is not set # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set +# CONFIG_SENSEAIR_SUNRISE_CO2 is not set # CONFIG_VZ89X is not set # end of Chemical Sensors @@ -5934,6 +6164,7 @@ CONFIG_MESON_SARADC=m # # Digital to analog converters # +# CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set @@ -5944,6 +6175,7 @@ CONFIG_MESON_SARADC=m # CONFIG_AD5593R is not set # CONFIG_AD5504 is not set # CONFIG_AD5624R_SPI is not set +# CONFIG_LTC2688 is not set # CONFIG_AD5686_SPI is not set # CONFIG_AD5696_I2C is not set # CONFIG_AD5755 is not set @@ -5953,6 +6185,7 @@ CONFIG_MESON_SARADC=m # CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set +# CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set @@ -5976,6 +6209,11 @@ CONFIG_MESON_SARADC=m # # end of IIO dummy driver +# +# Filters +# +# end of Filters + # # Frequency Synthesizers DDS/PLL # @@ -5991,6 +6229,9 @@ CONFIG_MESON_SARADC=m # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADMV1013 is not set +# CONFIG_ADMV4420 is not set +# CONFIG_ADRF6780 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -6047,6 +6288,8 @@ CONFIG_MPU3050_I2C=y # CONFIG_ADIS16480 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set +# CONFIG_BOSCH_BNO055_SERIAL is not set +# CONFIG_BOSCH_BNO055_I2C is not set # CONFIG_FXOS8700_I2C is not set # CONFIG_FXOS8700_SPI is not set # CONFIG_KMX61 is not set @@ -6083,6 +6326,7 @@ CONFIG_MPU3050_I2C=y # CONFIG_JSA1212 is not set # CONFIG_RPR0521 is not set # CONFIG_LTR501 is not set +# CONFIG_LTRF216A is not set # CONFIG_LV0104CS is not set # CONFIG_MAX44000 is not set # CONFIG_MAX44009 is not set @@ -6210,6 +6454,8 @@ CONFIG_IIO_HRTIMER_TRIGGER=y # CONFIG_RFD77402 is not set # CONFIG_SRF04 is not set # CONFIG_SX9310 is not set +# CONFIG_SX9324 is not set +# CONFIG_SX9360 is not set # CONFIG_SX9500 is not set # CONFIG_SRF08 is not set # CONFIG_VCNL3020 is not set @@ -6236,18 +6482,20 @@ CONFIG_IIO_HRTIMER_TRIGGER=y # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set # CONFIG_MAX31856 is not set +# CONFIG_MAX31865 is not set # end of Temperature sensors # CONFIG_NTB is not set -# CONFIG_VME_BUS is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set CONFIG_PWM_MESON=y # CONFIG_PWM_PCA9685 is not set +# CONFIG_PWM_XILINX is not set # # IRQ chip support @@ -6256,6 +6504,7 @@ CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 # CONFIG_AL_FIC is not set +# CONFIG_XILINX_INTC is not set CONFIG_MESON_IRQ_GPIO=y # end of IRQ chip support @@ -6264,7 +6513,9 @@ CONFIG_RESET_CONTROLLER=y CONFIG_RESET_MESON=y CONFIG_RESET_MESON_AUDIO_ARB=m CONFIG_RESET_SCMI=m +# CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set # # PHY Subsystem @@ -6275,20 +6526,27 @@ CONFIG_PHY_MESON8_HDMI_TX=y CONFIG_PHY_MESON8B_USB2=y CONFIG_PHY_MESON_CVBS_DAC=y # CONFIG_PHY_MESON_GXL_USB2 is not set +# CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG is not set # CONFIG_PHY_MESON_G12A_USB2 is not set # CONFIG_PHY_MESON_G12A_USB3_PCIE is not set # CONFIG_PHY_MESON_AXG_PCIE is not set # CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG is not set # CONFIG_PHY_MESON_AXG_MIPI_DPHY is not set + +# +# PHY drivers for Broadcom platforms +# # CONFIG_BCM_KONA_USB2_PHY is not set +# end of PHY drivers for Broadcom platforms + # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_DPHY_RX is not set # CONFIG_PHY_CADENCE_SIERRA is not set # CONFIG_PHY_CADENCE_SALVO is not set -# CONFIG_PHY_FSL_IMX8MQ_USB is not set -# CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set @@ -6315,13 +6573,13 @@ CONFIG_RAS=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android CONFIG_DAX=m CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y -CONFIG_MESON_MX_EFUSE=y +CONFIG_NVMEM_MESON_MX_EFUSE=y CONFIG_NVMEM_RMEM=m # @@ -6355,6 +6613,8 @@ CONFIG_COUNTER=m # CONFIG_MICROCHIP_TCB_CAPTURE is not set # CONFIG_INTEL_QEP is not set # CONFIG_MOST is not set +# CONFIG_PECI is not set +# CONFIG_HTE is not set # end of Device Drivers # @@ -6427,6 +6687,7 @@ CONFIG_F2FS_FS_LZ4=y CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y CONFIG_F2FS_IOSTAT=y +# CONFIG_F2FS_UNFAIR_RWSEM is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y CONFIG_EXPORTFS_BLOCK_OPS=y @@ -6469,6 +6730,8 @@ CONFIG_FSCACHE_STATS=y # CONFIG_FSCACHE_DEBUG is not set CONFIG_CACHEFILES=y # CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_ERROR_INJECTION is not set +# CONFIG_CACHEFILES_ONDEMAND is not set # end of Caches # @@ -6592,7 +6855,7 @@ CONFIG_EROFS_FS_XATTR=y CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_ZIP=y -# CONFIG_AUFS_FS is not set +CONFIG_EROFS_FS_ZIP_LZMA=y CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y @@ -6616,7 +6879,6 @@ CONFIG_NFS_DISABLE_UDP_SUPPORT=y CONFIG_NFS_V4_2_READ_PLUS=y CONFIG_NFSD=m CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_PNFS=y @@ -6713,6 +6975,7 @@ CONFIG_NLS_MAC_ROMANIAN=m CONFIG_NLS_MAC_TURKISH=m CONFIG_NLS_UTF8=y CONFIG_DLM=y +# CONFIG_DLM_DEPRECATED_API is not set # CONFIG_DLM_DEBUG is not set CONFIG_UNICODE=y # CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set @@ -6725,6 +6988,7 @@ CONFIG_IO_WQ=y CONFIG_KEYS=y # CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_TRUSTED_KEYS is not set # CONFIG_ENCRYPTED_KEYS is not set # CONFIG_KEY_DH_OPERATIONS is not set # CONFIG_KEY_NOTIFICATIONS is not set @@ -6752,6 +7016,10 @@ CONFIG_INIT_STACK_NONE=y # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set # end of Memory initialization + +CONFIG_RANDSTRUCT_NONE=y +# CONFIG_RANDSTRUCT_FULL is not set +# CONFIG_RANDSTRUCT_PERFORMANCE is not set # end of Kernel hardening options # end of Security options @@ -6794,84 +7062,29 @@ CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_SIMD=m +# end of Crypto core or helper # # Public-key cryptography # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m CONFIG_CRYPTO_ECDSA=m CONFIG_CRYPTO_ECRDSA=m CONFIG_CRYPTO_SM2=m CONFIG_CRYPTO_CURVE25519=m +# end of Public-key cryptography # -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_CHACHA20POLY1305=m -CONFIG_CRYPTO_AEGIS128=m -CONFIG_CRYPTO_AEGIS128_SIMD=y -CONFIG_CRYPTO_SEQIV=m -CONFIG_CRYPTO_ECHAINIV=m - -# -# Block modes -# -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_CFB=m -CONFIG_CRYPTO_CTR=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_OFB=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_KEYWRAP=m -CONFIG_CRYPTO_NHPOLY1305=m -CONFIG_CRYPTO_ADIANTUM=m -CONFIG_CRYPTO_ESSIV=m - -# -# Hash modes -# -CONFIG_CRYPTO_CMAC=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_VMAC=m - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_XXHASH=y -CONFIG_CRYPTO_BLAKE2B=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_GHASH=m -CONFIG_CRYPTO_POLY1305=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_SHA3=m -CONFIG_CRYPTO_SM3=m -CONFIG_CRYPTO_STREEBOG=m -CONFIG_CRYPTO_WP512=m - -# -# Ciphers +# Block ciphers # CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_AES_TI=m CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_ARIA=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_BLOWFISH_COMMON=m CONFIG_CRYPTO_CAMELLIA=m @@ -6881,13 +7094,83 @@ CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_GENERIC=m CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_TWOFISH_COMMON=m +# end of Block ciphers + +# +# Length-preserving ciphers and modes +# +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XCTR=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_NHPOLY1305=m +# end of Length-preserving ciphers and modes + +# +# AEAD (authenticated encryption with associated data) ciphers +# +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_AEGIS128_SIMD=y +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ESSIV=m +# end of AEAD (authenticated encryption with associated data) ciphers + +# +# Hashes, digests, and MACs +# +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_POLYVAL=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_SM3_GENERIC=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XXHASH=y +# end of Hashes, digests, and MACs + +# +# CRCs (cyclic redundancy checks) +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +# end of CRCs (cyclic redundancy checks) # # Compression @@ -6898,9 +7181,10 @@ CONFIG_CRYPTO_842=m CONFIG_CRYPTO_LZ4=m CONFIG_CRYPTO_LZ4HC=m CONFIG_CRYPTO_ZSTD=y +# end of Compression # -# Random Number Generation +# Random number generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=m @@ -6909,6 +7193,11 @@ CONFIG_CRYPTO_DRBG_HASH=y CONFIG_CRYPTO_DRBG_CTR=y CONFIG_CRYPTO_DRBG=m CONFIG_CRYPTO_JITTERENTROPY=m +# end of Random number generation + +# +# Userspace interface +# CONFIG_CRYPTO_USER_API=m CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m @@ -6917,7 +7206,33 @@ CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_STATS=y +# end of Userspace interface + CONFIG_CRYPTO_HASH_INFO=y + +# +# Accelerated Cryptographic Algorithms for CPU (arm) +# +CONFIG_CRYPTO_CURVE25519_NEON=m +CONFIG_CRYPTO_GHASH_ARM_CE=m +CONFIG_CRYPTO_NHPOLY1305_NEON=m +CONFIG_CRYPTO_POLY1305_ARM=m +CONFIG_CRYPTO_BLAKE2S_ARM=y +CONFIG_CRYPTO_BLAKE2B_NEON=m +CONFIG_CRYPTO_SHA1_ARM=m +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA1_ARM_CE=m +CONFIG_CRYPTO_SHA2_ARM_CE=m +CONFIG_CRYPTO_SHA256_ARM=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +CONFIG_CRYPTO_AES_ARM_CE=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_CRC32_ARM_CE=m +CONFIG_CRYPTO_CRCT10DIF_ARM_CE=m +# end of Accelerated Cryptographic Algorithms for CPU (arm) + # CONFIG_CRYPTO_HW is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y @@ -6926,6 +7241,7 @@ CONFIG_PKCS8_PRIVATE_KEY_PARSER=m CONFIG_PKCS7_MESSAGE_PARSER=y # CONFIG_PKCS7_TEST_KEY is not set CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set # # Certificates for signature checking @@ -6941,6 +7257,7 @@ CONFIG_SECONDARY_TRUSTED_KEYRING=y CONFIG_SYSTEM_BLACKLIST_KEYRING=y CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" # CONFIG_SYSTEM_REVOCATION_LIST is not set +# CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE is not set # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y @@ -6966,6 +7283,7 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # # Crypto library routines # +CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=m CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y @@ -6981,14 +7299,14 @@ CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_SM4=m # end of Crypto library routines -CONFIG_LIB_MEMNEQ=y CONFIG_CRC_CCITT=m CONFIG_CRC16=y CONFIG_CRC_T10DIF=y +CONFIG_CRC64_ROCKSOFT=y CONFIG_CRC_ITU_T=y CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set @@ -7013,6 +7331,7 @@ CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=y CONFIG_LZ4HC_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y @@ -7022,6 +7341,7 @@ CONFIG_XZ_DEC_IA64=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_DECOMPRESS_GZIP=y @@ -7039,6 +7359,7 @@ CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m CONFIG_TEXTSEARCH_FSM=m +CONFIG_XARRAY_MULTI=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y @@ -7048,8 +7369,9 @@ CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_DMA_NONCOHERENT_MMAP=y -CONFIG_DMA_REMAP=y CONFIG_DMA_CMA=y # CONFIG_DMA_PERNUMA_CMA is not set @@ -7065,6 +7387,7 @@ CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y +# CONFIG_FORCE_NR_CPUS is not set CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y @@ -7085,6 +7408,7 @@ CONFIG_FONT_SUPPORT=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_SG_POOL=y +CONFIG_STACKDEPOT=y CONFIG_SBITMAP=y # end of Library routines @@ -7110,10 +7434,17 @@ CONFIG_SYMBOLIC_ERRNAME=y CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + # # Compile-time checks and compiler options # -# CONFIG_DEBUG_INFO is not set +CONFIG_AS_HAS_NON_CONST_LEB128=y +CONFIG_DEBUG_INFO_NONE=y +# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -7140,22 +7471,28 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_UBSAN is not set # end of Generic Kernel Debugging Instruments -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MISC=y +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set +# end of Networking Debugging # # Memory Debugging # # CONFIG_PAGE_EXTENSION is not set # CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_PAGE_REF is not set # CONFIG_DEBUG_RODATA_TEST is not set # CONFIG_DEBUG_WX is not set # CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -7168,9 +7505,12 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -7229,6 +7569,7 @@ CONFIG_STACKTRACE=y # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_DEBUG_MAPLE_TREE is not set # end of Debug kernel data structures # CONFIG_DEBUG_CREDENTIALS is not set @@ -7240,6 +7581,7 @@ CONFIG_STACKTRACE=y # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 CONFIG_RCU_TRACE=y # CONFIG_RCU_EQS_DEBUG is not set # end of RCU Debugging @@ -7255,6 +7597,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y @@ -7292,6 +7635,7 @@ CONFIG_PROBE_EVENTS=y # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set # CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_RV is not set # CONFIG_SAMPLES is not set # CONFIG_STRICT_DEVMEM is not set @@ -7302,6 +7646,7 @@ CONFIG_PROBE_EVENTS=y # CONFIG_UNWINDER_FRAME_POINTER is not set CONFIG_UNWINDER_ARM=y CONFIG_ARM_UNWIND=y +# CONFIG_BACKTRACE_VERBOSE is not set # CONFIG_DEBUG_USER is not set # CONFIG_DEBUG_LL is not set CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" @@ -7324,8 +7669,8 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_DIV64 is not set -# CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set @@ -7342,9 +7687,9 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set # CONFIG_TEST_XARRAY is not set -# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_MAPLE_TREE is not set # CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set +# CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set # CONFIG_TEST_BITOPS is not set @@ -7359,10 +7704,14 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_STATIC_KEYS is not set # CONFIG_TEST_KMOD is not set # CONFIG_TEST_MEMCAT_P is not set -# CONFIG_TEST_STACKINIT is not set # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage + +# +# Rust hacking +# +# end of Rust hacking # end of Kernel hacking diff --git a/config/kernel/linux-meson-edge.config b/config/kernel/linux-meson-edge.config index 2aecdbf03..0d7355445 100644 --- a/config/kernel/linux-meson-edge.config +++ b/config/kernel/linux-meson-edge.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 6.1.0 Kernel Configuration +# Linux/arm 6.2.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0" CONFIG_CC_IS_GCC=y @@ -66,7 +66,6 @@ CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_IRQ_IPI=y CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set @@ -137,6 +136,7 @@ CONFIG_TREE_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y +CONFIG_NEED_SRCU_NMI_SAFE=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y @@ -159,6 +159,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y # end of Scheduler features CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_GCC11_NO_ARRAY_BOUNDS=y CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y @@ -207,6 +208,7 @@ CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_EXPERT=y @@ -232,6 +234,7 @@ CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_SELFTEST is not set # CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y @@ -445,7 +448,6 @@ CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_NR_CPUS=16 CONFIG_HOTPLUG_CPU=y CONFIG_ARM_PSCI=y -CONFIG_ARCH_NR_GPIO=0 CONFIG_HZ_FIXED=0 CONFIG_HZ_100=y # CONFIG_HZ_200 is not set @@ -608,6 +610,7 @@ CONFIG_KRETPROBES=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y @@ -678,6 +681,7 @@ CONFIG_HAVE_GCC_PLUGINS=y CONFIG_GCC_PLUGINS=y # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set CONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK=y +CONFIG_FUNCTION_ALIGNMENT=0 # end of General architecture-dependent options CONFIG_RT_MUTEXES=y @@ -808,7 +812,8 @@ CONFIG_ZSMALLOC=m # # CONFIG_SLAB is not set CONFIG_SLUB=y -# CONFIG_SLOB is not set +# CONFIG_SLOB_DEPRECATED is not set +# CONFIG_SLUB_TINY is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set @@ -1045,6 +1050,7 @@ CONFIG_NF_NAT_SIP=m CONFIG_NF_NAT_TFTP=m CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_NAT_OVS=y CONFIG_NETFILTER_SYNPROXY=m CONFIG_NF_TABLES=m CONFIG_NF_TABLES_INET=y @@ -1059,7 +1065,6 @@ CONFIG_NFT_MASQ=m CONFIG_NFT_REDIR=m CONFIG_NFT_NAT=m CONFIG_NFT_TUNNEL=m -CONFIG_NFT_OBJREF=m CONFIG_NFT_QUEUE=m CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m @@ -1595,6 +1600,7 @@ CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m CONFIG_BT_HS=y CONFIG_BT_LE=y +CONFIG_BT_LE_L2CAP_ECRED=y CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y CONFIG_BT_MSFTEXT=y @@ -1613,6 +1619,7 @@ CONFIG_BT_QCA=m CONFIG_BT_MTK=m CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_POLL_SYNC=y CONFIG_BT_HCIBTUSB_BCM=y CONFIG_BT_HCIBTUSB_MTK=y CONFIG_BT_HCIBTUSB_RTL=y @@ -1632,6 +1639,7 @@ CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_AG6XX=y CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_HCIBCM203X=m +# CONFIG_BT_HCIBCM4377 is not set CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIVHCI=m @@ -1648,6 +1656,7 @@ CONFIG_AF_RXRPC_IPV6=y CONFIG_AF_RXRPC_INJECT_LOSS=y CONFIG_AF_RXRPC_DEBUG=y CONFIG_RXKAD=y +# CONFIG_RXPERF is not set # CONFIG_AF_KCM is not set CONFIG_STREAM_PARSER=y # CONFIG_MCTP is not set @@ -1715,7 +1724,6 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEASPM is not set # CONFIG_PCIE_PTM is not set CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_QUIRKS=y # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set @@ -1875,7 +1883,6 @@ CONFIG_EFI_PARAMS_FROM_FDT=y CONFIG_EFI_RUNTIME_WRAPPERS=y CONFIG_EFI_GENERIC_STUB=y CONFIG_EFI_ARMSTUB_DTB_LOADER=y -CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y CONFIG_EFI_BOOTLOADER_CONTROL=m CONFIG_EFI_CAPSULE_LOADER=m # CONFIG_EFI_TEST is not set @@ -1927,6 +1934,7 @@ CONFIG_ZRAM_DEF_COMP_LZORLE=y CONFIG_ZRAM_DEF_COMP="lzo-rle" CONFIG_ZRAM_WRITEBACK=y CONFIG_ZRAM_MEMORY_TRACKING=y +CONFIG_ZRAM_MULTI_COMP=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 CONFIG_BLK_DEV_DRBD=m @@ -2354,7 +2362,6 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_MICROSEMI is not set # CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_NET_VENDOR_MYRI is not set -# CONFIG_FEALNX is not set # CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETERION is not set @@ -2596,6 +2603,7 @@ CONFIG_MT7921_COMMON=m # CONFIG_MT7921E is not set CONFIG_MT7921S=m CONFIG_MT7921U=m +# CONFIG_MT7996E is not set CONFIG_WLAN_VENDOR_MICROCHIP=y CONFIG_WILC1000=m CONFIG_WILC1000_SDIO=m @@ -2788,6 +2796,7 @@ CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LEGACY_TIOCSTI=y CONFIG_LDISC_AUTOLOAD=y # @@ -2836,6 +2845,7 @@ CONFIG_TTY_PRINTK=y CONFIG_TTY_PRINTK_LEVEL=6 CONFIG_VIRTIO_CONSOLE=y # CONFIG_IPMI_HANDLER is not set +# CONFIG_SSIF_IPMI_BMC is not set # CONFIG_IPMB_DEVICE_INTERFACE is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set @@ -2851,8 +2861,6 @@ CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set -CONFIG_RANDOM_TRUST_CPU=y -CONFIG_RANDOM_TRUST_BOOTLOADER=y # end of Character devices # @@ -2970,10 +2978,12 @@ CONFIG_SPI_MESON_SPIFC=y # CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_MICROCHIP_CORE_QSPI is not set # CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PCI1XXXX is not set # CONFIG_SPI_PXA2XX is not set # CONFIG_SPI_ROCKCHIP is not set # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_SN_F_OSPI is not set # CONFIG_SPI_MXIC is not set # CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set @@ -3123,6 +3133,7 @@ CONFIG_GPIO_SYSCON=y # Virtual GPIO drivers # # CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_LATCH is not set # CONFIG_GPIO_MOCKUP is not set # CONFIG_GPIO_VIRTIO is not set # CONFIG_GPIO_SIM is not set @@ -3163,7 +3174,6 @@ CONFIG_POWER_SUPPLY=y # CONFIG_BATTERY_BQ27XXX is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set -# CONFIG_CHARGER_ISP1704 is not set # CONFIG_CHARGER_MAX8903 is not set # CONFIG_CHARGER_LP8727 is not set # CONFIG_CHARGER_GPIO is not set @@ -3425,6 +3435,7 @@ CONFIG_BCMA_POSSIBLE=y CONFIG_MFD_CORE=m # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_SMPRO is not set # CONFIG_MFD_AS3722 is not set # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_AAT2870_CORE is not set @@ -3449,7 +3460,6 @@ CONFIG_MFD_CORE=m # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_HTC_PASIC3 is not set -# CONFIG_HTC_I2CPLD is not set # CONFIG_LPC_ICH is not set # CONFIG_LPC_SCH is not set # CONFIG_MFD_IQS62X is not set @@ -3509,6 +3519,7 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_LP873X is not set # CONFIG_MFD_TI_LP87565 is not set # CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS65219 is not set # CONFIG_MFD_TPS6586X is not set # CONFIG_MFD_TPS65910 is not set # CONFIG_MFD_TPS65912_I2C is not set @@ -3595,6 +3606,7 @@ CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_RT5190A is not set # CONFIG_REGULATOR_RT5759 is not set # CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6190 is not set # CONFIG_REGULATOR_RT6245 is not set # CONFIG_REGULATOR_RTQ2134 is not set # CONFIG_REGULATOR_RTMV20 is not set @@ -3926,7 +3938,6 @@ CONFIG_VIDEO_MESON_GE2D=m # # Aspeed media platform drivers # -# CONFIG_VIDEO_ASPEED is not set # # Atmel media platform drivers @@ -3955,6 +3966,10 @@ CONFIG_VIDEO_MESON_GE2D=m # Mediatek media platform drivers # +# +# Microchip Technology, Inc. media platform drivers +# + # # NVidia media platform drivers # @@ -4016,6 +4031,8 @@ CONFIG_VIDEO_VIMC=m CONFIG_VIDEO_VIVID=m CONFIG_VIDEO_VIVID_CEC=y CONFIG_VIDEO_VIVID_MAX_DEVS=64 +CONFIG_VIDEO_VISL=m +CONFIG_VISL_DEBUGFS=y # CONFIG_DVB_TEST_DRIVERS is not set CONFIG_MEDIA_COMMON_OPTIONS=y @@ -4079,12 +4096,14 @@ CONFIG_VIDEO_MT9V011=m # CONFIG_VIDEO_OG01A1B is not set # CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV08D10 is not set +# CONFIG_VIDEO_OV08X40 is not set # CONFIG_VIDEO_OV13858 is not set # CONFIG_VIDEO_OV13B10 is not set CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set # CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV4689 is not set # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set @@ -4108,11 +4127,11 @@ CONFIG_VIDEO_OV7640=m # CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5C73M3 is not set -# CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_ST_VGXY61 is not set # CONFIG_VIDEO_VS6624 is not set # CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set @@ -4182,6 +4201,7 @@ CONFIG_VIDEO_WM8775=m # CONFIG_VIDEO_SAA7110 is not set CONFIG_VIDEO_SAA711X=m # CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TC358746 is not set # CONFIG_VIDEO_TVP514X is not set CONFIG_VIDEO_TVP5150=m # CONFIG_VIDEO_TVP7002 is not set @@ -4467,6 +4487,7 @@ CONFIG_DVB_SP2=m # Graphics support # CONFIG_APERTURE_HELPERS=y +CONFIG_VIDEO_NOMODESET=y # CONFIG_IMX_IPUV3_CORE is not set CONFIG_DRM=y # CONFIG_DRM_DEBUG_MM is not set @@ -4638,7 +4659,6 @@ CONFIG_DRM_LIMA=y # CONFIG_DRM_SSD130X is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -4738,6 +4758,7 @@ CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y # CONFIG_LOGO is not set # end of Graphics support +# CONFIG_DRM_ACCEL is not set CONFIG_SOUND=m CONFIG_SND=m CONFIG_SND_TIMER=m @@ -5010,6 +5031,7 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_WM8904 is not set # CONFIG_SND_SOC_WM8940 is not set # CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8961 is not set # CONFIG_SND_SOC_WM8962 is not set # CONFIG_SND_SOC_WM8974 is not set # CONFIG_SND_SOC_WM8978 is not set @@ -5205,7 +5227,6 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_HCD_PLATFORM=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_FOTG210_HCD is not set # CONFIG_USB_MAX3421_HCD is not set CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y @@ -5259,6 +5280,10 @@ CONFIG_USBIP_VHCI_NR_HCS=1 CONFIG_USBIP_HOST=m CONFIG_USBIP_VUDC=m # CONFIG_USBIP_DEBUG is not set + +# +# USB dual-mode controller drivers +# # CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set @@ -5369,9 +5394,7 @@ CONFIG_USB_EZUSB_FX2=m # # USB Physical Layer drivers # -CONFIG_USB_PHY=y # CONFIG_NOP_USB_XCEIV is not set -CONFIG_USB_GPIO_VBUS=y # CONFIG_USB_ISP1301 is not set CONFIG_USB_ULPI=y CONFIG_USB_ULPI_VIEWPORT=y @@ -5389,7 +5412,6 @@ CONFIG_U_SERIAL_CONSOLE=y # USB Peripheral Controller # # CONFIG_USB_FUSB300 is not set -# CONFIG_USB_FOTG210_UDC is not set # CONFIG_USB_GR_UDC is not set # CONFIG_USB_R8A66597 is not set # CONFIG_USB_PXA27X is not set @@ -5862,6 +5884,7 @@ CONFIG_IOMMU_IO_PGTABLE_LPAE=y # end of Generic IOMMU Pagetable Support CONFIG_IOMMU_DEBUGFS=y +# CONFIG_IOMMUFD is not set # CONFIG_ARM_SMMU is not set # @@ -6013,6 +6036,8 @@ CONFIG_IIO_TRIGGERED_EVENT=m # CONFIG_FXLS8962AF_I2C is not set # CONFIG_FXLS8962AF_SPI is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_IIO_KX022A_SPI is not set +# CONFIG_IIO_KX022A_I2C is not set # CONFIG_KXSD9 is not set # CONFIG_KXCJK1013 is not set # CONFIG_MC3230 is not set @@ -6034,6 +6059,7 @@ CONFIG_IIO_TRIGGERED_EVENT=m # # Analog to digital converters # +# CONFIG_AD4130 is not set # CONFIG_AD7091R5 is not set # CONFIG_AD7124 is not set # CONFIG_AD7192 is not set @@ -6068,6 +6094,7 @@ CONFIG_IIO_TRIGGERED_EVENT=m # CONFIG_MAX11100 is not set # CONFIG_MAX1118 is not set # CONFIG_MAX11205 is not set +# CONFIG_MAX11410 is not set # CONFIG_MAX1241 is not set # CONFIG_MAX1363 is not set # CONFIG_MAX9611 is not set @@ -6100,6 +6127,7 @@ CONFIG_MESON_SARADC=m # # Analog to digital and digital to analog converters # +# CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # end of Analog to digital and digital to analog converters @@ -6228,6 +6256,7 @@ CONFIG_MESON_SARADC=m # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADF4377 is not set # CONFIG_ADMV1013 is not set # CONFIG_ADMV4420 is not set # CONFIG_ADRF6780 is not set @@ -6480,6 +6509,7 @@ CONFIG_IIO_HRTIMER_TRIGGER=y # CONFIG_TMP117 is not set # CONFIG_TSYS01 is not set # CONFIG_TSYS02D is not set +# CONFIG_MAX30208 is not set # CONFIG_MAX31856 is not set # CONFIG_MAX31865 is not set # end of Temperature sensors @@ -6564,6 +6594,7 @@ CONFIG_PHY_MESON_CVBS_DAC=y # CONFIG_ARM_CCI_PMU is not set # CONFIG_ARM_CCN is not set CONFIG_ARM_PMU=y +# CONFIG_MESON_DDR_PMU is not set # end of Performance monitor support CONFIG_RAS=y @@ -6797,8 +6828,10 @@ CONFIG_SQUASHFS=m CONFIG_SQUASHFS_FILE_CACHE=y # CONFIG_SQUASHFS_FILE_DIRECT is not set CONFIG_SQUASHFS_DECOMP_SINGLE=y -# CONFIG_SQUASHFS_DECOMP_MULTI is not set -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_DECOMP_MULTI=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y +CONFIG_SQUASHFS_MOUNT_DECOMP_THREADS=y CONFIG_SQUASHFS_XATTR=y CONFIG_SQUASHFS_ZLIB=y CONFIG_SQUASHFS_LZ4=y @@ -6877,6 +6910,7 @@ CONFIG_NFS_DEBUG=y CONFIG_NFS_DISABLE_UDP_SUPPORT=y CONFIG_NFS_V4_2_READ_PLUS=y CONFIG_NFSD=m +CONFIG_NFSD_V2=y CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y @@ -7053,7 +7087,6 @@ CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_PCRYPT=m @@ -7285,6 +7318,7 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=m CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_GF128MUL=m CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m @@ -7407,6 +7441,7 @@ CONFIG_FONT_SUPPORT=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_SG_POOL=y +CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y CONFIG_SBITMAP=y # end of Library routines @@ -7467,6 +7502,7 @@ CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y # CONFIG_UBSAN is not set # end of Generic Kernel Debugging Instruments @@ -7588,6 +7624,7 @@ CONFIG_RCU_TRACE=y # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_LATENCYTOP is not set +# CONFIG_DEBUG_CGROUP_REF is not set CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y @@ -7660,6 +7697,7 @@ CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" # # CONFIG_KUNIT is not set # CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FUNCTION_ERROR_INJECTION is not set # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y @@ -7679,7 +7717,6 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_HEXDUMP is not set # CONFIG_STRING_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set -# CONFIG_TEST_STRSCPY is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set # CONFIG_TEST_SCANF is not set @@ -7688,7 +7725,6 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_XARRAY is not set # CONFIG_TEST_MAPLE_TREE is not set # CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set # CONFIG_TEST_BITOPS is not set diff --git a/config/sources/families/include/meson_common.inc b/config/sources/families/include/meson_common.inc index 6461413ed..42bb0fa15 100644 --- a/config/sources/families/include/meson_common.inc +++ b/config/sources/families/include/meson_common.inc @@ -36,16 +36,16 @@ esac case $BRANCH in current) - export KERNEL_MAJOR_MINOR="5.15" # Major and minor versions of this kernel. - KERNELBRANCH="branch:linux-5.15.y" + export KERNEL_MAJOR_MINOR="6.1" # Major and minor versions of this kernel. + KERNELBRANCH="branch:linux-6.1.y" KERNELPATCHDIR='meson-'$BRANCH ;; edge) - export KERNEL_MAJOR_MINOR="6.1" # Major and minor versions of this kernel. - KERNELBRANCH="branch:linux-6.1.y" + export KERNEL_MAJOR_MINOR="6.2" # Major and minor versions of this kernel. + KERNELBRANCH="branch:linux-6.2.y" KERNELPATCHDIR='meson-'$BRANCH ;; diff --git a/patch/kernel/archive/meson-5.15/Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch b/patch/kernel/archive/meson-5.15/Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch deleted file mode 100644 index 2cde1c334..000000000 --- a/patch/kernel/archive/meson-5.15/Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch +++ /dev/null @@ -1,73 +0,0 @@ -Revert "mmc: core: Set HS clock speed before sending HS CMD13" - -This reverts commit 4bc31edebde51fcf8ad0794763b8679a7ecb5ec0. ---- - drivers/mmc/core/mmc.c | 23 ++++------------------- - 1 file changed, 4 insertions(+), 19 deletions(-) - -diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c -index efa95dc4fc4..e7ea45386c2 100644 ---- a/drivers/mmc/core/mmc.c -+++ b/drivers/mmc/core/mmc.c -@@ -1384,17 +1384,13 @@ static int mmc_select_hs400es(struct mmc_card *card) - goto out_err; - } - -- /* -- * Bump to HS timing and frequency. Some cards don't handle -- * SEND_STATUS reliably at the initial frequency. -- */ - mmc_set_timing(host, MMC_TIMING_MMC_HS); -- mmc_set_bus_speed(card); -- - err = mmc_switch_status(card, true); - if (err) - goto out_err; - -+ mmc_set_clock(host, card->ext_csd.hs_max_dtr); -+ - /* Switch card to DDR with strobe bit */ - val = EXT_CSD_DDR_BUS_WIDTH_8 | EXT_CSD_BUS_WIDTH_STROBE; - err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, -@@ -1452,7 +1448,7 @@ static int mmc_select_hs400es(struct mmc_card *card) - static int mmc_select_hs200(struct mmc_card *card) - { - struct mmc_host *host = card->host; -- unsigned int old_timing, old_signal_voltage, old_clock; -+ unsigned int old_timing, old_signal_voltage; - int err = -EINVAL; - u8 val; - -@@ -1483,17 +1479,8 @@ static int mmc_select_hs200(struct mmc_card *card) - false, true, MMC_CMD_RETRIES); - if (err) - goto err; -- -- /* -- * Bump to HS timing and frequency. Some cards don't handle -- * SEND_STATUS reliably at the initial frequency. -- * NB: We can't move to full (HS200) speeds until after we've -- * successfully switched over. -- */ - old_timing = host->ios.timing; -- old_clock = host->ios.clock; - mmc_set_timing(host, MMC_TIMING_MMC_HS200); -- mmc_set_clock(card->host, card->ext_csd.hs_max_dtr); - - /* - * For HS200, CRC errors are not a reliable way to know the -@@ -1506,10 +1493,8 @@ static int mmc_select_hs200(struct mmc_card *card) - * mmc_select_timing() assumes timing has not changed if - * it is a switch error. - */ -- if (err == -EBADMSG) { -- mmc_set_clock(host, old_clock); -+ if (err == -EBADMSG) - mmc_set_timing(host, old_timing); -- } - } - err: - if (err) { --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.15/board_odroidc1/dts-Enable-HDMI.patch b/patch/kernel/archive/meson-5.15/board_odroidc1/dts-Enable-HDMI.patch deleted file mode 100644 index e8fd3518c..000000000 --- a/patch/kernel/archive/meson-5.15/board_odroidc1/dts-Enable-HDMI.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 2954b682a71fad9d912c68737556259dabf3dcec Mon Sep 17 00:00:00 2001 -From: Martin Blumenstingl -Date: Fri, 20 Mar 2020 15:17:51 +0100 -Subject: [PATCH 065/122] ARM: dts: meson8b: odroid-c1: enable HDMI for the - Odroid-C1 - WiP - -WiP - -Signed-off-by: Martin Blumenstingl ---- - arch/arm/boot/dts/meson8b-odroidc1.dts | 73 ++++++++++++++++++++++++++ - 1 file changed, 73 insertions(+) - -diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts -index 04cce559980..ef52033561c 100644 ---- a/arch/arm/boot/dts/meson8b-odroidc1.dts -+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts -@@ -32,6 +32,17 @@ emmc_pwrseq: emmc-pwrseq { - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - -+ hdmi-connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_connector_in: endpoint { -+ remote-endpoint = <&hdmi_tx_tmds_out>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - blue { -@@ -93,6 +104,50 @@ rtc32k_xtal: rtc32k-xtal-clk { - #clock-cells = <0>; - }; - -+ sound { -+ compatible = "amlogic,gx-sound-card"; -+ model = "M8B-ODROID-C1"; -+ -+ assigned-clocks = <&clkc CLKID_MPLL0>, -+ <&clkc CLKID_MPLL1>; -+ assigned-clock-rates = <294912000>, -+ <270950400>; -+ -+ dai-link-0 { -+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; -+ }; -+ -+ dai-link-1 { -+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; -+ }; -+ -+ dai-link-2 { -+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; -+ dai-format = "i2s"; -+ mclk-fs = <256>; -+ -+ codec-0 { -+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>; -+ }; -+ }; -+ -+ dai-link-3 { -+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; -+ -+ codec-0 { -+ sound-dai = <&hdmi_tx 1>; -+ }; -+ }; -+ -+ dai-link-4 { -+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>; -+ -+ codec-0 { -+ sound-dai = <&hdmi_tx 0>; -+ }; -+ }; -+ }; -+ - vcc_1v8: regulator-vcc-1v8 { - /* - * RICHTEK RT9179 configured for a fixed output voltage of -@@ -187,6 +242,12 @@ vdd_rtc: regulator-vdd-rtc { - }; - }; - -+&aiu { -+ status = "okay"; -+ pinctrl-0 = <&spdif_out_1_pins>; -+ pinctrl-names = "default"; -+}; -+ - &cpu0 { - cpu-supply = <&vcck>; - }; -@@ -298,6 +359,18 @@ usb-hub { - }; - }; - -+&hdmi_tx { -+ status = "okay"; -+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&hdmi_tx_tmds_port { -+ hdmi_tx_tmds_out: endpoint { -+ remote-endpoint = <&hdmi_connector_in>; -+ }; -+}; -+ - &ir_receiver { - status = "okay"; - pinctrl-0 = <&ir_recv_pins>; --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.15/board_onecloud/0001-add-dts.patch b/patch/kernel/archive/meson-5.15/board_onecloud/0001-add-dts.patch deleted file mode 100644 index 582dce580..000000000 --- a/patch/kernel/archive/meson-5.15/board_onecloud/0001-add-dts.patch +++ /dev/null @@ -1,431 +0,0 @@ -Add dts - ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/meson8b-onecloud.dts | 402 +++++++++++++++++++++++++ - 2 files changed, 403 insertions(+) - create mode 100644 arch/arm/boot/dts/meson8b-onecloud.dts - -diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile -index 7a72fc636a7a..9f9ddbf04128 100644 ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -365,6 +365,7 @@ dtb-$(CONFIG_MACH_MESON8) += \ - meson8b-ec100.dtb \ - meson8b-mxq.dtb \ - meson8b-odroidc1.dtb \ -+ meson8b-onecloud.dtb \ - meson8m2-mxiii-plus.dtb - dtb-$(CONFIG_ARCH_MMP) += \ - pxa168-aspenite.dtb \ -diff --git a/arch/arm/boot/dts/meson8b-onecloud.dts b/arch/arm/boot/dts/meson8b-onecloud.dts -new file mode 100644 -index 000000000000..d517e45e22ba ---- /dev/null -+++ b/arch/arm/boot/dts/meson8b-onecloud.dts -@@ -0,0 +1,402 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Author: hzyitc -+ */ -+ -+/dts-v1/; -+#include "meson8b.dtsi" -+#include -+#include -+ -+/ { -+ model = "Xunlei OneCloud"; -+ compatible = "xunlei,onecloud", "amlogic,meson8b"; -+ -+ aliases { -+ serial0 = &uart_AO; -+ mmc0 = &sd_card_slot; -+ mmc1 = &sdhc; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x40000000 0x40000000>; -+ }; -+ -+ emmc_pwrseq: emmc-pwrseq { -+ compatible = "mmc-pwrseq-emmc"; -+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; -+ }; -+ -+ button { -+ // compatible = "gpio-keys-polled"; -+ // poll-interval = <100>; -+ -+ compatible = "gpio-keys"; -+ -+ autorepeat; -+ -+ reset-button { -+ label = "reset"; -+ linux,code = ; -+ -+ // gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_LOW>; -+ -+ interrupt-parent = <&gpio_intc>; -+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>; // GPIOAO 5 -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ red { -+ label = "onecloud:red:alive"; -+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; -+ -+ default-state = "on"; -+ linux,default-trigger = "default-on"; -+ }; -+ -+ green { -+ label = "onecloud:green:alive"; -+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; -+ -+ default-state = "off"; -+ linux,default-trigger = "mmc1"; -+ }; -+ -+ blue { -+ label = "onecloud:blue:alive"; -+ gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; -+ -+ default-state = "off"; -+ linux,default-trigger = "usb-host"; -+ }; -+ }; -+ -+ p12v: regulator-p12v { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "P12V"; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ vcc_5v: regulator-vcc-5v { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "VCC5V"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ -+ vin-supply = <&p12v>; -+ -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vcc_3v3: regulator-vcc-3v3 { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ vin-supply = <&p12v>; -+ -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vcc_1v8: regulator-vcc-1v8 { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "VCC1V8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ vin-supply = <&p12v>; -+ -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vcc_ddr: regulator-vcc-ddr { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "VCC_DDR"; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ -+ vin-supply = <&vcc_3v3>; -+ -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vcc_core: regulator-vcc-core { -+ compatible = "pwm-regulator"; -+ -+ regulator-name = "VCC_CORE"; -+ -+ // +---------------------------------------------------+ -+ // | The actual mapping in phyical | -+ // +------+--------+--------+--------+--------+--------+ -+ // | | 100% | 60% | 30% | 10% | 0% | -+ // +------+--------+--------+--------+--------+--------+ -+ // | V1.0 | 677mV | 857mV | 992mV | 1082mV | 1127mV | -+ // | V1.3 | 1116mV | 1121mV | 1125mV | 1128mV | 1129mV | -+ // +------+--------+--------+--------+--------+--------+ -+ // -+ // According to meson8b.dtsi, the CPU should be able to -+ // run at 504MHz with 870mV. But this regulator supplies -+ // not only CPU but also GPU. And according to the users' -+ // tests on V1.0, we need such higher voltages. -+ -+ pwms = <&pwm_cd 1 12001 0>; // PWM_D -+ pwm-dutycycle-range = <10 0>; -+ regulator-min-microvolt = <860000>; -+ regulator-max-microvolt = <1140000>; -+ -+ pwm-supply = <&p12v>; -+ -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&pwm_cd { -+ status = "okay"; -+ pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; -+ pinctrl-names = "default"; -+ clocks = <&xtal>, <&xtal>; -+ clock-names = "clkin0", "clkin1"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vcc_core>; -+}; -+ -+&mali { -+ // commented to allow cpufreq tweaking -+ // mali-supply = <&vcc_core>; -+}; -+ -+&gpio { -+ gpio-line-names = -+ // 0-3 Bank GPIOX 0-3 -+ "7U1_PIN_18", "7U1_PIN_19", -+ "7U1_PIN_14", "7U1_PIN_15", -+ // 4-7 Bank GPIOX 4-7 -+ "7U1_PIN_27", "7U1_PIN_25", -+ "7U1_PIN_28", "7U1_PIN_26", -+ // 8 Bank GPIOX 8 -+ "R_RightOf_LED", -+ // 9 Bank GPIOX 9 -+ "7U1_PIN_16", -+ // 10 Bank GPIOX 10 -+ "", -+ // 11 Bank GPIOX 11 -+ "7U1_PIN_12", -+ // 12-16 Bank GPIOX 16-20 -+ "7U1_PIN_43", "7U1_PIN_42", -+ "7U1_PIN_41(Resistor)", "7U1_PIN_44", -+ "7U1_PIN_34", -+ // 17 Bank GPIOX 21 -+ "7U1_PIN_13", -+ -+ // 18 Bank GPIOY 0 -+ "Resistor_TopOf_LED", -+ // 19-20 Bank GPIOY 1-3 -+ "", "", -+ // 21-26 Bank GPIOY 6-11 -+ "", "", -+ "", "", -+ "", "", -+ // 27 Bank GPIOY 12 -+ "", -+ // 28-29 Bank GPIOY 13-14 -+ "Left_BottomOf_CPU", "Right_BottomOf_CPU", -+ -+ // 30 Bank GPIODV 9 -+ "VCCK_PWM (PWM_C)", -+ // 31-35 Bank GPIODV 24-28 -+ "I2CA_SDA", "I2CA_SCL", -+ "I2CB_SDA", "I2CB_SCL", -+ "VDDEE_PWM (PWM_D)", -+ // 36 Bank GPIODV 29 -+ "", -+ -+ // 37-39 Bank GPIOH 0-2 -+ "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", -+ // 40-46 Bank GPIOH 3-9 -+ "ETH_PHY_INTR", "ETH_PHY_NRST", -+ "ETH_TXD1", "ETH_TXD0", -+ "ETH_TXD3", "ETH_TXD2", -+ "ETH_RGMII_TX_CLK", -+ -+ // 47-53 Bank CARD 0-6 -+ "SD_D1", "SD_D0", -+ "SD_CLK", "SD_CMD", -+ "SD_D3", "SD_D2", -+ "SD_CD", -+ -+ // 54-65 Bank BOOT 0-11 -+ "EMMC_D0", "EMMC_D1", -+ "EMMC_D2", "EMMC_D3", -+ "EMMC_D4", "EMMC_D5", -+ "EMMC_D6", "EMMC_D7", -+ "EMMC_CLK", "EMMC_RSTn", -+ "EMMC_CMD", "BOOT_SEL", -+ // 66-72 Bank BOOT 12-18 -+ "", "", -+ "", "", -+ "", "", -+ "", -+ -+ // 73-74 Bank DIF 0P 0N -+ "ETH_RXD1", "ETH_RXD0", -+ // 75-76 Bank DIF 1P 1N -+ "ETH_RX_DV", "RGMII_RX_CLK", -+ // 77-78 Bank DIF 2P 2N -+ "ETH_RXD3", "ETH_RXD2", -+ // 79-80 Bank DIF 3P 3N -+ "ETH_TXEN", "ETH_PHY_REF_CLK_25MOUT", -+ // 81-82 Bank DIF 4P 4N -+ "ETH_MDC", "ETH_MDIO"; -+}; -+ -+&gpio_ao { -+ gpio-line-names = -+ // 0-1 Band GPIOAO 0-1 -+ "UART TX", "UART RX", -+ // 2-4 Band GPIOAO 2-4 -+ "RED_LED", "GREEN_LED", "BLUE_LED", -+ // 5 Band GPIOAO 5 -+ "BUTTON", -+ // 6 Band GPIOAO 6 -+ "", -+ // 7 Band GPIOAO 7 -+ "IR_IN", -+ // 8 Band GPIOAO 8-13 -+ "", "", -+ "", "", -+ "", "", -+ -+ // 14 Band GPIO_BSD_EN -+ "", -+ // 15 GPIO_TEST_N -+ ""; -+}; -+ -+ðmac { -+ status = "okay"; -+ -+ pinctrl-0 = <ð_rgmii_pins>; -+ pinctrl-names = "default"; -+ -+ phy-handle = <ð_phy>; -+ phy-mode = "rgmii-id"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ // Realtek RTL8211F (0x001cc916) -+ eth_phy: ethernet-phy@0 { -+ reg = <0>; -+ -+ reset-assert-us = <10000>; -+ reset-deassert-us = <80000>; -+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; -+ -+ interrupt-parent = <&gpio_intc>; -+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; // GPIOH 3 -+ }; -+ }; -+}; -+ -+&saradc { -+ status = "okay"; -+ vref-supply = <&vcc_1v8>; -+}; -+ -+// eMMC -+&sdhc { -+ status = "okay"; -+ -+ pinctrl-0 = <&sdxc_c_pins>; -+ pinctrl-names = "default"; -+ -+ bus-width = <8>; -+ max-frequency = <100000000>; -+ -+ disable-wp; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ no-sdio; -+ -+ mmc-pwrseq = <&emmc_pwrseq>; -+ -+ vmmc-supply = <&vcc_3v3>; -+ // vqmmc-supply = <&vcc_3v3>; -+}; -+ -+&sdio { -+ status = "okay"; -+ -+ pinctrl-0 = <&sd_b_pins>; -+ pinctrl-names = "default"; -+ -+ // SD card -+ sd_card_slot: slot@1 { -+ compatible = "mmc-slot"; -+ reg = <1>; -+ status = "okay"; -+ -+ bus-width = <4>; -+ no-sdio; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ -+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; -+ -+ vmmc-supply = <&vcc_3v3>; -+ // vqmmc-supply = <&vcc_3v3>; -+ }; -+}; -+ -+&uart_AO { -+ status = "okay"; -+ pinctrl-0 = <&uart_ao_a_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&usb0_phy { -+ status = "okay"; -+}; -+ -+&usb0 { -+ status = "okay"; -+}; -+ -+&usb1_phy { -+ status = "okay"; -+}; -+ -+&usb1 { -+ status = "okay"; -+}; -+ -+&ir_receiver { -+ status = "okay"; -+ pinctrl-0 = <&ir_recv_pins>; -+ pinctrl-names = "default"; -+}; --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.15/board_onecloud/0002-dts-Support-HDMI.patch b/patch/kernel/archive/meson-5.15/board_onecloud/0002-dts-Support-HDMI.patch deleted file mode 100644 index b901f6dd5..000000000 --- a/patch/kernel/archive/meson-5.15/board_onecloud/0002-dts-Support-HDMI.patch +++ /dev/null @@ -1,92 +0,0 @@ -dts: Support HDMI - ---- - arch/arm/boot/dts/meson8b-onecloud.dts | 58 ++++++++++++++++++++++++++ - 1 file changed, 58 insertions(+) - -diff --git a/arch/arm/boot/dts/meson8b-onecloud.dts b/arch/arm/boot/dts/meson8b-onecloud.dts -index 050b2e65348..69fff33c496 100644 ---- a/arch/arm/boot/dts/meson8b-onecloud.dts -+++ b/arch/arm/boot/dts/meson8b-onecloud.dts -@@ -32,6 +32,48 @@ emmc_pwrseq: emmc-pwrseq { - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - -+ hdmi-connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_connector_in: endpoint { -+ remote-endpoint = <&hdmi_tx_tmds_out>; -+ }; -+ }; -+ }; -+ -+ sound { -+ compatible = "amlogic,gx-sound-card"; -+ -+ assigned-clocks = <&clkc CLKID_MPLL0>, -+ <&clkc CLKID_MPLL1>; -+ assigned-clock-rates = <294912000>, -+ <270950400>; -+ -+ dai-link-0 { -+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; -+ }; -+ -+ dai-link-1 { -+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; -+ dai-format = "i2s"; -+ mclk-fs = <256>; -+ -+ codec-0 { -+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>; -+ }; -+ }; -+ -+ dai-link-2 { -+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>; -+ -+ codec-0 { -+ sound-dai = <&hdmi_tx 0>; -+ }; -+ }; -+ }; -+ - button { - // compatible = "gpio-keys-polled"; - // poll-interval = <100>; -@@ -142,6 +184,10 @@ vcc_core: regulator-vcc-core { - }; - }; - -+&aiu { -+ status = "okay"; -+}; -+ - &cpu0 { - cpu-supply = <&vcc_core>; - }; -@@ -150,6 +196,18 @@ &mali { - mali-supply = <&vcc_core>; - }; - -+&hdmi_tx { -+ status = "okay"; -+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&hdmi_tx_tmds_port { -+ hdmi_tx_tmds_out: endpoint { -+ remote-endpoint = <&hdmi_connector_in>; -+ }; -+}; -+ - &gpio { - gpio-line-names = - // 0-3 Bank GPIOX 0-3 --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.15/board_onecloud/usb-disable-ACA-check.patch b/patch/kernel/archive/meson-5.15/board_onecloud/usb-disable-ACA-check.patch deleted file mode 100644 index c17e8596d..000000000 --- a/patch/kernel/archive/meson-5.15/board_onecloud/usb-disable-ACA-check.patch +++ /dev/null @@ -1,33 +0,0 @@ -USB: Disable ACA check - -In V1.3, USB0 fails in this check. -But it can work normally. -So just disable this check. - ---- - drivers/phy/amlogic/phy-meson8b-usb2.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/phy/amlogic/phy-meson8b-usb2.c b/drivers/phy/amlogic/phy-meson8b-usb2.c -index dd96763911b8..dff1bc44f1ca 100644 ---- a/drivers/phy/amlogic/phy-meson8b-usb2.c -+++ b/drivers/phy/amlogic/phy-meson8b-usb2.c -@@ -197,13 +197,13 @@ static int phy_meson8b_usb2_power_on(struct phy *phy) - udelay(ACA_ENABLE_COMPLETE_TIME); - - regmap_read(priv->regmap, REG_ADP_BC, ®); -- if (reg & REG_ADP_BC_ACA_PIN_FLOAT) { -+ /*if (reg & REG_ADP_BC_ACA_PIN_FLOAT) { - dev_warn(&phy->dev, "USB ID detect failed!\n"); - clk_disable_unprepare(priv->clk_usb); - clk_disable_unprepare(priv->clk_usb_general); - reset_control_rearm(priv->reset); - return -EINVAL; -- } -+ }*/ - } - } - --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.15/generate-uImage-instand-of-zImage.patch b/patch/kernel/archive/meson-5.15/generate-uImage-instand-of-zImage.patch deleted file mode 100644 index 085dd2ff6..000000000 --- a/patch/kernel/archive/meson-5.15/generate-uImage-instand-of-zImage.patch +++ /dev/null @@ -1,27 +0,0 @@ -Generate uImage instand of zImage - ---- - scripts/package/builddeb | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/scripts/package/builddeb b/scripts/package/builddeb -index 91a502bb9..196889f1d 100755 ---- a/scripts/package/builddeb -+++ b/scripts/package/builddeb -@@ -218,6 +218,13 @@ if [ "$ARCH" != "um" ]; then - create_package linux-libc-dev debian/linux-libc-dev - fi - -+sed -e "s/exit 0//g" -i $tmpdir/DEBIAN/postinst -+cat >> $tmpdir/DEBIAN/postinst < /dev/null 2>&1 -+rm -f /boot/zImage -+exit 0 -+EOT -+ - create_package "$packagename" "$tmpdir" - - if [ -n "$BUILD_DEBUG" ] ; then --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.15/m8-m8b-m8m2-Support-HDMI.patch b/patch/kernel/archive/meson-5.15/m8-m8b-m8m2-Support-HDMI.patch deleted file mode 100644 index 2339ee514..000000000 --- a/patch/kernel/archive/meson-5.15/m8-m8b-m8m2-Support-HDMI.patch +++ /dev/null @@ -1,5568 +0,0 @@ -meson8/meson8b/meson8m2: Support HDMI - -The following codes are come from https://github.com/xdarklight/linux/tree/meson-mx-integration-5.15-20211031. - -Special thank. - ---- - .../bindings/display/amlogic,meson-vpu.yaml | 13 + - .../phy/amlogic,meson-cvbs-dac-phy.yaml | 81 + - .../phy/amlogic,meson8-hdmi-tx-phy.yaml | 65 + - arch/arm/boot/dts/meson.dtsi | 13 + - arch/arm/boot/dts/meson8.dtsi | 168 +- - arch/arm/boot/dts/meson8b.dtsi | 171 +- - arch/arm/boot/dts/meson8m2.dtsi | 4 + - drivers/clk/meson/meson8b.c | 163 +- - drivers/clk/meson/meson8b.h | 26 +- - drivers/gpu/drm/meson/Kconfig | 8 + - drivers/gpu/drm/meson/Makefile | 3 +- - drivers/gpu/drm/meson/meson_drv.c | 290 ++- - drivers/gpu/drm/meson/meson_drv.h | 53 +- - drivers/gpu/drm/meson/meson_encoder_cvbs.c | 318 ++++ - ...meson_venc_cvbs.h => meson_encoder_cvbs.h} | 2 +- - drivers/gpu/drm/meson/meson_encoder_hdmi.c | 20 +- - drivers/gpu/drm/meson/meson_plane.c | 33 +- - drivers/gpu/drm/meson/meson_transwitch_hdmi.c | 1602 +++++++++++++++++ - drivers/gpu/drm/meson/meson_transwitch_hdmi.h | 536 ++++++ - drivers/gpu/drm/meson/meson_vclk.c | 146 ++ - drivers/gpu/drm/meson/meson_venc.c | 45 +- - drivers/gpu/drm/meson/meson_venc_cvbs.c | 293 --- - drivers/gpu/drm/meson/meson_viu.c | 18 +- - drivers/phy/amlogic/Kconfig | 20 + - drivers/phy/amlogic/Makefile | 2 + - drivers/phy/amlogic/phy-meson-cvbs-dac.c | 310 ++++ - drivers/phy/amlogic/phy-meson8-hdmi-tx.c | 160 ++ - include/dt-bindings/clock/meson8b-clkc.h | 10 + - 28 files changed, 4101 insertions(+), 472 deletions(-) - create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml - create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml - create mode 100644 drivers/gpu/drm/meson/meson_encoder_cvbs.c - rename drivers/gpu/drm/meson/{meson_venc_cvbs.h => meson_encoder_cvbs.h} (92%) - create mode 100644 drivers/gpu/drm/meson/meson_transwitch_hdmi.c - create mode 100644 drivers/gpu/drm/meson/meson_transwitch_hdmi.h - delete mode 100644 drivers/gpu/drm/meson/meson_venc_cvbs.c - create mode 100644 drivers/phy/amlogic/phy-meson-cvbs-dac.c - create mode 100644 drivers/phy/amlogic/phy-meson8-hdmi-tx.c - -diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml -index 047fd69e0377..7cb14c12f115 100644 ---- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml -+++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml -@@ -66,8 +66,12 @@ properties: - - const: amlogic,meson-gx-vpu - - enum: - - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2) -+ - amlogic,meson8-vpu -+ - amlogic,meson8b-vpu -+ - amlogic,meson8m2-vpu - - reg: -+ minItems: 1 - maxItems: 2 - - reg-names: -@@ -82,6 +86,15 @@ properties: - description: should point to a canvas provider node - $ref: /schemas/types.yaml#/definitions/phandle - -+ phys: -+ maxItems: 1 -+ description: -+ PHY specifier for the CVBS DAC -+ -+ phy-names: -+ items: -+ - const: cvbs-dac -+ - power-domains: - maxItems: 1 - description: phandle to the associated power domain -diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml -new file mode 100644 -index 000000000000..d73cb12c0d9f ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml -@@ -0,0 +1,81 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: "http://devicetree.org/schemas/phy/amlogic,meson-cvbs-dac-phy.yaml#" -+$schema: "http://devicetree.org/meta-schemas/core.yaml#" -+ -+title: Amlogic Meson Composite Video Baseband Signal DAC -+ -+maintainers: -+ - Martin Blumenstingl -+ -+description: |+ -+ The CVBS DAC node should be the child of a syscon node with the -+ required property: -+ -+ compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" -+ -+ Refer to the bindings described in -+ Documentation/devicetree/bindings/mfd/syscon.yaml -+ -+properties: -+ $nodename: -+ pattern: "^video-dac@[0-9a-f]+$" -+ -+ compatible: -+ oneOf: -+ - items: -+ - enum: -+ - amlogic,meson8-cvbs-dac -+ - amlogic,meson-gxbb-cvbs-dac -+ - amlogic,meson-gxl-cvbs-dac -+ - amlogic,meson-g12a-cvbs-dac -+ - const: amlogic,meson-cvbs-dac -+ - const: amlogic,meson-cvbs-dac -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 1 -+ -+ nvmem-cells: -+ minItems: 1 -+ -+ nvmem-cell-names: -+ items: -+ - const: cvbs_trimming -+ -+ "#phy-cells": -+ const: 0 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - "#phy-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ video-dac@2f4 { -+ compatible = "amlogic,meson8-cvbs-dac", "amlogic,meson-cvbs-dac"; -+ reg = <0x2f4 0x8>; -+ -+ #phy-cells = <0>; -+ -+ clocks = <&vdac_clock>; -+ -+ nvmem-cells = <&cvbs_trimming>; -+ nvmem-cell-names = "cvbs_trimming"; -+ }; -+ - | -+ video-dac@2ec { -+ compatible = "amlogic,meson-g12a-cvbs-dac", "amlogic,meson-cvbs-dac"; -+ reg = <0x2ec 0x8>; -+ -+ #phy-cells = <0>; -+ -+ clocks = <&vdac_clock>; -+ }; -diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml -new file mode 100644 -index 000000000000..1f085cdd1c85 ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml -@@ -0,0 +1,65 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: "http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#" -+$schema: "http://devicetree.org/meta-schemas/core.yaml#" -+ -+title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY -+ -+maintainers: -+ - Martin Blumenstingl -+ -+description: |+ -+ The HDMI TX PHY node should be the child of a syscon node with the -+ required property: -+ -+ compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" -+ -+ Refer to the bindings described in -+ Documentation/devicetree/bindings/mfd/syscon.yaml -+ -+properties: -+ $nodename: -+ pattern: "^hdmi-phy@[0-9a-f]+$" -+ -+ compatible: -+ oneOf: -+ - items: -+ - enum: -+ - amlogic,meson8b-hdmi-tx-phy -+ - amlogic,meson8m2-hdmi-tx-phy -+ - const: amlogic,meson8-hdmi-tx-phy -+ - const: amlogic,meson8-hdmi-tx-phy -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 1 -+ description: -+ HDMI TMDS clock -+ -+ "#phy-cells": -+ const: 0 -+ -+required: -+ - compatible -+ - "#phy-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ hdmi-phy@3a0 { -+ compatible = "amlogic,meson8-hdmi-tx-phy"; -+ reg = <0x3a0 0xc>; -+ clocks = <&tmds_clock>; -+ #phy-cells = <0>; -+ }; -+ - | -+ hdmi-phy@3a0 { -+ compatible = "amlogic,meson8b-hdmi-tx-phy", "amlogic,meson8-hdmi-tx-phy"; -+ reg = <0x3a0 0xc>; -+ clocks = <&tmds_clock>; -+ #phy-cells = <0>; -+ }; -diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi -index 26eaba3fa96f..28caf20d4181 100644 ---- a/arch/arm/boot/dts/meson.dtsi -+++ b/arch/arm/boot/dts/meson.dtsi -@@ -35,6 +35,19 @@ hhi: system-controller@4000 { - "simple-mfd", - "syscon"; - reg = <0x4000 0x400>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x4000 0x400>; -+ -+ -+ cvbs_dac: video-dac@2f4 { -+ compatible = "amlogic,meson-cvbs-dac"; -+ reg = <0x2f4 0x8>; -+ -+ #phy-cells = <0>; -+ -+ status = "disabled"; -+ }; - }; - - aiu: audio-controller@5400 { -diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi -index 9997a5d0333a..e8073f6abd20 100644 ---- a/arch/arm/boot/dts/meson8.dtsi -+++ b/arch/arm/boot/dts/meson8.dtsi -@@ -314,6 +314,113 @@ mali: gpu@c0000 { - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; -+ -+ hdmi_tx: hdmi-tx@42000 { -+ compatible = "amlogic,meson8-hdmi-tx"; -+ reg = <0x42000 0xc>; -+ interrupts = ; -+ phys = <&hdmi_tx_phy>; -+ phy-names = "hdmi"; -+ clocks = <&clkc CLKID_HDMI_PCLK>, -+ <&clkc CLKID_HDMI_SYS>; -+ clock-names = "pclk", "sys"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ #sound-dai-cells = <1>; -+ sound-name-prefix = "HDMITX"; -+ -+ status = "disabled"; -+ -+ /* VPU VENC Input */ -+ hdmi_tx_venc_port: port@0 { -+ reg = <0>; -+ -+ hdmi_tx_in: endpoint { -+ remote-endpoint = <&hdmi_tx_out>; -+ }; -+ }; -+ -+ /* TMDS Output */ -+ hdmi_tx_tmds_port: port@1 { -+ reg = <1>; -+ }; -+ }; -+ -+ vpu: vpu@100000 { -+ compatible = "amlogic,meson8-vpu"; -+ -+ reg = <0x100000 0x10000>; -+ reg-names = "vpu"; -+ -+ interrupts = ; -+ -+ amlogic,canvas = <&canvas>; -+ -+ /* -+ * The VCLK{,2}_IN path always needs to derived from -+ * the CLKID_VID_PLL_FINAL_DIV so other clocks like -+ * MPLL1 are not used (MPLL1 is reserved for audio -+ * purposes). -+ */ -+ assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>, -+ <&clkc CLKID_VCLK2_IN_SEL>; -+ assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>, -+ <&clkc CLKID_VID_PLL_FINAL_DIV>; -+ -+ clocks = <&clkc CLKID_VPU_INTR>, -+ <&clkc CLKID_HDMI_INTR_SYNC>, -+ <&clkc CLKID_GCLK_VENCI_INT>, -+ <&clkc CLKID_HDMI_PLL_HDMI_OUT>, -+ <&clkc CLKID_HDMI_TX_PIXEL>, -+ <&clkc CLKID_CTS_ENCP>, -+ <&clkc CLKID_CTS_ENCI>, -+ <&clkc CLKID_CTS_ENCT>, -+ <&clkc CLKID_CTS_ENCL>, -+ <&clkc CLKID_CTS_VDAC0>; -+ clock-names = "vpu_intr", -+ "hdmi_intr_sync", -+ "venci_int", -+ "tmds", -+ "hdmi_tx_pixel", -+ "cts_encp", -+ "cts_enci", -+ "cts_enct", -+ "cts_encl", -+ "cts_vdac0"; -+ -+ resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; -+ reset-names = "vid_pll_pre", -+ "vid_pll_post", -+ "vid_pll_soft_pre", -+ "vid_pll_soft_post"; -+ -+ phys = <&cvbs_dac>; -+ phy-names = "cvbs-dac"; -+ -+ power-domains = <&pwrc PWRC_MESON8_VPU_ID>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* CVBS VDAC output port */ -+ cvbs_vdac_port: port@0 { -+ reg = <0>; -+ }; -+ -+ /* HDMI-TX output port */ -+ hdmi_tx_port: port@1 { -+ reg = <1>; -+ -+ hdmi_tx_out: endpoint { -+ remote-endpoint = <&hdmi_tx_in>; -+ }; -+ }; -+ }; - }; - }; /* end of / */ - -@@ -363,6 +470,14 @@ gpio_ao: ao-bank@14 { - gpio-ranges = <&pinctrl_aobus 0 0 16>; - }; - -+ hdmi_cec_ao_pins: hdmi-cec-ao { -+ mux { -+ groups = "hdmi_cec_ao"; -+ function = "hdmi_cec_ao"; -+ bias-pull-up; -+ }; -+ }; -+ - i2s_am_clk_pins: i2s-am-clk-out { - mux { - groups = "i2s_am_clk_out_ao"; -@@ -427,6 +542,15 @@ mux { - }; - }; - }; -+ -+ cec_AO: cec@100 { -+ compatible = "amlogic,meson-gx-ao-cec"; // FIXME -+ reg = <0x100 0x14>; -+ interrupts = ; -+ // TODO: 32768HZ clock -+ hdmi-phandle = <&hdmi_tx>; -+ status = "disabled"; -+ }; - }; - - &ao_arc_rproc { -@@ -479,6 +603,22 @@ gpio: banks@80b0 { - gpio-ranges = <&pinctrl_cbus 0 0 120>; - }; - -+ hdmi_hpd_pins: hdmi-hpd { -+ mux { -+ groups = "hdmi_hpd"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ -+ hdmi_i2c_pins: hdmi-i2c { -+ mux { -+ groups = "hdmi_sda", "hdmi_scl"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ - sd_a_pins: sd-a { - mux { - groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", -@@ -584,6 +724,17 @@ smp-sram@1ff80 { - }; - }; - -+&cvbs_dac { -+ compatible = "amlogic,meson8-cvbs-dac", "amlogic,meson-cvbs-dac"; -+ -+ clocks = <&clkc CLKID_CTS_VDAC0>; -+ -+ nvmem-cells = <&cvbs_trimming>; -+ nvmem-cell-names = "cvbs_trimming"; -+ -+ status = "okay"; -+}; -+ - &efuse { - compatible = "amlogic,meson8-efuse"; - clocks = <&clkc CLKID_EFUSE>; -@@ -593,6 +744,10 @@ temperature_calib: calib@1f4 { - /* only the upper two bytes are relevant */ - reg = <0x1f4 0x4>; - }; -+ -+ cvbs_trimming: calib@1f8 { -+ reg = <0x1f8 0x2>; -+ }; - }; - - ðmac { -@@ -608,16 +763,18 @@ &gpio_intc { - }; - - &hhi { -- clkc: clock-controller { -+ clkc: clock-controller@0 { - compatible = "amlogic,meson8-clkc"; -+ reg = <0x0 0x39c>; - clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; - clock-names = "xtal", "ddr_pll"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -- pwrc: power-controller { -+ pwrc: power-controller@100 { - compatible = "amlogic,meson8-pwrc"; -+ reg = <0x100 0x10>; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&pmu>; - clocks = <&clkc CLKID_VPU>; -@@ -625,6 +782,13 @@ pwrc: power-controller { - assigned-clocks = <&clkc CLKID_VPU>; - assigned-clock-rates = <364285714>; - }; -+ -+ hdmi_tx_phy: hdmi-phy@3a0 { -+ compatible = "amlogic,meson8-hdmi-tx-phy"; -+ clocks = <&clkc CLKID_HDMI_PLL_HDMI_OUT>; -+ reg = <0x3a0 0xc>; -+ #phy-cells = <0>; -+ }; - }; - - &hwrng { -diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi -index 94f1c03decce..5519086a1887 100644 ---- a/arch/arm/boot/dts/meson8b.dtsi -+++ b/arch/arm/boot/dts/meson8b.dtsi -@@ -276,6 +276,116 @@ mali: gpu@c0000 { - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; -+ -+ hdmi_tx: hdmi-tx@42000 { -+ compatible = "amlogic,meson8b-hdmi-tx"; -+ reg = <0x42000 0xc>; -+ interrupts = ; -+ phys = <&hdmi_tx_phy>; -+ phy-names = "hdmi"; -+ clocks = <&clkc CLKID_HDMI_PCLK>, -+ <&clkc CLKID_HDMI_SYS>; -+ clock-names = "pclk", "sys"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ #sound-dai-cells = <1>; -+ sound-name-prefix = "HDMITX"; -+ -+ status = "disabled"; -+ -+ /* VPU VENC Input */ -+ hdmi_tx_venc_port: port@0 { -+ reg = <0>; -+ -+ hdmi_tx_in: endpoint { -+ remote-endpoint = <&hdmi_tx_out>; -+ }; -+ }; -+ -+ /* TMDS Output */ -+ hdmi_tx_tmds_port: port@1 { -+ reg = <1>; -+ }; -+ }; -+ -+ vpu: vpu@100000 { -+ compatible = "amlogic,meson8b-vpu"; -+ -+ reg = <0x100000 0x10000>; -+ reg-names = "vpu"; -+ -+ interrupts = ; -+ -+ amlogic,canvas = <&canvas>; -+ -+ /* -+ * The VCLK{,2}_IN path always needs to derived from -+ * the CLKID_VID_PLL_FINAL_DIV so other clocks like -+ * MPLL1 are not used (MPLL1 is reserved for audio -+ * purposes). -+ */ -+ assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>, -+ <&clkc CLKID_VCLK2_IN_SEL>; -+ assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>, -+ <&clkc CLKID_VID_PLL_FINAL_DIV>; -+ -+ clocks = <&clkc CLKID_VPU_INTR>, -+ <&clkc CLKID_HDMI_INTR_SYNC>, -+ <&clkc CLKID_GCLK_VENCI_INT>, -+ <&clkc CLKID_HDMI_PLL_HDMI_OUT>, -+ <&clkc CLKID_HDMI_TX_PIXEL>, -+ <&clkc CLKID_CTS_ENCP>, -+ <&clkc CLKID_CTS_ENCI>, -+ <&clkc CLKID_CTS_ENCT>, -+ <&clkc CLKID_CTS_ENCL>, -+ <&clkc CLKID_CTS_VDAC0>; -+ clock-names = "vpu_intr", -+ "hdmi_intr_sync", -+ "venci_int", -+ "tmds", -+ "hdmi_tx_pixel", -+ "cts_encp", -+ "cts_enci", -+ "cts_enct", -+ "cts_encl", -+ "cts_vdac0"; -+ -+ resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; -+ reset-names = "vid_pll_pre", -+ "vid_pll_post", -+ "vid_pll_soft_pre", -+ "vid_pll_soft_post"; -+ -+ phys = <&cvbs_dac>; -+ phy-names = "cvbs-dac"; -+ -+ power-domains = <&pwrc PWRC_MESON8_VPU_ID>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ #sound-dai-cells = <0>; -+ sound-name-prefix = "HDMITX"; -+ -+ /* CVBS VDAC output port */ -+ cvbs_vdac_port: port@0 { -+ reg = <0>; -+ }; -+ -+ /* HDMI-TX output port */ -+ hdmi_tx_port: port@1 { -+ reg = <1>; -+ -+ hdmi_tx_out: endpoint { -+ remote-endpoint = <&hdmi_tx_in>; -+ }; -+ }; -+ }; - }; - }; /* end of / */ - -@@ -325,6 +435,14 @@ gpio_ao: ao-bank@14 { - gpio-ranges = <&pinctrl_aobus 0 0 16>; - }; - -+ hdmi_cec_ao_pins: hdmi-cec-ao { -+ mux { -+ groups = "hdmi_cec_1"; -+ function = "hdmi_cec"; -+ bias-pull-up; -+ }; -+ }; -+ - i2s_am_clk_pins: i2s-am-clk-out { - mux { - groups = "i2s_am_clk_out"; -@@ -381,6 +499,15 @@ mux { - }; - }; - }; -+ -+ cec_AO: cec@100 { -+ compatible = "amlogic,meson-gx-ao-cec"; // FIXME -+ reg = <0x100 0x14>; -+ interrupts = ; -+ // TODO: 32768HZ clock -+ hdmi-phandle = <&hdmi_tx>; -+ status = "disabled"; -+ }; - }; - - &ao_arc_rproc { -@@ -471,6 +598,22 @@ mux { - }; - }; - -+ hdmi_hpd_pins: hdmi-hpd { -+ mux { -+ groups = "hdmi_hpd"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ -+ hdmi_i2c_pins: hdmi-i2c { -+ mux { -+ groups = "hdmi_sda", "hdmi_scl"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ - i2c_a_pins: i2c-a { - mux { - groups = "i2c_sda_a", "i2c_sck_a"; -@@ -547,6 +690,16 @@ smp-sram@1ff80 { - }; - }; - -+&cvbs_dac { -+ compatible = "amlogic,meson8-cvbs-dac", "amlogic,meson-cvbs-dac"; -+ -+ clocks = <&clkc CLKID_CTS_VDAC0>; -+ -+ nvmem-cells = <&cvbs_trimming>; -+ nvmem-cell-names = "cvbs_trimming"; -+ -+ status = "okay"; -+}; - - &efuse { - compatible = "amlogic,meson8b-efuse"; -@@ -557,6 +710,10 @@ temperature_calib: calib@1f4 { - /* only the upper two bytes are relevant */ - reg = <0x1f4 0x4>; - }; -+ -+ cvbs_trimming: calib@1f8 { -+ reg = <0x1f8 0x2>; -+ }; - }; - - ðmac { -@@ -586,16 +743,18 @@ &gpio_intc { - }; - - &hhi { -- clkc: clock-controller { -+ clkc: clock-controller@0 { - compatible = "amlogic,meson8b-clkc"; -+ reg = <0x0 0x39c>; - clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; - clock-names = "xtal", "ddr_pll"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -- pwrc: power-controller { -+ pwrc: power-controller@100 { - compatible = "amlogic,meson8b-pwrc"; -+ reg = <0x100 0x10>; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&pmu>; - resets = <&reset RESET_DBLK>, -@@ -617,6 +776,14 @@ pwrc: power-controller { - assigned-clocks = <&clkc CLKID_VPU>; - assigned-clock-rates = <182142857>; - }; -+ -+ hdmi_tx_phy: hdmi-phy@3a0 { -+ compatible = "amlogic,meson8b-hdmi-tx-phy", -+ "amlogic,meson8-hdmi-tx-phy"; -+ clocks = <&clkc CLKID_HDMI_PLL_HDMI_OUT>; -+ reg = <0x3a0 0xc>; -+ #phy-cells = <0>; -+ }; - }; - - &hwrng { -diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi -index 6725dd9fd825..fcb2ad976098 100644 ---- a/arch/arm/boot/dts/meson8m2.dtsi -+++ b/arch/arm/boot/dts/meson8m2.dtsi -@@ -96,6 +96,10 @@ &usb1_phy { - compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; - }; - -+&vpu { -+ compatible = "amlogic,meson8m2-vpu"; -+}; -+ - &wdt { - compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; - }; -diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c -index 809a0bfb670d..12e9b6618dbb 100644 ---- a/drivers/clk/meson/meson8b.c -+++ b/drivers/clk/meson/meson8b.c -@@ -118,6 +118,56 @@ static struct clk_regmap meson8b_fixed_pll = { - }, - }; - -+static struct clk_fixed_factor hdmi_pll_dco_in = { -+ .mult = 2, -+ .div = 1, -+ .hw.init = &(struct clk_init_data){ -+ .name = "hdmi_pll_dco_in", -+ .ops = &clk_fixed_factor_ops, -+ .parent_data = &(const struct clk_parent_data) { -+ .fw_name = "xtal", -+ .index = -1, -+ }, -+ .num_parents = 1, -+ }, -+}; -+ -+/* -+ * Taken from the vendor driver for the 2970/2975MHz (both only differ in the -+ * FRAC part in HHI_VID_PLL_CNTL2) where these values are identical for Meson8, -+ * Meson8b and Meson8m2. This doubles the input (or output - it's not clear -+ * which one but the result is the same) clock. The vendor driver additionally -+ * has the following comment about: "optimise HPLL VCO 2.97GHz performance". -+ */ -+static const struct reg_sequence meson8b_hdmi_pll_init_regs[] = { -+ { .reg = HHI_VID_PLL_CNTL2, .def = 0x69c84000 }, -+ { .reg = HHI_VID_PLL_CNTL3, .def = 0x8a46c023 }, -+ { .reg = HHI_VID_PLL_CNTL4, .def = 0x4123b100 }, -+ { .reg = HHI_VID_PLL_CNTL5, .def = 0x00012385 }, -+ { .reg = HHI_VID2_PLL_CNTL2, .def = 0x0430a800 }, -+}; -+ -+static const struct pll_params_table hdmi_pll_params_table[] = { -+ PLL_PARAMS(40, 1), -+ PLL_PARAMS(42, 1), -+ PLL_PARAMS(44, 1), -+ PLL_PARAMS(45, 1), -+ PLL_PARAMS(49, 1), -+ PLL_PARAMS(52, 1), -+ PLL_PARAMS(54, 1), -+ PLL_PARAMS(56, 1), -+ PLL_PARAMS(59, 1), -+ PLL_PARAMS(60, 1), -+ PLL_PARAMS(61, 1), -+ PLL_PARAMS(62, 1), -+ PLL_PARAMS(64, 1), -+ PLL_PARAMS(66, 1), -+ PLL_PARAMS(68, 1), -+ PLL_PARAMS(71, 1), -+ PLL_PARAMS(82, 1), -+ { /* sentinel */ } -+}; -+ - static struct clk_regmap meson8b_hdmi_pll_dco = { - .data = &(struct meson_clk_pll_data){ - .en = { -@@ -150,15 +200,16 @@ static struct clk_regmap meson8b_hdmi_pll_dco = { - .shift = 29, - .width = 1, - }, -+ .table = hdmi_pll_params_table, -+ .init_regs = meson8b_hdmi_pll_init_regs, -+ .init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs), - }, - .hw.init = &(struct clk_init_data){ - /* sometimes also called "HPLL" or "HPLL PLL" */ - .name = "hdmi_pll_dco", -- .ops = &meson_clk_pll_ro_ops, -- .parent_data = &(const struct clk_parent_data) { -- .fw_name = "xtal", -- .name = "xtal", -- .index = -1, -+ .ops = &meson_clk_pll_ops, -+ .parent_hws = (const struct clk_hw *[]) { -+ &hdmi_pll_dco_in.hw - }, - .num_parents = 1, - }, -@@ -173,7 +224,7 @@ static struct clk_regmap meson8b_hdmi_pll_lvds_out = { - }, - .hw.init = &(struct clk_init_data){ - .name = "hdmi_pll_lvds_out", -- .ops = &clk_regmap_divider_ro_ops, -+ .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_hdmi_pll_dco.hw - }, -@@ -191,7 +242,7 @@ static struct clk_regmap meson8b_hdmi_pll_hdmi_out = { - }, - .hw.init = &(struct clk_init_data){ - .name = "hdmi_pll_hdmi_out", -- .ops = &clk_regmap_divider_ro_ops, -+ .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_hdmi_pll_dco.hw - }, -@@ -1045,6 +1096,23 @@ static struct clk_regmap meson8b_l2_dram_clk_gate = { - }, - }; - -+/* also called LVDS_CLK_EN */ -+static struct clk_regmap meson8b_vid_pll_lvds_en = { -+ .data = &(struct clk_regmap_gate_data){ -+ .offset = HHI_VID_DIVIDER_CNTL, -+ .bit_idx = 11, -+ }, -+ .hw.init = &(struct clk_init_data){ -+ .name = "vid_pll_lvds_en", -+ .ops = &clk_regmap_gate_ops, -+ .parent_hws = (const struct clk_hw *[]) { -+ &meson8b_hdmi_pll_lvds_out.hw -+ }, -+ .num_parents = 1, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+}; -+ - static struct clk_regmap meson8b_vid_pll_in_sel = { - .data = &(struct clk_regmap_mux_data){ - .offset = HHI_VID_DIVIDER_CNTL, -@@ -1053,7 +1121,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll_in_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - /* - * TODO: depending on the SoC there is also a second parent: - * Meson8: unknown -@@ -1061,7 +1129,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { - * Meson8m2: vid2_pll - */ - .parent_hws = (const struct clk_hw *[]) { -- &meson8b_hdmi_pll_lvds_out.hw -+ &meson8b_vid_pll_lvds_en.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, -@@ -1075,7 +1143,7 @@ static struct clk_regmap meson8b_vid_pll_in_en = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll_in_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vid_pll_in_sel.hw - }, -@@ -1092,7 +1160,7 @@ static struct clk_regmap meson8b_vid_pll_pre_div = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll_pre_div", -- .ops = &clk_regmap_divider_ro_ops, -+ .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vid_pll_in_en.hw - }, -@@ -1109,7 +1177,7 @@ static struct clk_regmap meson8b_vid_pll_post_div = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll_post_div", -- .ops = &clk_regmap_divider_ro_ops, -+ .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vid_pll_pre_div.hw - }, -@@ -1126,7 +1194,7 @@ static struct clk_regmap meson8b_vid_pll = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */ - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vid_pll_pre_div.hw, -@@ -1145,7 +1213,7 @@ static struct clk_regmap meson8b_vid_pll_final_div = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll_final_div", -- .ops = &clk_regmap_divider_ro_ops, -+ .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vid_pll.hw - }, -@@ -1172,10 +1240,10 @@ static struct clk_regmap meson8b_vclk_in_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_in_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - }, - }; - -@@ -1186,7 +1254,7 @@ static struct clk_regmap meson8b_vclk_in_en = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_in_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_in_sel.hw - }, -@@ -1202,7 +1270,7 @@ static struct clk_regmap meson8b_vclk_en = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_in_en.hw - }, -@@ -1218,7 +1286,7 @@ static struct clk_regmap meson8b_vclk_div1_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_div1_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_en.hw - }, -@@ -1248,7 +1316,7 @@ static struct clk_regmap meson8b_vclk_div2_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_div2_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_div2_div.hw - }, -@@ -1278,7 +1346,7 @@ static struct clk_regmap meson8b_vclk_div4_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_div4_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_div4_div.hw - }, -@@ -1308,7 +1376,7 @@ static struct clk_regmap meson8b_vclk_div6_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_div6_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_div6_div.hw - }, -@@ -1338,7 +1406,7 @@ static struct clk_regmap meson8b_vclk_div12_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_div12_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_div12_div.hw - }, -@@ -1355,10 +1423,10 @@ static struct clk_regmap meson8b_vclk2_in_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_in_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - }, - }; - -@@ -1369,7 +1437,7 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_in_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_in_sel.hw - }, -@@ -1385,7 +1453,7 @@ static struct clk_regmap meson8b_vclk2_clk_en = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_clk_in_en.hw - }, -@@ -1401,7 +1469,7 @@ static struct clk_regmap meson8b_vclk2_div1_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_div1_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw - }, -@@ -1431,7 +1499,7 @@ static struct clk_regmap meson8b_vclk2_div2_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_div2_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_div2_div.hw - }, -@@ -1461,7 +1529,7 @@ static struct clk_regmap meson8b_vclk2_div4_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_div4_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_div4_div.hw - }, -@@ -1491,7 +1559,7 @@ static struct clk_regmap meson8b_vclk2_div6_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_div6_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_div6_div.hw - }, -@@ -1521,7 +1589,7 @@ static struct clk_regmap meson8b_vclk2_div12_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_div12_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_div12_div.hw - }, -@@ -1546,7 +1614,7 @@ static struct clk_regmap meson8b_cts_enct_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_enct_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1560,7 +1628,7 @@ static struct clk_regmap meson8b_cts_enct = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_enct", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cts_enct_sel.hw - }, -@@ -1577,7 +1645,7 @@ static struct clk_regmap meson8b_cts_encp_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_encp_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1591,7 +1659,7 @@ static struct clk_regmap meson8b_cts_encp = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_encp", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cts_encp_sel.hw - }, -@@ -1608,7 +1676,7 @@ static struct clk_regmap meson8b_cts_enci_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_enci_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1622,7 +1690,7 @@ static struct clk_regmap meson8b_cts_enci = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_enci", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cts_enci_sel.hw - }, -@@ -1639,7 +1707,7 @@ static struct clk_regmap meson8b_hdmi_tx_pixel_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "hdmi_tx_pixel_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1653,7 +1721,7 @@ static struct clk_regmap meson8b_hdmi_tx_pixel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "hdmi_tx_pixel", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_hdmi_tx_pixel_sel.hw - }, -@@ -1678,7 +1746,7 @@ static struct clk_regmap meson8b_cts_encl_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_encl_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk2_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1692,7 +1760,7 @@ static struct clk_regmap meson8b_cts_encl = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_encl", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cts_encl_sel.hw - }, -@@ -1709,7 +1777,7 @@ static struct clk_regmap meson8b_cts_vdac0_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_vdac0_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk2_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1723,7 +1791,7 @@ static struct clk_regmap meson8b_cts_vdac0 = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_vdac0", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cts_vdac0_sel.hw - }, -@@ -2905,6 +2973,8 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = { - [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, - [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, - [CLKID_CTS_I958] = &meson8b_cts_i958.hw, -+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, -+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, - [CLK_NR_CLKS] = NULL, - }, - .num = CLK_NR_CLKS, -@@ -3122,6 +3192,8 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { - [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, - [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, - [CLKID_CTS_I958] = &meson8b_cts_i958.hw, -+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, -+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, - [CLK_NR_CLKS] = NULL, - }, - .num = CLK_NR_CLKS, -@@ -3341,6 +3413,8 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = { - [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, - [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, - [CLKID_CTS_I958] = &meson8b_cts_i958.hw, -+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, -+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, - [CLK_NR_CLKS] = NULL, - }, - .num = CLK_NR_CLKS, -@@ -3539,6 +3613,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { - &meson8b_cts_mclk_i958_div, - &meson8b_cts_mclk_i958, - &meson8b_cts_i958, -+ &meson8b_vid_pll_lvds_en, - }; - - static const struct meson8b_clk_reset_line { -diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h -index b1a5074cf148..ce62ed47cbfc 100644 ---- a/drivers/clk/meson/meson8b.h -+++ b/drivers/clk/meson/meson8b.h -@@ -51,6 +51,16 @@ - #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ - #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ - #define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ -+#define HHI_VID_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ -+#define HHI_VID_PLL_CNTL4 0x32c /* 0xcb offset in data sheet */ -+#define HHI_VID_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ -+#define HHI_VID_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ -+#define HHI_VID2_PLL_CNTL 0x380 /* 0xe0 offset in data sheet */ -+#define HHI_VID2_PLL_CNTL2 0x384 /* 0xe1 offset in data sheet */ -+#define HHI_VID2_PLL_CNTL3 0x388 /* 0xe2 offset in data sheet */ -+#define HHI_VID2_PLL_CNTL4 0x38c /* 0xe3 offset in data sheet */ -+#define HHI_VID2_PLL_CNTL5 0x390 /* 0xe4 offset in data sheet */ -+#define HHI_VID2_PLL_CNTL6 0x394 /* 0xe5 offset in data sheet */ - - /* - * MPLL register offeset taken from the S905 datasheet. Vendor kernel source -@@ -107,14 +117,11 @@ - #define CLKID_PERIPH_SEL 125 - #define CLKID_AXI_SEL 127 - #define CLKID_L2_DRAM_SEL 129 --#define CLKID_HDMI_PLL_LVDS_OUT 131 --#define CLKID_HDMI_PLL_HDMI_OUT 132 -+#define CLKID_HDMI_PLL_LVDS_OUT 131 - #define CLKID_VID_PLL_IN_SEL 133 - #define CLKID_VID_PLL_IN_EN 134 - #define CLKID_VID_PLL_PRE_DIV 135 - #define CLKID_VID_PLL_POST_DIV 136 --#define CLKID_VID_PLL_FINAL_DIV 137 --#define CLKID_VCLK_IN_SEL 138 - #define CLKID_VCLK_IN_EN 139 - #define CLKID_VCLK_DIV1 140 - #define CLKID_VCLK_DIV2_DIV 141 -@@ -125,7 +132,6 @@ - #define CLKID_VCLK_DIV6 146 - #define CLKID_VCLK_DIV12_DIV 147 - #define CLKID_VCLK_DIV12 148 --#define CLKID_VCLK2_IN_SEL 149 - #define CLKID_VCLK2_IN_EN 150 - #define CLKID_VCLK2_DIV1 151 - #define CLKID_VCLK2_DIV2_DIV 152 -@@ -137,17 +143,11 @@ - #define CLKID_VCLK2_DIV12_DIV 158 - #define CLKID_VCLK2_DIV12 159 - #define CLKID_CTS_ENCT_SEL 160 --#define CLKID_CTS_ENCT 161 - #define CLKID_CTS_ENCP_SEL 162 --#define CLKID_CTS_ENCP 163 - #define CLKID_CTS_ENCI_SEL 164 --#define CLKID_CTS_ENCI 165 - #define CLKID_HDMI_TX_PIXEL_SEL 166 --#define CLKID_HDMI_TX_PIXEL 167 - #define CLKID_CTS_ENCL_SEL 168 --#define CLKID_CTS_ENCL 169 - #define CLKID_CTS_VDAC0_SEL 170 --#define CLKID_CTS_VDAC0 171 - #define CLKID_HDMI_SYS_SEL 172 - #define CLKID_HDMI_SYS_DIV 173 - #define CLKID_MALI_0_SEL 175 -@@ -182,8 +182,10 @@ - #define CLKID_CTS_MCLK_I958_DIV 211 - #define CLKID_VCLK_EN 214 - #define CLKID_VCLK2_EN 215 -+#define CLKID_VID_PLL_LVDS_EN 216 -+#define CLKID_HDMI_PLL_DCO_IN 217 - --#define CLK_NR_CLKS 216 -+#define CLK_NR_CLKS 218 - - /* - * include the CLKID and RESETID that have -diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig -index a4e1ed96e5e8..2023bc2b4dec 100644 ---- a/drivers/gpu/drm/meson/Kconfig -+++ b/drivers/gpu/drm/meson/Kconfig -@@ -18,3 +18,11 @@ config DRM_MESON_DW_HDMI - default y if DRM_MESON - select DRM_DW_HDMI - imply DRM_DW_HDMI_I2S_AUDIO -+ -+config DRM_MESON_TRANSWITCH_HDMI -+ tristate "Amlogic Meson8/8b/8m2 TranSwitch HDMI 1.4 Controller support" -+ depends on ARM || COMPILE_TEST -+ depends on DRM_MESON -+ default y if DRM_MESON -+ select REGMAP_MMIO -+ select SND_SOC_HDMI_CODEC if SND_SOC -diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile -index 523fce45f16b..817a5270aee6 100644 ---- a/drivers/gpu/drm/meson/Makefile -+++ b/drivers/gpu/drm/meson/Makefile -@@ -1,8 +1,9 @@ - # SPDX-License-Identifier: GPL-2.0-only --meson-drm-y := meson_drv.o meson_plane.o meson_crtc.o meson_venc_cvbs.o -+meson-drm-y := meson_drv.o meson_plane.o meson_crtc.o meson_encoder_cvbs.o - meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_overlay.o - meson-drm-y += meson_rdma.o meson_osd_afbcd.o - meson-drm-y += meson_encoder_hdmi.o - - obj-$(CONFIG_DRM_MESON) += meson-drm.o - obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o -+obj-$(CONFIG_DRM_MESON_TRANSWITCH_HDMI) += meson_transwitch_hdmi.o -diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c -index 6e37de4fcb46..71d4cdc57d58 100644 ---- a/drivers/gpu/drm/meson/meson_drv.c -+++ b/drivers/gpu/drm/meson/meson_drv.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -31,7 +32,7 @@ - #include "meson_plane.h" - #include "meson_osd_afbcd.h" - #include "meson_registers.h" --#include "meson_venc_cvbs.h" -+#include "meson_encoder_cvbs.h" - #include "meson_encoder_hdmi.h" - #include "meson_viu.h" - #include "meson_vpp.h" -@@ -133,28 +134,100 @@ static struct regmap_config meson_regmap_config = { - - static void meson_vpu_init(struct meson_drm *priv) - { -- u32 value; -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG0)); -+ writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG1)); -+ } else { -+ u32 value; -+ -+ /* -+ * Slave dc0 and dc5 connected to master port 1. -+ * By default other slaves are connected to master port 0. -+ */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) | -+ VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); -+ -+ /* Slave dc0 connected to master port 1 */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); -+ -+ /* Slave dc4 and dc7 connected to master port 1 */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) | -+ VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); -+ -+ /* Slave dc1 connected to master port 1 */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); -+ } -+} -+ -+static int meson_video_clock_init(struct meson_drm *priv) -+{ -+ int ret; -+ -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ return 0; -+ -+ ret = clk_bulk_prepare(VPU_VID_CLK_NUM, priv->vid_clks); -+ if (ret) -+ return dev_err_probe(priv->dev, ret, -+ "Failed to prepare the video clocks\n"); -+ -+ ret = clk_bulk_prepare(VPU_INTR_CLK_NUM, priv->intr_clks); -+ if (ret) -+ return dev_err_probe(priv->dev, ret, -+ "Failed to prepare the interrupt clocks\n"); -+ -+ return 0; -+} -+ -+static void meson_video_clock_exit(struct meson_drm *priv) -+{ -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ return; -+ -+ if (priv->clk_dac_enabled) -+ clk_disable(priv->clk_dac); -+ -+ if (priv->clk_venc_enabled) -+ clk_disable(priv->clk_venc); -+ -+ clk_bulk_unprepare(VPU_INTR_CLK_NUM, priv->intr_clks); -+ clk_bulk_unprepare(VPU_VID_CLK_NUM, priv->vid_clks); -+} -+ -+static void meson_fbdev_setup(struct meson_drm *priv) -+{ -+ unsigned int preferred_bpp; - - /* -- * Slave dc0 and dc5 connected to master port 1. -- * By default other slaves are connected to master port 0. -+ * All SoC generations before GXBB don't have a way to configure the -+ * alpha value for DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888 with -+ * 32-bit but missing alpha ??? TODO: better explanation here. -+ * Use 24-bit to get a working framebuffer console. Applications that -+ * can do better (for example: kmscube) will switch to a better format -+ * like DRM_FORMAT_XRGB8888 while passing a sane alpha value. - */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) | -- VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); -- -- /* Slave dc0 connected to master port 1 */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); -- -- /* Slave dc4 and dc7 connected to master port 1 */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) | -- VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); -- -- /* Slave dc1 connected to master port 1 */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ preferred_bpp = 24; -+ else -+ preferred_bpp = 32; -+ -+ drm_fbdev_generic_setup(priv->drm, preferred_bpp); - } - - struct meson_drm_soc_attr { -@@ -163,6 +236,16 @@ struct meson_drm_soc_attr { - }; - - static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = { -+ /* The maximum frequency of HDMI PLL on Meson8/8b/8m2 is ~3GHz */ -+ { -+ .limits = { -+ .max_hdmi_phy_freq = 2976000, -+ }, -+ .attrs = (const struct soc_device_attribute []) { -+ { .soc_id = "Meson8*", }, -+ { /* sentinel */ }, -+ } -+ }, - /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */ - { - .limits = { -@@ -210,6 +293,46 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - priv->compat = match->compat; - priv->afbcd.ops = match->afbcd_ops; - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ priv->vid_pll_resets[VPU_RESET_VID_PLL_PRE].id = "vid_pll_pre"; -+ priv->vid_pll_resets[VPU_RESET_VID_PLL_POST].id = "vid_pll_post"; -+ priv->vid_pll_resets[VPU_RESET_VID_PLL_SOFT_PRE].id = "vid_pll_soft_pre"; -+ priv->vid_pll_resets[VPU_RESET_VID_PLL_SOFT_POST].id = "vid_pll_soft_post"; -+ -+ ret = devm_reset_control_bulk_get_exclusive(dev, -+ VPU_RESET_VID_PLL_NUM, -+ priv->vid_pll_resets); -+ if (ret) -+ return ret; -+ -+ priv->intr_clks[VPU_INTR_CLK_VPU].id = "vpu_intr"; -+ priv->intr_clks[VPU_INTR_CLK_HDMI_INTR_SYNC].id = "hdmi_intr_sync"; -+ priv->intr_clks[VPU_INTR_CLK_VENCI].id = "venci_int"; -+ -+ ret = devm_clk_bulk_get(dev, VPU_INTR_CLK_NUM, priv->intr_clks); -+ if (ret) -+ return ret; -+ -+ priv->vid_clks[VPU_VID_CLK_TMDS].id = "tmds"; -+ priv->vid_clks[VPU_VID_CLK_HDMI_TX_PIXEL].id = "hdmi_tx_pixel"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCP].id = "cts_encp"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCI].id = "cts_enci"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCT].id = "cts_enct"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCL].id = "cts_encl"; -+ priv->vid_clks[VPU_VID_CLK_CTS_VDAC0].id = "cts_vdac0"; -+ -+ ret = devm_clk_bulk_get(dev, VPU_VID_CLK_NUM, priv->vid_clks); -+ if (ret) -+ return ret; -+ -+ ret = meson_video_clock_init(priv); -+ if (ret) -+ goto free_drm; -+ // TODO: error handling below -+ } -+ - regs = devm_platform_ioremap_resource_byname(pdev, "vpu"); - if (IS_ERR(regs)) { - ret = PTR_ERR(regs); -@@ -218,24 +341,27 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - - priv->io_base = regs; - -+ /* -+ * The HHI resource is optional because it contains the clocks and CVBS -+ * encoder registers. These are managed by separate drivers though. -+ */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi"); -- if (!res) { -- ret = -EINVAL; -- goto free_drm; -- } -- /* Simply ioremap since it may be a shared register zone */ -- regs = devm_ioremap(dev, res->start, resource_size(res)); -- if (!regs) { -- ret = -EADDRNOTAVAIL; -- goto free_drm; -- } -+ if (res) { -+ /* Simply ioremap since it may be a shared register zone */ -+ regs = devm_ioremap(dev, res->start, resource_size(res)); -+ if (!regs) { -+ ret = -EADDRNOTAVAIL; -+ goto free_drm; -+ } - -- priv->hhi = devm_regmap_init_mmio(dev, regs, -- &meson_regmap_config); -- if (IS_ERR(priv->hhi)) { -- dev_err(&pdev->dev, "Couldn't create the HHI regmap\n"); -- ret = PTR_ERR(priv->hhi); -- goto free_drm; -+ priv->hhi = devm_regmap_init_mmio(dev, regs, -+ &meson_regmap_config); -+ if (IS_ERR(priv->hhi)) { -+ dev_err(&pdev->dev, -+ "Couldn't create the HHI regmap\n"); -+ ret = PTR_ERR(priv->hhi); -+ goto free_drm; -+ } - } - - priv->canvas = meson_canvas_get(dev); -@@ -266,6 +392,11 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - goto free_drm; - } - -+ priv->cvbs_dac = devm_phy_optional_get(dev, "cvbs-dac"); -+ if (IS_ERR(priv->cvbs_dac)) -+ return dev_err_probe(dev, PTR_ERR(priv->cvbs_dac), -+ "Failed to get the 'cvbs-dac' PHY\n"); -+ - priv->vsync_irq = platform_get_irq(pdev, 0); - - ret = drm_vblank_init(drm, 1); -@@ -310,7 +441,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - - /* Encoder Initialization */ - -- ret = meson_venc_cvbs_create(priv); -+ ret = meson_encoder_cvbs_init(priv); - if (ret) - goto exit_afbcd; - -@@ -352,7 +483,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - if (ret) - goto uninstall_irq; - -- drm_fbdev_generic_setup(drm, 32); -+ meson_fbdev_setup(priv); - - return 0; - -@@ -407,6 +538,8 @@ static int __maybe_unused meson_drv_pm_suspend(struct device *dev) - if (!priv) - return 0; - -+ // TODO: video clock suspend -+ - return drm_mode_config_helper_suspend(priv->drm); - } - -@@ -417,6 +550,7 @@ static int __maybe_unused meson_drv_pm_resume(struct device *dev) - if (!priv) - return 0; - -+ meson_video_clock_init(priv); - meson_vpu_init(priv); - meson_venc_init(priv); - meson_vpp_init(priv); -@@ -435,46 +569,6 @@ static int compare_of(struct device *dev, void *data) - return dev->of_node == data; - } - --/* Possible connectors nodes to ignore */ --static const struct of_device_id connectors_match[] = { -- { .compatible = "composite-video-connector" }, -- { .compatible = "svideo-connector" }, -- { .compatible = "hdmi-connector" }, -- { .compatible = "dvi-connector" }, -- {} --}; -- --static int meson_probe_remote(struct platform_device *pdev, -- struct component_match **match, -- struct device_node *parent, -- struct device_node *remote) --{ -- struct device_node *ep, *remote_node; -- int count = 1; -- -- /* If node is a connector, return and do not add to match table */ -- if (of_match_node(connectors_match, remote)) -- return 1; -- -- component_match_add(&pdev->dev, match, compare_of, remote); -- -- for_each_endpoint_of_node(remote, ep) { -- remote_node = of_graph_get_remote_port_parent(ep); -- if (!remote_node || -- remote_node == parent || /* Ignore parent endpoint */ -- !of_device_is_available(remote_node)) { -- of_node_put(remote_node); -- continue; -- } -- -- count += meson_probe_remote(pdev, match, remote, remote_node); -- -- of_node_put(remote_node); -- } -- -- return count; --} -- - static void meson_drv_shutdown(struct platform_device *pdev) - { - struct meson_drm *priv = dev_get_drvdata(&pdev->dev); -@@ -486,6 +580,13 @@ static void meson_drv_shutdown(struct platform_device *pdev) - drm_atomic_helper_shutdown(priv->drm); - } - -+/* Possible connectors nodes to ignore */ -+static const struct of_device_id connectors_match[] = { -+ { .compatible = "composite-video-connector" }, -+ { .compatible = "svideo-connector" }, -+ {} -+}; -+ - static int meson_drv_probe(struct platform_device *pdev) - { - struct component_match *match = NULL; -@@ -500,8 +601,21 @@ static int meson_drv_probe(struct platform_device *pdev) - continue; - } - -- count += meson_probe_remote(pdev, &match, np, remote); -+ /* If an analog connector is detected, count it as an output */ -+ if (of_match_node(connectors_match, remote)) { -+ ++count; -+ of_node_put(remote); -+ continue; -+ } -+ -+ dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n", -+ np, remote, dev_name(&pdev->dev)); -+ -+ component_match_add(&pdev->dev, &match, compare_of, remote); -+ - of_node_put(remote); -+ -+ ++count; - } - - if (count && !match) -@@ -527,6 +641,18 @@ static int meson_drv_remove(struct platform_device *pdev) - return 0; - } - -+static struct meson_drm_match_data meson_drm_m8_data = { -+ .compat = VPU_COMPATIBLE_M8, -+}; -+ -+static struct meson_drm_match_data meson_drm_m8b_data = { -+ .compat = VPU_COMPATIBLE_M8B, -+}; -+ -+static struct meson_drm_match_data meson_drm_m8m2_data = { -+ .compat = VPU_COMPATIBLE_M8M2, -+}; -+ - static struct meson_drm_match_data meson_drm_gxbb_data = { - .compat = VPU_COMPATIBLE_GXBB, - }; -@@ -546,6 +672,12 @@ static struct meson_drm_match_data meson_drm_g12a_data = { - }; - - static const struct of_device_id dt_match[] = { -+ { .compatible = "amlogic,meson8-vpu", -+ .data = (void *)&meson_drm_m8_data }, -+ { .compatible = "amlogic,meson8b-vpu", -+ .data = (void *)&meson_drm_m8b_data }, -+ { .compatible = "amlogic,meson8m2-vpu", -+ .data = (void *)&meson_drm_m8m2_data }, - { .compatible = "amlogic,meson-gxbb-vpu", - .data = (void *)&meson_drm_gxbb_data }, - { .compatible = "amlogic,meson-gxl-vpu", -diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h -index 177dac3ca3be..d1250271c94a 100644 ---- a/drivers/gpu/drm/meson/meson_drv.h -+++ b/drivers/gpu/drm/meson/meson_drv.h -@@ -7,22 +7,28 @@ - #ifndef __MESON_DRV_H - #define __MESON_DRV_H - -+#include - #include - #include - #include - #include -+#include - - struct drm_crtc; - struct drm_device; - struct drm_plane; - struct meson_drm; - struct meson_afbcd_ops; -+struct phy; - - enum vpu_compatible { -- VPU_COMPATIBLE_GXBB = 0, -- VPU_COMPATIBLE_GXL = 1, -- VPU_COMPATIBLE_GXM = 2, -- VPU_COMPATIBLE_G12A = 3, -+ VPU_COMPATIBLE_M8 = 0, -+ VPU_COMPATIBLE_M8B = 1, -+ VPU_COMPATIBLE_M8M2 = 2, -+ VPU_COMPATIBLE_GXBB = 3, -+ VPU_COMPATIBLE_GXL = 4, -+ VPU_COMPATIBLE_GXM = 5, -+ VPU_COMPATIBLE_G12A = 6, - }; - - struct meson_drm_match_data { -@@ -34,6 +40,32 @@ struct meson_drm_soc_limits { - unsigned int max_hdmi_phy_freq; - }; - -+enum vpu_bulk_intr_clk_id { -+ VPU_INTR_CLK_VPU = 0, -+ VPU_INTR_CLK_HDMI_INTR_SYNC, -+ VPU_INTR_CLK_VENCI, -+ VPU_INTR_CLK_NUM -+}; -+ -+enum vpu_bulk_clk_id { -+ VPU_VID_CLK_TMDS = 0, -+ VPU_VID_CLK_HDMI_TX_PIXEL, -+ VPU_VID_CLK_CTS_ENCP, -+ VPU_VID_CLK_CTS_ENCI, -+ VPU_VID_CLK_CTS_ENCT, -+ VPU_VID_CLK_CTS_ENCL, -+ VPU_VID_CLK_CTS_VDAC0, -+ VPU_VID_CLK_NUM -+}; -+ -+enum vpu_bulk_vid_pll_reset_id { -+ VPU_RESET_VID_PLL_PRE = 0, -+ VPU_RESET_VID_PLL_POST, -+ VPU_RESET_VID_PLL_SOFT_PRE, -+ VPU_RESET_VID_PLL_SOFT_POST, -+ VPU_RESET_VID_PLL_NUM -+}; -+ - struct meson_drm { - struct device *dev; - enum vpu_compatible compat; -@@ -54,6 +86,19 @@ struct meson_drm { - - const struct meson_drm_soc_limits *limits; - -+ struct phy *cvbs_dac; -+ bool cvbs_dac_enabled; -+ -+ struct clk_bulk_data intr_clks[VPU_INTR_CLK_NUM]; -+ bool intr_clks_enabled; -+ struct clk_bulk_data vid_clks[VPU_VID_CLK_NUM]; -+ bool vid_clk_rate_exclusive[VPU_VID_CLK_NUM]; -+ struct clk *clk_venc; -+ bool clk_venc_enabled; -+ struct clk *clk_dac; -+ bool clk_dac_enabled; -+ struct reset_control_bulk_data vid_pll_resets[VPU_RESET_VID_PLL_NUM]; -+ - /* Components Data */ - struct { - bool osd1_enabled; -diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c -new file mode 100644 -index 000000000000..6cfbf47dbbc1 ---- /dev/null -+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c -@@ -0,0 +1,318 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Copyright (C) 2016 BayLibre, SAS -+ * Author: Neil Armstrong -+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. -+ * Copyright (C) 2014 Endless Mobile -+ * -+ * Written by: -+ * Jasper St. Pierre -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "meson_registers.h" -+#include "meson_vclk.h" -+#include "meson_encoder_cvbs.h" -+ -+/* HHI VDAC Registers */ -+#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ -+#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */ -+#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ -+#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */ -+ -+struct meson_encoder_cvbs { -+ struct drm_encoder encoder; -+ struct drm_bridge bridge; -+ struct drm_bridge *next_bridge; -+ struct meson_drm *priv; -+}; -+ -+#define bridge_to_meson_encoder_cvbs(x) \ -+ container_of(x, struct meson_encoder_cvbs, bridge) -+ -+/* Supported Modes */ -+ -+struct meson_cvbs_mode meson_cvbs_modes[MESON_CVBS_MODES_COUNT] = { -+ { /* PAL */ -+ .enci = &meson_cvbs_enci_pal, -+ .mode = { -+ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, -+ 720, 732, 795, 864, 0, 576, 580, 586, 625, 0, -+ DRM_MODE_FLAG_INTERLACE), -+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, -+ }, -+ }, -+ { /* NTSC */ -+ .enci = &meson_cvbs_enci_ntsc, -+ .mode = { -+ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, -+ 720, 739, 801, 858, 0, 480, 488, 494, 525, 0, -+ DRM_MODE_FLAG_INTERLACE), -+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, -+ }, -+ }, -+}; -+ -+static const struct meson_cvbs_mode * -+meson_cvbs_get_mode(const struct drm_display_mode *req_mode) -+{ -+ int i; -+ -+ for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) { -+ struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i]; -+ -+ if (drm_mode_match(req_mode, &meson_mode->mode, -+ DRM_MODE_MATCH_TIMINGS | -+ DRM_MODE_MATCH_CLOCK | -+ DRM_MODE_MATCH_FLAGS | -+ DRM_MODE_MATCH_3D_FLAGS)) -+ return meson_mode; -+ } -+ -+ return NULL; -+} -+ -+static int meson_encoder_cvbs_attach(struct drm_bridge *bridge, -+ enum drm_bridge_attach_flags flags) -+{ -+ struct meson_encoder_cvbs *meson_encoder_cvbs = -+ bridge_to_meson_encoder_cvbs(bridge); -+ int ret; -+ -+ ret = phy_init(meson_encoder_cvbs->priv->cvbs_dac); -+ if (ret) -+ return ret; -+ -+ return drm_bridge_attach(bridge->encoder, meson_encoder_cvbs->next_bridge, -+ &meson_encoder_cvbs->bridge, flags); -+} -+ -+static void meson_encoder_cvbs_detach(struct drm_bridge *bridge) -+{ -+ struct meson_encoder_cvbs *meson_encoder_cvbs = -+ bridge_to_meson_encoder_cvbs(bridge); -+ int ret; -+ -+ ret = phy_exit(meson_encoder_cvbs->priv->cvbs_dac); -+ if (ret) -+ dev_err(meson_encoder_cvbs->priv->dev, -+ "Failed to exit the CVBS DAC\n"); -+} -+ -+static int meson_encoder_cvbs_get_modes(struct drm_bridge *bridge, -+ struct drm_connector *connector) -+{ -+ struct meson_encoder_cvbs *meson_encoder_cvbs = -+ bridge_to_meson_encoder_cvbs(bridge); -+ struct meson_drm *priv = meson_encoder_cvbs->priv; -+ struct drm_display_mode *mode; -+ int i; -+ -+ for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) { -+ struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i]; -+ -+ mode = drm_mode_duplicate(priv->drm, &meson_mode->mode); -+ if (!mode) { -+ dev_err(priv->dev, "Failed to create a new display mode\n"); -+ return 0; -+ } -+ -+ drm_mode_probed_add(connector, mode); -+ } -+ -+ return i; -+} -+ -+static int meson_encoder_cvbs_mode_valid(struct drm_bridge *bridge, -+ const struct drm_display_info *display_info, -+ const struct drm_display_mode *mode) -+{ -+ if (meson_cvbs_get_mode(mode)) -+ return MODE_OK; -+ -+ return MODE_BAD; -+} -+ -+static int meson_encoder_cvbs_atomic_check(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) -+{ -+ if (meson_cvbs_get_mode(&crtc_state->mode)) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state) -+{ -+ struct meson_encoder_cvbs *encoder_cvbs = bridge_to_meson_encoder_cvbs(bridge); -+ struct drm_atomic_state *state = bridge_state->base.state; -+ struct meson_drm *priv = encoder_cvbs->priv; -+ const struct meson_cvbs_mode *meson_mode; -+ struct drm_connector_state *conn_state; -+ struct drm_crtc_state *crtc_state; -+ struct drm_connector *connector; -+ -+ connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); -+ if (WARN_ON(!connector)) -+ return; -+ -+ conn_state = drm_atomic_get_new_connector_state(state, connector); -+ if (WARN_ON(!conn_state)) -+ return; -+ -+ crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); -+ if (WARN_ON(!crtc_state)) -+ return; -+ -+ meson_mode = meson_cvbs_get_mode(&crtc_state->adjusted_mode); -+ if (WARN_ON(!meson_mode)) -+ return; -+ -+ meson_venci_cvbs_mode_set(priv, meson_mode->enci); -+ -+ /* Setup 27MHz vclk2 for ENCI and VDAC */ -+ meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS, -+ MESON_VCLK_CVBS, MESON_VCLK_CVBS, -+ MESON_VCLK_CVBS, MESON_VCLK_CVBS, -+ true); -+ -+ /* VDAC0 source is not from ATV */ -+ writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0, -+ priv->io_base + _REG(VENC_VDAC_DACSEL0)); -+ -+ if (!priv->cvbs_dac) { -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) -+ regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1); -+ else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) -+ regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001); -+ else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) -+ regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001); -+ -+ regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0x0); -+ } else if (!priv->cvbs_dac_enabled) { -+ int ret = phy_power_on(priv->cvbs_dac); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to power on the CVBS DAC\n"); -+ -+ priv->cvbs_dac_enabled = true; -+ } -+} -+ -+static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state) -+{ -+ struct meson_encoder_cvbs *meson_encoder_cvbs = -+ bridge_to_meson_encoder_cvbs(bridge); -+ struct meson_drm *priv = meson_encoder_cvbs->priv; -+ -+ /* Disable CVBS VDAC */ -+ if (!priv->cvbs_dac) { -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { -+ regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); -+ regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); -+ } else { -+ regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); -+ regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); -+ } -+ } else if (priv->cvbs_dac_enabled) { -+ int ret = phy_power_off(priv->cvbs_dac); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to power off the CVBS DAC\n"); -+ -+ priv->cvbs_dac_enabled = false; -+ } -+} -+ -+static const struct drm_bridge_funcs meson_encoder_cvbs_bridge_funcs = { -+ .attach = meson_encoder_cvbs_attach, -+ .mode_valid = meson_encoder_cvbs_mode_valid, -+ .get_modes = meson_encoder_cvbs_get_modes, -+ .atomic_enable = meson_encoder_cvbs_atomic_enable, -+ .atomic_disable = meson_encoder_cvbs_atomic_disable, -+ .atomic_check = meson_encoder_cvbs_atomic_check, -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_reset = drm_atomic_helper_bridge_reset, -+}; -+ -+int meson_encoder_cvbs_init(struct meson_drm *priv) -+{ -+ struct drm_device *drm = priv->drm; -+ struct meson_encoder_cvbs *meson_encoder_cvbs; -+ struct drm_connector *connector; -+ struct device_node *remote; -+ int ret; -+ -+ meson_encoder_cvbs = devm_kzalloc(priv->dev, sizeof(*meson_encoder_cvbs), GFP_KERNEL); -+ if (!meson_encoder_cvbs) -+ return -ENOMEM; -+ -+ /* CVBS Connector Bridge */ -+ remote = of_graph_get_remote_node(priv->dev->of_node, 0, 0); -+ if (!remote) { -+ dev_info(drm->dev, "CVBS Output connector not available\n"); -+ return 0; -+ } -+ -+ meson_encoder_cvbs->next_bridge = of_drm_find_bridge(remote); -+ if (!meson_encoder_cvbs->next_bridge) { -+ dev_err(priv->dev, "Failed to find CVBS Connector bridge\n"); -+ return -EPROBE_DEFER; -+ } -+ -+ /* CVBS Encoder Bridge */ -+ meson_encoder_cvbs->bridge.funcs = &meson_encoder_cvbs_bridge_funcs; -+ meson_encoder_cvbs->bridge.of_node = priv->dev->of_node; -+ meson_encoder_cvbs->bridge.type = DRM_MODE_CONNECTOR_Composite; -+ meson_encoder_cvbs->bridge.ops = DRM_BRIDGE_OP_MODES; -+ meson_encoder_cvbs->bridge.interlace_allowed = true; -+ -+ drm_bridge_add(&meson_encoder_cvbs->bridge); -+ -+ meson_encoder_cvbs->priv = priv; -+ -+ /* Encoder */ -+ ret = drm_simple_encoder_init(priv->drm, &meson_encoder_cvbs->encoder, -+ DRM_MODE_ENCODER_TVDAC); -+ if (ret) { -+ dev_err(priv->dev, "Failed to init CVBS encoder: %d\n", ret); -+ return ret; -+ } -+ -+ meson_encoder_cvbs->encoder.possible_crtcs = BIT(0); -+ -+ /* Attach CVBS Encoder Bridge to Encoder */ -+ ret = drm_bridge_attach(&meson_encoder_cvbs->encoder, &meson_encoder_cvbs->bridge, NULL, -+ DRM_BRIDGE_ATTACH_NO_CONNECTOR); -+ if (ret) { -+ dev_err(priv->dev, "Failed to attach bridge: %d\n", ret); -+ return ret; -+ } -+ -+ /* Initialize & attach Bridge Connector */ -+ connector = drm_bridge_connector_init(priv->drm, &meson_encoder_cvbs->encoder); -+ if (IS_ERR(connector)) { -+ dev_err(priv->dev, "Unable to create CVBS bridge connector\n"); -+ return PTR_ERR(connector); -+ } -+ drm_connector_attach_encoder(connector, &meson_encoder_cvbs->encoder); -+ -+ return 0; -+} -diff --git a/drivers/gpu/drm/meson/meson_venc_cvbs.h b/drivers/gpu/drm/meson/meson_encoder_cvbs.h -similarity index 92% -rename from drivers/gpu/drm/meson/meson_venc_cvbs.h -rename to drivers/gpu/drm/meson/meson_encoder_cvbs.h -index ab7f76ba469c..61d9d183ce7f 100644 ---- a/drivers/gpu/drm/meson/meson_venc_cvbs.h -+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.h -@@ -24,6 +24,6 @@ struct meson_cvbs_mode { - /* Modes supported by the CVBS output */ - extern struct meson_cvbs_mode meson_cvbs_modes[MESON_CVBS_MODES_COUNT]; - --int meson_venc_cvbs_create(struct meson_drm *priv); -+int meson_encoder_cvbs_init(struct meson_drm *priv); - - #endif /* __MESON_VENC_CVBS_H */ -diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c -index a7692584487c..62c5cde59224 100644 ---- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c -+++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c -@@ -188,13 +188,13 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge, - { - struct meson_encoder_hdmi *encoder_hdmi = bridge_to_meson_encoder_hdmi(bridge); - struct drm_atomic_state *state = bridge_state->base.state; -- unsigned int ycrcb_map = VPU_HDMI_OUTPUT_CBYCR; - struct meson_drm *priv = encoder_hdmi->priv; - struct drm_connector_state *conn_state; - const struct drm_display_mode *mode; - struct drm_crtc_state *crtc_state; - struct drm_connector *connector; - bool yuv420_mode = false; -+ unsigned int ycrcb_map; - int vic; - - connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); -@@ -215,9 +215,18 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge, - - dev_dbg(priv->dev, "\"%s\" vic %d\n", mode->name, vic); - -- if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) { -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_RGB888_1X24) -+ ycrcb_map = VPU_HDMI_OUTPUT_YCBCR; -+ else -+ ycrcb_map = VPU_HDMI_OUTPUT_CRYCB; -+ } else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) { - ycrcb_map = VPU_HDMI_OUTPUT_CRYCB; - yuv420_mode = true; -+ } else { -+ ycrcb_map = VPU_HDMI_OUTPUT_CBYCR; - } - - /* VENC + VENC-DVI Mode setup */ -@@ -426,8 +435,11 @@ int meson_encoder_hdmi_init(struct meson_drm *priv) - - drm_connector_attach_max_bpc_property(meson_encoder_hdmi->connector, 8, 8); - -- /* Handle this here until handled by drm_bridge_connector_init() */ -- meson_encoder_hdmi->connector->ycbcr_420_allowed = true; -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ /* Handle this here until handled by drm_bridge_connector_init() */ -+ meson_encoder_hdmi->connector->ycbcr_420_allowed = true; - - pdev = of_find_device_by_node(remote); - of_node_put(remote); -diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c -index 44aa52629443..c835e6d35568 100644 ---- a/drivers/gpu/drm/meson/meson_plane.c -+++ b/drivers/gpu/drm/meson/meson_plane.c -@@ -199,8 +199,11 @@ static void meson_plane_atomic_update(struct drm_plane *plane, - priv->viu.osd1_ctrl_stat2 &= ~OSD_DPATH_MALI_AFBCD; - } - -- /* On GXBB, Use the old non-HDR RGB2YUV converter */ -- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) -+ /* On GXBB and earlier, Use the old non-HDR RGB2YUV converter */ -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) - priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; - - if (priv->viu.osd1_afbcd && -@@ -231,17 +234,21 @@ static void meson_plane_atomic_update(struct drm_plane *plane, - } - } - -- switch (fb->format->format) { -- case DRM_FORMAT_XRGB8888: -- case DRM_FORMAT_XBGR8888: -- /* For XRGB, replace the pixel's alpha by 0xFF */ -- priv->viu.osd1_ctrl_stat2 |= OSD_REPLACE_EN; -- break; -- case DRM_FORMAT_ARGB8888: -- case DRM_FORMAT_ABGR8888: -- /* For ARGB, use the pixel's alpha */ -- priv->viu.osd1_ctrl_stat2 &= ~OSD_REPLACE_EN; -- break; -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ switch (fb->format->format) { -+ case DRM_FORMAT_XRGB8888: -+ case DRM_FORMAT_XBGR8888: -+ /* For XRGB, replace the pixel's alpha by 0xFF */ -+ priv->viu.osd1_ctrl_stat2 |= OSD_REPLACE_EN; -+ break; -+ case DRM_FORMAT_ARGB8888: -+ case DRM_FORMAT_ABGR8888: -+ /* For ARGB, use the pixel's alpha */ -+ priv->viu.osd1_ctrl_stat2 &= ~OSD_REPLACE_EN; -+ break; -+ } - } - - /* Default scaler parameters */ -diff --git a/drivers/gpu/drm/meson/meson_transwitch_hdmi.c b/drivers/gpu/drm/meson/meson_transwitch_hdmi.c -new file mode 100644 -index 000000000000..f1eab2201690 ---- /dev/null -+++ b/drivers/gpu/drm/meson/meson_transwitch_hdmi.c -@@ -0,0 +1,1602 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2021 Martin Blumenstingl -+ * -+ * All registers and magic values are taken from Amlogic's GPL kernel sources: -+ * Copyright (C) 2010 Amlogic, Inc. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+ -+#include "meson_transwitch_hdmi.h" -+ -+#define HDMI_ADDR_PORT 0x0 -+#define HDMI_DATA_PORT 0x4 -+#define HDMI_CTRL_PORT 0x8 -+ #define HDMI_CTRL_PORT_APB3_ERR_EN BIT(15) -+ -+struct meson_txc_hdmi { -+ struct device *dev; -+ -+ struct regmap *regmap; -+ -+ struct clk *pclk; -+ struct clk *sys_clk; -+ -+ struct phy *phy; -+ bool phy_is_on; -+ -+ struct mutex codec_mutex; -+ enum drm_connector_status last_connector_status; -+ hdmi_codec_plugged_cb codec_plugged_cb; -+ struct device *codec_dev; -+ -+ struct platform_device *hdmi_codec_pdev; -+ uint8_t eld[MAX_ELD_BYTES]; -+ -+ struct drm_connector connector; -+ struct drm_bridge bridge; -+ struct drm_bridge *next_bridge; -+ -+ unsigned int input_bus_format; -+ unsigned int output_bus_format; -+ bool sink_is_hdmi; -+}; -+ -+#define bridge_to_meson_txc_hdmi(x) container_of(x, struct meson_txc_hdmi, bridge) -+ -+static const struct regmap_range meson_txc_hdmi_regmap_ranges[] = { -+ regmap_reg_range(0x0000, 0x07ff), -+ regmap_reg_range(0x8000, 0x800c), -+}; -+ -+static const struct regmap_access_table meson_txc_hdmi_regmap_access = { -+ .yes_ranges = meson_txc_hdmi_regmap_ranges, -+ .n_yes_ranges = ARRAY_SIZE(meson_txc_hdmi_regmap_ranges), -+}; -+ -+static int meson_txc_hdmi_reg_read(void *context, unsigned int addr, -+ unsigned int *data) -+{ -+ void __iomem *base = context; -+ -+ writel(addr, base + HDMI_ADDR_PORT); -+ writel(addr, base + HDMI_ADDR_PORT); -+ -+ *data = readl(base + HDMI_DATA_PORT); -+ -+ return 0; -+} -+ -+static int meson_txc_hdmi_reg_write(void *context, unsigned int addr, -+ unsigned int data) -+{ -+ void __iomem *base = context; -+ -+ writel(addr, base + HDMI_ADDR_PORT); -+ writel(addr, base + HDMI_ADDR_PORT); -+ -+ writel(data, base + HDMI_DATA_PORT); -+ -+ return 0; -+} -+ -+static const struct regmap_config meson_txc_hdmi_regmap_config = { -+ .reg_bits = 16, -+ .val_bits = 16, -+ .reg_stride = 1, -+ .reg_read = meson_txc_hdmi_reg_read, -+ .reg_write = meson_txc_hdmi_reg_write, -+ .rd_table = &meson_txc_hdmi_regmap_access, -+ .wr_table = &meson_txc_hdmi_regmap_access, -+ .max_register = HDMI_OTHER_RX_PACKET_INTR_CLR, -+ .fast_io = true, -+}; -+ -+static void meson_txc_hdmi_write_infoframe(struct regmap *regmap, -+ unsigned int tx_pkt_reg, u8 *buf, -+ unsigned int len, bool enable) -+{ -+ unsigned int i; -+ -+ /* Write the data bytes by starting at register offset 1 */ -+ for (i = HDMI_INFOFRAME_HEADER_SIZE; i < len; i++) -+ regmap_write(regmap, -+ tx_pkt_reg + i - HDMI_INFOFRAME_HEADER_SIZE + 1, -+ buf[i]); -+ -+ /* Zero all remaining data bytes */ -+ for (; i < 0x1c; i++) -+ regmap_write(regmap, tx_pkt_reg + i, 0x00); -+ -+ /* Write the header (which we skipped above) */ -+ regmap_write(regmap, tx_pkt_reg + 0x00, buf[3]); -+ regmap_write(regmap, tx_pkt_reg + 0x1c, buf[0]); -+ regmap_write(regmap, tx_pkt_reg + 0x1d, buf[1]); -+ regmap_write(regmap, tx_pkt_reg + 0x1e, buf[2]); -+ -+ regmap_write(regmap, tx_pkt_reg + 0x1f, enable ? 0xff : 0x00); -+} -+ -+static void meson_txc_hdmi_disable_infoframe(struct meson_txc_hdmi *priv, -+ unsigned int tx_pkt_reg) -+{ -+ u8 buf[HDMI_INFOFRAME_HEADER_SIZE] = { 0 }; -+ -+ meson_txc_hdmi_write_infoframe(priv->regmap, tx_pkt_reg, buf, -+ HDMI_INFOFRAME_HEADER_SIZE, false); -+} -+ -+static void meson_txc_hdmi_sys5_reset_assert(struct meson_txc_hdmi *priv) -+{ -+ /* A comment in the vendor driver says: bit5,6 is converted */ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0); -+ usleep_range(10, 20); -+} -+ -+static void meson_txc_hdmi_sys5_reset_deassert(struct meson_txc_hdmi *priv) -+{ -+ /* Release the resets except tmds_clk */ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN); -+ usleep_range(10, 20); -+ -+ /* Release the tmds_clk reset as well */ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x0); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN); -+ usleep_range(10, 20); -+} -+ -+static void meson_txc_hdmi_config_hdcp_registers(struct meson_txc_hdmi *priv) -+{ -+ regmap_write(priv->regmap, TX_HDCP_CONFIG0, -+ FIELD_PREP(TX_HDCP_CONFIG0_ROM_ENCRYPT_OFF, 0x3)); -+ regmap_write(priv->regmap, TX_HDCP_MEM_CONFIG, 0x0); -+ regmap_write(priv->regmap, TX_HDCP_ENCRYPT_BYTE, 0x0); -+ -+ regmap_write(priv->regmap, TX_HDCP_MODE, TX_HDCP_MODE_CLEAR_AVMUTE); -+ -+ regmap_write(priv->regmap, TX_HDCP_MODE, TX_HDCP_MODE_ESS_CONFIG); -+} -+ -+static u8 meson_txc_hdmi_bus_fmt_to_color_depth(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ /* 8 bit */ -+ return 0x0; -+ -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ /* 10 bit */ -+ return 0x1; -+ -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ /* 12 bit */ -+ return 0x2; -+ -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ /* 16 bit */ -+ return 0x3; -+ -+ default: -+ /* unknown, default to 8 bit */ -+ return 0x0; -+ } -+} -+ -+static enum hdmi_colorspace -+meson_txc_hdmi_bus_fmt_hdmi_colorspace(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ return HDMI_COLORSPACE_YUV444; -+ -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ return HDMI_COLORSPACE_YUV422; -+ -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ default: -+ return HDMI_COLORSPACE_RGB; -+ } -+} -+ -+static u8 meson_txc_hdmi_bus_fmt_to_color_format(unsigned int bus_format) -+{ -+ switch (meson_txc_hdmi_bus_fmt_hdmi_colorspace(bus_format)) { -+ case HDMI_COLORSPACE_YUV422: -+ /* Documented as YCbCr422 */ -+ return 0x3; -+ -+ case HDMI_COLORSPACE_YUV444: -+ /* Documented as YCbCr444 */ -+ return 0x1; -+ -+ case HDMI_COLORSPACE_RGB: -+ default: -+ /* Documented as RGB444 */ -+ return 0x0; -+ } -+} -+ -+static void meson_txc_hdmi_config_color_space(struct meson_txc_hdmi *priv, -+ enum hdmi_quantization_range quant_range, -+ enum hdmi_colorimetry colorimetry) -+{ -+ unsigned int regval; -+ -+ regmap_write(priv->regmap, TX_VIDEO_DTV_MODE, -+ FIELD_PREP(TX_VIDEO_DTV_MODE_COLOR_DEPTH, -+ meson_txc_hdmi_bus_fmt_to_color_depth(priv->output_bus_format))); -+ -+ regmap_write(priv->regmap, TX_VIDEO_DTV_OPTION_L, -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_FORMAT, -+ meson_txc_hdmi_bus_fmt_to_color_format(priv->output_bus_format)) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_FORMAT, -+ meson_txc_hdmi_bus_fmt_to_color_format(priv->input_bus_format)) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_DEPTH, -+ meson_txc_hdmi_bus_fmt_to_color_depth(priv->output_bus_format)) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_DEPTH, -+ meson_txc_hdmi_bus_fmt_to_color_depth(priv->input_bus_format))); -+ -+ if (quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) -+ regval = FIELD_PREP(TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235); -+ else -+ regval = FIELD_PREP(TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255); -+ -+ regmap_write(priv->regmap, TX_VIDEO_DTV_OPTION_H, regval); -+ -+ if (colorimetry == HDMI_COLORIMETRY_ITU_601) { -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B0, 0x2f); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B1, 0x1d); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R0, 0x8b); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R1, 0x4c); -+ -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB0, 0x18); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB1, 0x58); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR0, 0xd0); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR1, 0xb6); -+ } else { -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B0, 0x7b); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B1, 0x12); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R0, 0x6c); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R1, 0x36); -+ -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB0, 0xf2); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB1, 0x2f); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR0, 0xd4); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR1, 0x77); -+ } -+} -+ -+/* -+ * FIXME - questions for CDNS team: -+ * - what is the name of the 0x0018 register? -+ * - what do BIT(1), BIT(2), BIT(4) and BIT(5) mean? -+ * - if it's not clear from the names of these bits: when to set each of them? -+ * (below code depends on the HDMI_COLORIMETRY and one special case also on -+ * the color depth and a special HDMI VIC) -+ */ -+static void meson_txc_hdmi_config_serializer_clock(struct meson_txc_hdmi *priv, -+ enum hdmi_colorimetry colorimetry) -+{ -+ /* Serializer Internal clock setting */ -+ if (colorimetry == HDMI_COLORIMETRY_ITU_601) -+ regmap_write(priv->regmap, 0x0018, 0x24); -+ else -+ regmap_write(priv->regmap, 0x0018, 0x22); -+ -+#if 0 -+ // TODO: not ported yet -+ if ((param->VIC==HDMI_1080p60)&&(param->color_depth==COLOR_30BIT)&&(hdmi_rd_reg(0x018)==0x22)) { -+ regmap_write(priv->regmap, 0x0018, 0x12); -+ } -+#endif -+} -+ -+static void meson_txc_hdmi_reconfig_packet_setting(struct meson_txc_hdmi *priv, -+ u8 cea_mode) -+{ -+ u8 alloc_active2, alloc_eof1, alloc_sof1, alloc_sof2; -+ -+ regmap_write(priv->regmap, TX_PACKET_CONTROL_1, -+ FIELD_PREP(TX_PACKET_CONTROL_1_PACKET_START_LATENCY, 58)); -+ regmap_write(priv->regmap, TX_PACKET_CONTROL_2, -+ TX_PACKET_CONTROL_2_HORIZONTAL_GC_PACKET_TRANSPORT_EN); -+ -+ switch (cea_mode) { -+ case 31: -+ /* 1920x1080p50 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x10; -+ alloc_sof1 = 0xb6; -+ alloc_sof2 = 0x11; -+ break; -+ case 93: -+ /* 3840x2160p24 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x47; -+ alloc_sof1 = 0xf8; -+ alloc_sof2 = 0x52; -+ break; -+ case 94: -+ /* 3840x2160p25 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x44; -+ alloc_sof1 = 0xda; -+ alloc_sof2 = 0x52; -+ break; -+ case 95: -+ /* 3840x2160p30 */ -+ alloc_active2 = 0x0f; -+ alloc_eof1 = 0x3a; -+ alloc_sof1 = 0x60; -+ alloc_sof2 = 0x52; -+ break; -+ case 98: -+ /* 4096x2160p24 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x47; -+ alloc_sof1 = 0xf8; -+ alloc_sof2 = 0x52; -+ break; -+ default: -+ /* Disable the special packet settings only */ -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_1, 0x00); -+ return; -+ } -+ -+ /* -+ * The vendor driver says: manually configure these register to get -+ * stable video timings. -+ */ -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_1, 0x01); -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_2, alloc_active2); -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_EOF_1, alloc_eof1); -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_EOF_2, 0x12); -+ regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_0, 0x01); -+ regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_1, 0x00); -+ regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_2, 0x0a); -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_SOF_1, alloc_sof1); -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_SOF_2, alloc_sof2); -+ regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_1, -+ TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING, -+ TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING); -+} -+ -+static void meson_txc_hdmi_set_avi_infoframe(struct meson_txc_hdmi *priv, -+ struct drm_connector *conn, -+ const struct drm_display_mode *mode, -+ enum hdmi_quantization_range quant_range, -+ enum hdmi_colorimetry colorimetry) -+{ -+ u8 buf[HDMI_INFOFRAME_SIZE(AVI)], *video_code; -+ struct hdmi_avi_infoframe frame; -+ int ret; -+ -+ ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, conn, mode); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to setup AVI infoframe: %d\n", ret); -+ return; -+ } -+ -+ /* fixed infoframe configuration not linked to the mode */ -+ frame.colorspace = meson_txc_hdmi_bus_fmt_hdmi_colorspace(priv->output_bus_format); -+ frame.colorimetry = colorimetry; -+ -+ drm_hdmi_avi_infoframe_quant_range(&frame, conn, mode, quant_range); -+ -+ ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf)); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to pack AVI infoframe: %d\n", ret); -+ return; -+ } -+ -+ video_code = &buf[HDMI_INFOFRAME_HEADER_SIZE + 3]; -+ if (*video_code > 108) { -+ regmap_write(priv->regmap, TX_PKT_REG_EXCEPT0_BASE_ADDR, -+ *video_code); -+ *video_code = 0x00; -+ } else { -+ regmap_write(priv->regmap, TX_PKT_REG_EXCEPT0_BASE_ADDR, -+ 0x00); -+ } -+ -+ meson_txc_hdmi_write_infoframe(priv->regmap, -+ TX_PKT_REG_AVI_INFO_BASE_ADDR, buf, -+ sizeof(buf), true); -+} -+ -+static void meson_txc_hdmi_set_vendor_infoframe(struct meson_txc_hdmi *priv, -+ struct drm_connector *conn, -+ const struct drm_display_mode *mode) -+{ -+ u8 buf[HDMI_INFOFRAME_HEADER_SIZE + 6]; -+ struct hdmi_vendor_infoframe frame; -+ int ret; -+ -+ ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame, conn, mode); -+ if (ret) { -+ drm_dbg(priv->bridge.dev, -+ "Failed to setup vendor infoframe: %d\n", ret); -+ return; -+ } -+ -+ ret = hdmi_vendor_infoframe_pack(&frame, buf, sizeof(buf)); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to pack vendor infoframe: %d\n", ret); -+ return; -+ } -+ -+ meson_txc_hdmi_write_infoframe(priv->regmap, -+ TX_PKT_REG_VEND_INFO_BASE_ADDR, buf, -+ sizeof(buf), true); -+} -+ -+static void meson_txc_hdmi_set_spd_infoframe(struct meson_txc_hdmi *priv) -+{ -+ u8 buf[HDMI_INFOFRAME_SIZE(SPD)]; -+ struct hdmi_spd_infoframe frame; -+ int ret; -+ -+ ret = hdmi_spd_infoframe_init(&frame, "Amlogic", "Meson TXC HDMI"); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to setup SPD infoframe: %d\n", ret); -+ return; -+ } -+ -+ ret = hdmi_spd_infoframe_pack(&frame, buf, sizeof(buf)); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to pack SDP infoframe: %d\n", ret); -+ return; -+ } -+ -+ meson_txc_hdmi_write_infoframe(priv->regmap, -+ TX_PKT_REG_SPD_INFO_BASE_ADDR, buf, -+ sizeof(buf), true); -+} -+ -+static void meson_txc_hdmi_handle_plugged_change(struct meson_txc_hdmi *priv) -+{ -+ bool plugged; -+ -+ plugged = priv->last_connector_status == connector_status_connected; -+ -+ if (priv->codec_dev && priv->codec_plugged_cb) -+ priv->codec_plugged_cb(priv->codec_dev, plugged); -+} -+ -+static int meson_txc_hdmi_bridge_attach(struct drm_bridge *bridge, -+ enum drm_bridge_attach_flags flags) -+{ -+ struct meson_txc_hdmi *priv = bridge->driver_private; -+ -+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { -+ drm_err(bridge->dev, -+ "DRM_BRIDGE_ATTACH_NO_CONNECTOR flag is not set but needed\n"); -+ return -EINVAL; -+ } -+ -+ return drm_bridge_attach(bridge->encoder, priv->next_bridge, bridge, -+ flags); -+} -+ -+static int meson_txc_hdmi_bridge_atomic_check(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) -+{ -+ struct meson_txc_hdmi *priv = bridge->driver_private; -+ -+ priv->output_bus_format = bridge_state->output_bus_cfg.format; -+ priv->input_bus_format = bridge_state->input_bus_cfg.format; -+ -+ drm_dbg(bridge->dev, "input format 0x%04x, output format 0x%04x\n", -+ priv->input_bus_format, priv->output_bus_format); -+ -+ return 0; -+} -+ -+/* Can return a maximum of 11 possible output formats for a mode/connector */ -+#define MAX_OUTPUT_SEL_FORMATS 11 -+ -+static u32 * -+meson_txc_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ unsigned int *num_output_fmts) -+{ -+ struct drm_connector *conn = conn_state->connector; -+ struct drm_display_info *info = &conn->display_info; -+ u8 max_bpc = conn_state->max_requested_bpc; -+ unsigned int i = 0; -+ u32 *output_fmts; -+ -+ *num_output_fmts = 0; -+ -+ output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), -+ GFP_KERNEL); -+ if (!output_fmts) -+ return NULL; -+ -+ /* If we are the only bridge, avoid negotiating with ourselves */ -+ if (list_is_singular(&bridge->encoder->bridge_chain)) { -+ *num_output_fmts = 1; -+ output_fmts[0] = MEDIA_BUS_FMT_FIXED; -+ -+ return output_fmts; -+ } -+ -+ /* -+ * Order bus formats from 16bit to 8bit and from YUV422 to RGB -+ * if supported. In any case the default RGB888 format is added -+ */ -+ -+ if (max_bpc >= 16 && info->bpc == 16) { -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; -+ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; -+ } -+ -+ if (max_bpc >= 12 && info->bpc >= 12) { -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) -+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ } -+ -+ if (max_bpc >= 10 && info->bpc >= 10) { -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) -+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ } -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) -+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ -+ /* Default 8bit RGB fallback */ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ -+ *num_output_fmts = i; -+ -+ return output_fmts; -+} -+ -+/* Can return a maximum of 3 possible input formats for an output format */ -+#define MAX_INPUT_SEL_FORMATS 3 -+ -+static u32 * -+meson_txc_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ u32 output_fmt, -+ unsigned int *num_input_fmts) -+{ -+ u32 *input_fmts; -+ unsigned int i = 0; -+ -+ *num_input_fmts = 0; -+ -+ input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), -+ GFP_KERNEL); -+ if (!input_fmts) -+ return NULL; -+ -+ switch (output_fmt) { -+ /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ -+ case MEDIA_BUS_FMT_FIXED: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ break; -+ -+ /* 8bit */ -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ break; -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ break; -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ break; -+ -+ /* 10bit */ -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ break; -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ break; -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ break; -+ -+ /* 12bit */ -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ break; -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ break; -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ break; -+ -+ /* 16bit */ -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; -+ break; -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; -+ break; -+ } -+ -+ *num_input_fmts = i; -+ -+ if (*num_input_fmts == 0) { -+ kfree(input_fmts); -+ input_fmts = NULL; -+ } -+ -+ return input_fmts; -+} -+ -+static void meson_txc_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state) -+{ -+ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); -+ struct drm_atomic_state *state = bridge_state->base.state; -+ enum hdmi_quantization_range quant_range; -+ struct drm_connector_state *conn_state; -+ const struct drm_display_mode *mode; -+ enum hdmi_colorimetry colorimetry; -+ struct drm_crtc_state *crtc_state; -+ struct drm_connector *connector; -+ unsigned int i; -+ u8 cea_mode; -+ -+ connector = drm_atomic_get_new_connector_for_encoder(state, -+ bridge->encoder); -+ if (WARN_ON(!connector)) -+ return; -+ -+ conn_state = drm_atomic_get_new_connector_state(state, connector); -+ if (WARN_ON(!conn_state)) -+ return; -+ -+ crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); -+ if (WARN_ON(!crtc_state)) -+ return; -+ -+ mode = &crtc_state->adjusted_mode; -+ -+ memcpy(connector->eld, priv->eld, MAX_ELD_BYTES); -+ -+ if (priv->input_bus_format == MEDIA_BUS_FMT_FIXED) -+ priv->input_bus_format = MEDIA_BUS_FMT_RGB888_1X24; -+ -+ cea_mode = drm_match_cea_mode(mode); -+ -+ if (priv->sink_is_hdmi) { -+ quant_range = drm_default_rgb_quant_range(mode); -+ -+ switch (cea_mode) { -+ case 2 ... 3: -+ case 6 ... 7: -+ case 17 ... 18: -+ case 21 ... 22: -+ colorimetry = HDMI_COLORIMETRY_ITU_601; -+ break; -+ -+ default: -+ colorimetry = HDMI_COLORIMETRY_ITU_709; -+ break; -+ } -+ -+ meson_txc_hdmi_set_avi_infoframe(priv, connector, mode, -+ quant_range, colorimetry); -+ meson_txc_hdmi_set_vendor_infoframe(priv, connector, mode); -+ meson_txc_hdmi_set_spd_infoframe(priv); -+ } else { -+ quant_range = HDMI_QUANTIZATION_RANGE_FULL; -+ colorimetry = HDMI_COLORIMETRY_NONE; -+ } -+ -+ meson_txc_hdmi_sys5_reset_assert(priv); -+ -+ meson_txc_hdmi_config_hdcp_registers(priv); -+ -+ if (cea_mode == 39) -+ regmap_write(priv->regmap, TX_VIDEO_DTV_TIMING, 0x0); -+ else -+ regmap_write(priv->regmap, TX_VIDEO_DTV_TIMING, -+ TX_VIDEO_DTV_TIMING_DISABLE_VIC39_CORRECTION); -+ -+ regmap_write(priv->regmap, TX_CORE_DATA_CAPTURE_2, -+ TX_CORE_DATA_CAPTURE_2_INTERNAL_PACKET_ENABLE); -+ regmap_write(priv->regmap, TX_CORE_DATA_MONITOR_1, -+ TX_CORE_DATA_MONITOR_1_LANE0 | -+ FIELD_PREP(TX_CORE_DATA_MONITOR_1_SELECT_LANE0, 0x7)); -+ regmap_write(priv->regmap, TX_CORE_DATA_MONITOR_2, -+ FIELD_PREP(TX_CORE_DATA_MONITOR_2_MONITOR_SELECT, 0x2)); -+ -+ if (priv->sink_is_hdmi) -+ regmap_write(priv->regmap, TX_TMDS_MODE, -+ TX_TMDS_MODE_FORCED_HDMI | -+ TX_TMDS_MODE_HDMI_CONFIG); -+ else -+ regmap_write(priv->regmap, TX_TMDS_MODE, -+ TX_TMDS_MODE_FORCED_HDMI); -+ -+ regmap_write(priv->regmap, TX_SYS4_CONNECT_SEL_1, 0x0); -+ -+ /* -+ * Set tmds_clk pattern to be "0000011111" before being sent to AFE -+ * clock channel. -+ */ -+ regmap_write(priv->regmap, TX_SYS4_CK_INV_VIDEO, -+ TX_SYS4_CK_INV_VIDEO_TMDS_CLK_PATTERN); -+ -+ regmap_write(priv->regmap, TX_SYS5_FIFO_CONFIG, -+ TX_SYS5_FIFO_CONFIG_CLK_CHANNEL3_OUTPUT_ENABLE | -+ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_ENABLE | -+ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_ENABLE | -+ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_ENABLE); -+ -+ meson_txc_hdmi_config_color_space(priv, quant_range, colorimetry); -+ -+ meson_txc_hdmi_sys5_reset_deassert(priv); -+ -+ meson_txc_hdmi_config_serializer_clock(priv, colorimetry); -+ meson_txc_hdmi_reconfig_packet_setting(priv, cea_mode); -+ -+ /* all resets need to be applied twice */ -+ for (i = 0; i < 2; i++) { -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0); -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST | -+ TX_SYS5_TX_SOFT_RESET_2_TX_DDC_HDCP_RSTN | -+ TX_SYS5_TX_SOFT_RESET_2_TX_DDC_EDID_RSTN | -+ TX_SYS5_TX_SOFT_RESET_2_TX_DIG_RESET_N_CH3); -+ usleep_range(5000, 10000); -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x00); -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, 0x00); -+ usleep_range(5000, 10000); -+ } -+ -+ if (!priv->phy_is_on) { -+ int ret; -+ -+ ret = phy_power_on(priv->phy); -+ if (ret) -+ drm_err(bridge->dev, "Failed to turn on PHY\n"); -+ else -+ priv->phy_is_on = true; -+ } -+} -+ -+static void meson_txc_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state) -+{ -+ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); -+ -+ if (priv->phy_is_on) { -+ int ret; -+ -+ ret = phy_power_off(priv->phy); -+ if (ret) -+ drm_err(bridge->dev, "Failed to turn off PHY\n"); -+ else -+ priv->phy_is_on = false; -+ } -+ -+ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AUDIO_INFO_BASE_ADDR); -+ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AVI_INFO_BASE_ADDR); -+ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_EXCEPT0_BASE_ADDR); -+ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_VEND_INFO_BASE_ADDR); -+ -+ memset(priv->eld, 0, MAX_ELD_BYTES); -+} -+ -+static enum drm_mode_status -+meson_txc_hdmi_bridge_mode_valid(struct drm_bridge *bridge, -+ const struct drm_display_info *info, -+ const struct drm_display_mode *mode) -+{ -+ return MODE_OK; -+} -+ -+static enum drm_connector_status meson_txc_hdmi_bridge_detect(struct drm_bridge *bridge) -+{ -+ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); -+ enum drm_connector_status status; -+ unsigned int val; -+ -+ regmap_read(priv->regmap, TX_HDCP_ST_EDID_STATUS, &val); -+ if (val & TX_HDCP_ST_EDID_STATUS_HPD_STATUS) -+ status = connector_status_connected; -+ else -+ status = connector_status_disconnected; -+ -+ mutex_lock(&priv->codec_mutex); -+ if (priv->last_connector_status != status) { -+ priv->last_connector_status = status; -+ meson_txc_hdmi_handle_plugged_change(priv); -+ } -+ mutex_unlock(&priv->codec_mutex); -+ -+ return status; -+} -+ -+static int meson_txc_hdmi_get_edid_block(void *data, u8 *buf, unsigned int block, -+ size_t len) -+{ -+ unsigned int i, regval, start = block * EDID_LENGTH; -+ struct meson_txc_hdmi *priv = data; -+ int ret; -+ -+ /* Start the DDC transaction */ -+ regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, 0); -+ regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG); -+ -+ ret = regmap_read_poll_timeout(priv->regmap, -+ TX_HDCP_ST_EDID_STATUS, -+ regval, -+ (regval & TX_HDCP_ST_EDID_STATUS_EDID_DATA_READY), -+ 1000, 200000); -+ -+ regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, 0); -+ -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < len; i++) { -+ regmap_read(priv->regmap, TX_RX_EDID_OFFSET + start + i, -+ ®val); -+ buf[i] = regval; -+ } -+ -+ return 0; -+} -+ -+static struct edid *meson_txc_hdmi_bridge_get_edid(struct drm_bridge *bridge, -+ struct drm_connector *connector) -+{ -+ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); -+ struct edid *edid; -+ -+ edid = drm_do_get_edid(connector, meson_txc_hdmi_get_edid_block, priv); -+ if (!edid) { -+ drm_dbg(priv->bridge.dev, "Failed to get EDID\n"); -+ return NULL; -+ } -+ -+ priv->sink_is_hdmi = drm_detect_hdmi_monitor(edid); -+ -+ return edid; -+} -+ -+static const struct drm_bridge_funcs meson_txc_hdmi_bridge_funcs = { -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_reset = drm_atomic_helper_bridge_reset, -+ .attach = meson_txc_hdmi_bridge_attach, -+ .atomic_check = meson_txc_hdmi_bridge_atomic_check, -+ .atomic_get_output_bus_fmts = meson_txc_hdmi_bridge_atomic_get_output_bus_fmts, -+ .atomic_get_input_bus_fmts = meson_txc_hdmi_bridge_atomic_get_input_bus_fmts, -+ .atomic_enable = meson_txc_hdmi_bridge_atomic_enable, -+ .atomic_disable = meson_txc_hdmi_bridge_atomic_disable, -+ .mode_valid = meson_txc_hdmi_bridge_mode_valid, -+ .detect = meson_txc_hdmi_bridge_detect, -+ .get_edid = meson_txc_hdmi_bridge_get_edid, -+}; -+ -+static int meson_txc_hdmi_parse_dt(struct meson_txc_hdmi *priv) -+{ -+ struct device_node *endpoint, *remote; -+ -+ endpoint = of_graph_get_endpoint_by_regs(priv->dev->of_node, 1, -1); -+ if (!endpoint) { -+ dev_err(priv->dev, "Missing endpoint in port@1\n"); -+ return -ENODEV; -+ } -+ -+ remote = of_graph_get_remote_port_parent(endpoint); -+ of_node_put(endpoint); -+ if (!remote) { -+ dev_err(priv->dev, "Endpoint in port@1 unconnected\n"); -+ return -ENODEV; -+ } -+ -+ if (!of_device_is_available(remote)) { -+ dev_err(priv->dev, "port@1 remote device is disabled\n"); -+ of_node_put(remote); -+ return -ENODEV; -+ } -+ -+ priv->next_bridge = of_drm_find_bridge(remote); -+ of_node_put(remote); -+ if (!priv->next_bridge) -+ return -EPROBE_DEFER; -+ -+ return 0; -+} -+ -+static int meson_txc_hdmi_hw_init(struct meson_txc_hdmi *priv) -+{ -+ unsigned long ddc_i2c_bus_clk_hz = 500 * 1000; -+ unsigned long sys_clk_hz = 24 * 1000 * 1000; -+ int ret; -+ -+ ret = phy_init(priv->phy); -+ if (ret) { -+ dev_err(priv->dev, "Failed to initialize the PHY: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_set_rate(priv->sys_clk, sys_clk_hz); -+ if (ret) { -+ dev_err(priv->dev, "Failed to set HDMI system clock to 24MHz\n"); -+ goto err_phy_exit; -+ } -+ -+ ret = clk_prepare_enable(priv->sys_clk); -+ if (ret) { -+ dev_err(priv->dev, "Failed to enable the sys clk\n"); -+ goto err_phy_exit; -+ } -+ -+ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_POWER_ON, -+ HDMI_OTHER_CTRL1_POWER_ON); -+ -+ /* -+ * FIXME - questions for CDNS team: -+ * - what is the name of the 0x0010 register? -+ * - what do bit [7:0] stand for? -+ */ -+ regmap_write(priv->regmap, 0x0010, 0xff); -+ -+ regmap_write(priv->regmap, TX_HDCP_MODE, 0x40); -+ -+ /* -+ * FIXME - questions for CDNS team: -+ * - what is the name of the 0x0017 register? -+ * - is there a description for BIT(0), BIT(2), BIT(3) and BIT(4) or -+ * are 0x1d and 0x0 the only allowed values? -+ */ -+ /* Band-gap and main-bias. 0x1d = power-up, 0x00 = power-down */ -+ regmap_write(priv->regmap, 0x0017, 0x1d); -+ -+ meson_txc_hdmi_config_serializer_clock(priv, HDMI_COLORIMETRY_NONE); -+ -+ /* -+ * FIXME - questions for CDNS team: -+ * - what is the name of the 0x001a register? -+ * - is there a description for BIT(3), BIT(4), BIT(5), BIT(6) and -+ * BIT(7)? -+ */ -+ /* -+ * bit[2:0]=011: CK channel output TMDS CLOCK -+ * bit[2:0]=101, ck channel output PHYCLCK -+ */ -+ regmap_write(priv->regmap, 0x001a, 0xfb); -+ -+ /* Termination resistor calib value */ -+ regmap_write(priv->regmap, TX_CORE_CALIB_VALUE, 0x0f); -+ -+ /* HPD glitch filter */ -+ regmap_write(priv->regmap, TX_HDCP_HPD_FILTER_L, 0xa0); -+ regmap_write(priv->regmap, TX_HDCP_HPD_FILTER_H, 0xa0); -+ -+ /* Disable MEM power-down */ -+ regmap_write(priv->regmap, TX_MEM_PD_REG0, 0x0); -+ -+ regmap_write(priv->regmap, TX_HDCP_CONFIG3, -+ FIELD_PREP(TX_HDCP_CONFIG3_DDC_I2C_BUS_CLOCK_TIME_DIVIDER, -+ (sys_clk_hz / ddc_i2c_bus_clk_hz) - 1)); -+ -+ /* Enable software controlled DDC transaction */ -+ regmap_write(priv->regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_FORCED_MEM_COPY_DONE | -+ TX_HDCP_EDID_CONFIG_MEM_COPY_DONE_CONFIG); -+ regmap_write(priv->regmap, TX_CORE_EDID_CONFIG_MORE, -+ TX_CORE_EDID_CONFIG_MORE_SYS_TRIGGER_CONFIG_SEMI_MANU); -+ -+ /* mask (= disable) all interrupts */ -+ regmap_write(priv->regmap, HDMI_OTHER_INTR_MASKN, 0x0); -+ -+ /* clear any pending interrupt */ -+ regmap_write(priv->regmap, HDMI_OTHER_INTR_STAT_CLR, -+ HDMI_OTHER_INTR_STAT_CLR_EDID_RISING | -+ HDMI_OTHER_INTR_STAT_CLR_HPD_FALLING | -+ HDMI_OTHER_INTR_STAT_CLR_HPD_RISING); -+ -+ return 0; -+ -+err_phy_exit: -+ phy_exit(priv->phy); -+ return 0; -+} -+ -+static void meson_txc_hdmi_hw_exit(struct meson_txc_hdmi *priv) -+{ -+ int ret; -+ -+ /* mask (= disable) all interrupts */ -+ regmap_write(priv->regmap, HDMI_OTHER_INTR_MASKN, -+ HDMI_OTHER_INTR_MASKN_TX_EDID_INT_RISE | -+ HDMI_OTHER_INTR_MASKN_TX_HPD_INT_FALL | -+ HDMI_OTHER_INTR_MASKN_TX_HPD_INT_RISE); -+ -+ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_POWER_ON, 0); -+ -+ clk_disable_unprepare(priv->sys_clk); -+ -+ ret = phy_exit(priv->phy); -+ if (ret) -+ dev_err(priv->dev, "Failed to exit the PHY: %d\n", ret); -+} -+ -+static u32 meson_txc_hdmi_hdmi_codec_calc_audio_n(struct hdmi_codec_params *hparms) -+{ -+ u32 audio_n; -+ -+ if ((hparms->sample_rate % 44100) == 0) -+ audio_n = (128 * hparms->sample_rate) / 900; -+ else -+ audio_n = (128 * hparms->sample_rate) / 1000; -+ -+ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_EAC3 || -+ hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_DTS_HD) -+ audio_n *= 4; -+ -+ return audio_n; -+} -+ -+static u8 meson_txc_hdmi_hdmi_codec_coding_type(struct hdmi_codec_params *hparms) -+{ -+ switch (hparms->cea.coding_type) { -+ case HDMI_AUDIO_CODING_TYPE_MLP: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_HBR_AUDIO_PACKET; -+ case HDMI_AUDIO_CODING_TYPE_DSD: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_ONE_BIT_AUDIO; -+ case HDMI_AUDIO_CODING_TYPE_DST: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_DST_AUDIO_PACKET; -+ default: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_AUDIO_SAMPLE_PACKET; -+ } -+} -+ -+static int meson_txc_hdmi_hdmi_codec_hw_params(struct device *dev, void *data, -+ struct hdmi_codec_daifmt *fmt, -+ struct hdmi_codec_params *hparms) -+{ -+ u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)]; -+ struct meson_txc_hdmi *priv = data; -+ u16 audio_tx_format; -+ u32 audio_n; -+ int len, i; -+ -+ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_MLP) { -+ /* -+ * TODO: fixed CTS is not supported yet, it needs special -+ * TX_SYS1_ACR_N_* settings -+ */ -+ return -EINVAL; -+ } -+ -+ switch (hparms->sample_width) { -+ case 16: -+ audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK, -+ TX_AUDIO_FORMAT_BIT_WIDTH_16); -+ break; -+ -+ case 20: -+ audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK, -+ TX_AUDIO_FORMAT_BIT_WIDTH_20); -+ break; -+ -+ case 24: -+ audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK, -+ TX_AUDIO_FORMAT_BIT_WIDTH_24); -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ switch (fmt->fmt) { -+ case HDMI_I2S: -+ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON); -+ -+ audio_tx_format |= TX_AUDIO_FORMAT_SPDIF_OR_I2S | -+ TX_AUDIO_FORMAT_I2S_ONE_BIT_OR_I2S | -+ FIELD_PREP(TX_AUDIO_FORMAT_I2S_FORMAT, 0x2); -+ -+ if (hparms->channels > 2) -+ audio_tx_format |= TX_AUDIO_FORMAT_I2S_2_OR_8_CH; -+ -+ regmap_write(priv->regmap, TX_AUDIO_FORMAT, -+ audio_tx_format); -+ -+ regmap_write(priv->regmap, TX_AUDIO_I2S, TX_AUDIO_I2S_ENABLE); -+ regmap_write(priv->regmap, TX_AUDIO_SPDIF, 0x0); -+ break; -+ -+ case HDMI_SPDIF: -+ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, 0x0); -+ -+ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_STREAM) -+ audio_tx_format |= TX_AUDIO_FORMAT_SPDIF_CHANNEL_STATUS_FROM_DATA_OR_REG; -+ -+ regmap_write(priv->regmap, TX_AUDIO_FORMAT, -+ audio_tx_format); -+ -+ regmap_write(priv->regmap, TX_AUDIO_I2S, 0x0); -+ regmap_write(priv->regmap, TX_AUDIO_SPDIF, TX_AUDIO_SPDIF_ENABLE); -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ if (hparms->channels > 2) -+ regmap_write(priv->regmap, TX_AUDIO_HEADER, -+ TX_AUDIO_HEADER_AUDIO_SAMPLE_PACKET_HEADER_LAYOUT1); -+ else -+ regmap_write(priv->regmap, TX_AUDIO_HEADER, 0x0); -+ -+ regmap_write(priv->regmap, TX_AUDIO_SAMPLE, -+ FIELD_PREP(TX_AUDIO_SAMPLE_CHANNEL_VALID, -+ BIT(hparms->channels) - 1)); -+ -+ audio_n = meson_txc_hdmi_hdmi_codec_calc_audio_n(hparms); -+ -+ regmap_write(priv->regmap, TX_SYS1_ACR_N_0, -+ FIELD_PREP(TX_SYS1_ACR_N_0_N_BYTE0, -+ (audio_n >> 0) & 0xff)); -+ regmap_write(priv->regmap, TX_SYS1_ACR_N_1, -+ FIELD_PREP(TX_SYS1_ACR_N_1_N_BYTE1, -+ (audio_n >> 8) & 0xff)); -+ regmap_update_bits(priv->regmap, TX_SYS1_ACR_N_2, -+ TX_SYS1_ACR_N_2_N_UPPER_NIBBLE, -+ FIELD_PREP(TX_SYS1_ACR_N_2_N_UPPER_NIBBLE, -+ (audio_n >> 16) & 0xf)); -+ -+ regmap_write(priv->regmap, TX_SYS0_ACR_CTS_0, 0x0); -+ regmap_write(priv->regmap, TX_SYS0_ACR_CTS_1, 0x0); -+ regmap_write(priv->regmap, TX_SYS0_ACR_CTS_2, -+ TX_SYS0_ACR_CTS_2_FORCE_ARC_STABLE); -+ -+ regmap_write(priv->regmap, TX_AUDIO_CONTROL, -+ TX_AUDIO_CONTROL_AUTO_AUDIO_FIFO_CLEAR | -+ FIELD_PREP(TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_MASK, -+ meson_txc_hdmi_hdmi_codec_coding_type(hparms)) | -+ TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_FLAT); -+ -+ len = hdmi_audio_infoframe_pack(&hparms->cea, buf, sizeof(buf)); -+ if (len < 0) -+ return len; -+ -+ meson_txc_hdmi_write_infoframe(priv->regmap, -+ TX_PKT_REG_AUDIO_INFO_BASE_ADDR, -+ buf, len, true); -+ -+ for (i = 0; i < ARRAY_SIZE(hparms->iec.status); i++) { -+ unsigned char sub1, sub2; -+ -+ sub1 = sub2 = hparms->iec.status[i]; -+ -+ if (i == 2) { -+ sub1 |= FIELD_PREP(IEC958_AES2_CON_CHANNEL, 1); -+ sub2 |= FIELD_PREP(IEC958_AES2_CON_CHANNEL, 2); -+ } -+ -+ regmap_write(priv->regmap, TX_IEC60958_SUB1_OFFSET + i, sub1); -+ regmap_write(priv->regmap, TX_IEC60958_SUB2_OFFSET + i, sub2); -+ } -+ -+ return 0; -+} -+ -+static int meson_txc_hdmi_hdmi_codec_audio_startup(struct device *dev, -+ void *data) -+{ -+ struct meson_txc_hdmi *priv = data; -+ -+ regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_2, -+ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE, 0x0); -+ -+ /* reset audio master and sample */ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN); -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x0); -+ -+ regmap_write(priv->regmap, TX_AUDIO_CONTROL_MORE, -+ TX_AUDIO_CONTROL_MORE_ENABLE); -+ -+ regmap_write(priv->regmap, TX_AUDIO_FIFO, -+ FIELD_PREP(TX_AUDIO_FIFO_FIFO_DEPTH_MASK, -+ TX_AUDIO_FIFO_FIFO_DEPTH_512) | -+ FIELD_PREP(TX_AUDIO_FIFO_CRITICAL_THRESHOLD_MASK, -+ TX_AUDIO_FIFO_CRITICAL_THRESHOLD_DEPTH_DIV16) | -+ FIELD_PREP(TX_AUDIO_FIFO_NORMAL_THRESHOLD_MASK, -+ TX_AUDIO_FIFO_NORMAL_THRESHOLD_DEPTH_DIV8)); -+ -+ regmap_write(priv->regmap, TX_AUDIO_LIPSYNC, 0x0); -+ -+ regmap_write(priv->regmap, TX_SYS1_ACR_N_2, -+ FIELD_PREP(TX_SYS1_ACR_N_2_N_MEAS_TOLERANCE, 0x3)); -+ -+ return 0; -+} -+ -+static void meson_txc_hdmi_hdmi_codec_audio_shutdown(struct device *dev, -+ void *data) -+{ -+ struct meson_txc_hdmi *priv = data; -+ -+ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AUDIO_INFO_BASE_ADDR); -+ -+ regmap_write(priv->regmap, TX_AUDIO_CONTROL_MORE, 0x0); -+ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, 0x0); -+ -+ regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_2, -+ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE, -+ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE); -+} -+ -+static int meson_txc_hdmi_hdmi_codec_mute_stream(struct device *dev, -+ void *data, -+ bool enable, int direction) -+{ -+ struct meson_txc_hdmi *priv = data; -+ -+ regmap_write(priv->regmap, TX_AUDIO_PACK, -+ enable ? 0 : TX_AUDIO_PACK_AUDIO_SAMPLE_PACKETS_ENABLE); -+ -+ return 0; -+} -+ -+static int meson_txc_hdmi_hdmi_codec_get_eld(struct device *dev, void *data, -+ uint8_t *buf, size_t len) -+{ -+ struct meson_txc_hdmi *priv = data; -+ -+ memcpy(buf, priv->eld, min_t(size_t, MAX_ELD_BYTES, len)); -+ -+ return 0; -+} -+ -+static int meson_txc_hdmi_hdmi_codec_get_dai_id(struct snd_soc_component *component, -+ struct device_node *endpoint) -+{ -+ struct of_endpoint of_ep; -+ int ret; -+ -+ ret = of_graph_parse_endpoint(endpoint, &of_ep); -+ if (ret < 0) -+ return ret; -+ -+ /* -+ * HDMI sound should be located as reg = <2> -+ * Then, it is sound port 0 -+ */ -+ if (of_ep.port == 2) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static int meson_txc_hdmi_hdmi_codec_hook_plugged_cb(struct device *dev, -+ void *data, -+ hdmi_codec_plugged_cb fn, -+ struct device *codec_dev) -+{ -+ struct meson_txc_hdmi *priv = data; -+ -+ mutex_lock(&priv->codec_mutex); -+ priv->codec_plugged_cb = fn; -+ priv->codec_dev = codec_dev; -+ meson_txc_hdmi_handle_plugged_change(priv); -+ mutex_unlock(&priv->codec_mutex); -+ -+ return 0; -+} -+ -+static struct hdmi_codec_ops meson_txc_hdmi_hdmi_codec_ops = { -+ .hw_params = meson_txc_hdmi_hdmi_codec_hw_params, -+ .audio_startup = meson_txc_hdmi_hdmi_codec_audio_startup, -+ .audio_shutdown = meson_txc_hdmi_hdmi_codec_audio_shutdown, -+ .mute_stream = meson_txc_hdmi_hdmi_codec_mute_stream, -+ .get_eld = meson_txc_hdmi_hdmi_codec_get_eld, -+ .get_dai_id = meson_txc_hdmi_hdmi_codec_get_dai_id, -+ .hook_plugged_cb = meson_txc_hdmi_hdmi_codec_hook_plugged_cb, -+}; -+ -+static int meson_txc_hdmi_hdmi_codec_init(struct meson_txc_hdmi *priv) -+{ -+ struct hdmi_codec_pdata pdata = { -+ .ops = &meson_txc_hdmi_hdmi_codec_ops, -+ .i2s = 1, -+ .spdif = 1, -+ .max_i2s_channels = 8, -+ .data = priv, -+ }; -+ -+ priv->hdmi_codec_pdev = platform_device_register_data(priv->dev, -+ HDMI_CODEC_DRV_NAME, -+ PLATFORM_DEVID_AUTO, -+ &pdata, sizeof(pdata)); -+ return PTR_ERR_OR_ZERO(priv->hdmi_codec_pdev); -+} -+ -+static int meson_txc_hdmi_bind(struct device *dev, struct device *master, -+ void *data) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct meson_txc_hdmi *priv; -+ void __iomem *base; -+ u32 regval; -+ int ret; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->dev = dev; -+ priv->input_bus_format = MEDIA_BUS_FMT_FIXED; -+ priv->output_bus_format = MEDIA_BUS_FMT_FIXED; -+ -+ mutex_init(&priv->codec_mutex); -+ -+ dev_set_drvdata(dev, priv); -+ -+ base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ priv->regmap = devm_regmap_init(dev, NULL, base, -+ &meson_txc_hdmi_regmap_config); -+ if (IS_ERR(priv->regmap)) -+ return PTR_ERR(priv->regmap); -+ -+ priv->pclk = devm_clk_get(dev, "pclk"); -+ if (IS_ERR(priv->pclk)) { -+ ret = PTR_ERR(priv->pclk); -+ return dev_err_probe(dev, ret, "Failed to get the pclk\n"); -+ } -+ -+ priv->sys_clk = devm_clk_get(dev, "sys"); -+ if (IS_ERR(priv->sys_clk)) { -+ ret = PTR_ERR(priv->sys_clk); -+ return dev_err_probe(dev, ret, -+ "Failed to get the sys clock\n"); -+ } -+ -+ priv->phy = devm_phy_get(dev, "hdmi"); -+ if (IS_ERR(priv->phy)) { -+ ret = PTR_ERR(priv->phy); -+ return dev_err_probe(dev, ret, "Failed to get the HDMI PHY\n"); -+ } -+ -+ ret = meson_txc_hdmi_parse_dt(priv); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(priv->pclk); -+ if (ret) { -+ dev_err_probe(dev, ret, "Failed to enable the pclk\n"); -+ return ret; -+ } -+ -+ regval = readl(base + HDMI_CTRL_PORT); -+ regval |= HDMI_CTRL_PORT_APB3_ERR_EN; -+ writel(regval, base + HDMI_CTRL_PORT); -+ -+ ret = meson_txc_hdmi_hw_init(priv); -+ if (ret) -+ goto err_disable_clk; -+ -+ ret = meson_txc_hdmi_hdmi_codec_init(priv); -+ if (ret) -+ goto err_hw_exit; -+ -+ priv->bridge.driver_private = priv; -+ priv->bridge.funcs = &meson_txc_hdmi_bridge_funcs; -+ priv->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID; -+ priv->bridge.of_node = dev->of_node; -+ priv->bridge.interlace_allowed = true; -+ -+ drm_bridge_add(&priv->bridge); -+ -+ return 0; -+ -+err_hw_exit: -+ meson_txc_hdmi_hw_exit(priv); -+err_disable_clk: -+ clk_disable_unprepare(priv->pclk); -+ return ret; -+} -+ -+static void meson_txc_hdmi_unbind(struct device *dev, struct device *master, -+ void *data) -+{ -+ struct meson_txc_hdmi *priv = dev_get_drvdata(dev); -+ -+ platform_device_unregister(priv->hdmi_codec_pdev); -+ -+ drm_bridge_remove(&priv->bridge); -+ -+ meson_txc_hdmi_hw_exit(priv); -+ -+ clk_disable_unprepare(priv->pclk); -+} -+ -+static const struct component_ops meson_txc_hdmi_component_ops = { -+ .bind = meson_txc_hdmi_bind, -+ .unbind = meson_txc_hdmi_unbind, -+}; -+ -+static int meson_txc_hdmi_probe(struct platform_device *pdev) -+{ -+ return component_add(&pdev->dev, &meson_txc_hdmi_component_ops); -+} -+ -+static int meson_txc_hdmi_remove(struct platform_device *pdev) -+{ -+ component_del(&pdev->dev, &meson_txc_hdmi_component_ops); -+ -+ return 0; -+} -+ -+static const struct of_device_id meson_txc_hdmi_of_table[] = { -+ { .compatible = "amlogic,meson8-hdmi-tx" }, -+ { .compatible = "amlogic,meson8b-hdmi-tx" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, meson_txc_hdmi_of_table); -+ -+static struct platform_driver meson_txc_hdmi_platform_driver = { -+ .probe = meson_txc_hdmi_probe, -+ .remove = meson_txc_hdmi_remove, -+ .driver = { -+ .name = "meson-transwitch-hdmi", -+ .of_match_table = meson_txc_hdmi_of_table, -+ }, -+}; -+module_platform_driver(meson_txc_hdmi_platform_driver); -+ -+MODULE_AUTHOR("Martin Blumenstingl "); -+MODULE_DESCRIPTION("Amlogic Meson8 and Meson8b TranSwitch HDMI 1.4 TX driver"); -+MODULE_LICENSE("GPL v2"); -diff --git a/drivers/gpu/drm/meson/meson_transwitch_hdmi.h b/drivers/gpu/drm/meson/meson_transwitch_hdmi.h -new file mode 100644 -index 000000000000..14929475c0c8 ---- /dev/null -+++ b/drivers/gpu/drm/meson/meson_transwitch_hdmi.h -@@ -0,0 +1,536 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2021 Martin Blumenstingl -+ * -+ * All registers and magic values are taken from Amlogic's GPL kernel sources: -+ * Copyright (C) 2010 Amlogic, Inc. -+ */ -+ -+#include -+#include -+ -+#ifndef __MESON_TRANSWITCH_HDMI_H__ -+#define __MESON_TRANSWITCH_HDMI_H__ -+ -+/* HDMI TX register */ -+ -+// System config 0 -+#define TX_SYS0_AFE_SIGNAL 0x0000 -+#define TX_SYS0_AFE_LOOP 0x0001 -+#define TX_SYS0_ACR_CTS_0 0x0002 -+ #define TX_SYS0_ACR_CTS_0_AUDIO_CTS_BYTE0 GENMASK(7, 0) -+#define TX_SYS0_ACR_CTS_1 0x0003 -+ #define TX_SYS0_ACR_CTS_1_AUDIO_CTS_BYTE1 GENMASK(7, 0) -+#define TX_SYS0_ACR_CTS_2 0x0004 -+ #define TX_SYS0_ACR_CTS_2_FORCE_ARC_STABLE BIT(5) -+#define TX_SYS0_BIST_CONTROL 0x0005 -+ #define TX_SYS0_BIST_CONTROL_AFE_BIST_ENABLE BIT(7) -+ #define TX_SYS0_BIST_CONTROL_TMDS_SHIFT_PATTERN_SELECT BIT(6) -+ #define TX_SYS0_BIST_CONTROL_TMDS_PRBS_PATTERN_SELECT GENMASK(5, 4) -+ #define TX_SYS0_BIST_CONTROL_TMDS_REPEAT_BIST_PATTERN GENMASK(2, 0) -+ -+#define TX_SYS0_BIST_DATA_0 0x0006 -+#define TX_SYS0_BIST_DATA_1 0x0007 -+#define TX_SYS0_BIST_DATA_2 0x0008 -+#define TX_SYS0_BIST_DATA_3 0x0009 -+#define TX_SYS0_BIST_DATA_4 0x000A -+#define TX_SYS0_BIST_DATA_5 0x000B -+#define TX_SYS0_BIST_DATA_6 0x000C -+#define TX_SYS0_BIST_DATA_7 0x000D -+#define TX_SYS0_BIST_DATA_8 0x000E -+#define TX_SYS0_BIST_DATA_9 0x000F -+ -+// system config 1 -+#define TX_HDMI_PHY_CONFIG0 0x0010 -+ #define TX_HDMI_PHY_CONFIG0_HDMI_COMMON_B7_B0 GENMASK(7, 0) -+#define TX_HDMI_PHY_CONFIG1 0x0010 -+ #define TX_HDMI_PHY_CONFIG1_HDMI_COMMON_B11_B8 GENMASK(3, 0) -+ #define TX_HDMI_PHY_CONFIG1_HDMI_CTL_REG_B3_B0 GENMASK(7, 4) -+#define TX_HDMI_PHY_CONFIG2 0x0012 -+ #define TX_HDMI_PHY_CONFIG_HDMI_CTL_REG_B11_B4 GENMASK(7, 0) -+#define TX_HDMI_PHY_CONFIG3 0x0013 -+ #define TX_HDMI_PHY_CONFIG3_HDMI_L2H_CTL GENMASK(3, 0) -+ #define TX_HDMI_PHY_CONFIG3_HDMI_MDR_PU GENMASK(7, 4) -+#define TX_HDMI_PHY_CONFIG4 0x0014 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_LF_PD BIT(0) -+ #define TX_HDMI_PHY_CONFIG4_HDMI_PHY_CLK_EN BIT(1) -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE GENMASK(3, 2) -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_NORMAL 0x0 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_CLK_CH3_EQUAL_CH0 0x1 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_ALTERNATE_HIGH_LOW 0x2 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_ALTERNATE_LOW_HIGH 0x3 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_PREM_CTL GENMASK(7, 4) -+#define TX_HDMI_PHY_CONFIG5 0x0015 -+ #define TX_HDMI_PHY_CONFIG5_HDMI_VCM_CTL GENMASK(7, 5) -+ #define TX_HDMI_PHY_CONFIG5_HDMI_PREFCTL GENMASK(2, 0) -+#define TX_HDMI_PHY_CONFIG6 0x0016 -+ #define TX_HDMI_PHY_CONFIG6_HDMI_RTERM_CTL GENMASK(3, 0) -+ #define TX_HDMI_PHY_CONFIG6_HDMI_SWING_CTL GENMASK(7, 4) -+#define TX_SYS1_AFE_TEST 0x0017 -+#define TX_SYS1_PLL 0x0018 -+#define TX_SYS1_TUNE 0x0019 -+#define TX_SYS1_AFE_CONNECT 0x001A -+ -+#define TX_SYS1_ACR_N_0 0x001C -+ #define TX_SYS1_ACR_N_0_N_BYTE0 GENMASK(7, 0) -+#define TX_SYS1_ACR_N_1 0x001D -+ #define TX_SYS1_ACR_N_1_N_BYTE1 GENMASK(7, 0) -+#define TX_SYS1_ACR_N_2 0x001E -+ #define TX_SYS1_ACR_N_2_N_MEAS_TOLERANCE GENMASK(7, 4) -+ #define TX_SYS1_ACR_N_2_N_UPPER_NIBBLE GENMASK(3, 0) -+#define TX_SYS1_PRBS_DATA 0x001F -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE GENMASK(1, 0) -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_11 0x0 -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_15 0x1 -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_7 0x2 -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_31 0x3 -+ -+// HDCP CONFIG -+#define TX_HDCP_ECC_CONFIG 0x0024 -+#define TX_HDCP_CRC_CONFIG 0x0025 -+#define TX_HDCP_EDID_CONFIG 0x0026 -+ #define TX_HDCP_EDID_CONFIG_FORCED_SYS_TRIGGER BIT(7) -+ #define TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG BIT(6) -+ #define TX_HDCP_EDID_CONFIG_MEM_ACC_SEQ_MODE BIT(5) -+ #define TX_HDCP_EDID_CONFIG_MEM_ACC_SEQ_START BIT(4) -+ #define TX_HDCP_EDID_CONFIG_FORCED_MEM_COPY_DONE BIT(3) -+ #define TX_HDCP_EDID_CONFIG_MEM_COPY_DONE_CONFIG BIT(2) -+ #define TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG_SEMI_MANU BIT(1) -+ -+#define TX_HDCP_MEM_CONFIG 0x0027 -+ #define TX_HDCP_MEM_CONFIG_READ_DECRYPT BIT(3) -+ -+#define TX_HDCP_HPD_FILTER_L 0x0028 -+#define TX_HDCP_HPD_FILTER_H 0x0029 -+#define TX_HDCP_ENCRYPT_BYTE 0x002A -+#define TX_HDCP_CONFIG0 0x002B -+ #define TX_HDCP_CONFIG0_ROM_ENCRYPT_OFF GENMASK(4, 3) -+ -+#define TX_HDCP_CONFIG1 0x002C -+#define TX_HDCP_CONFIG2 0x002D -+#define TX_HDCP_CONFIG3 0x002E -+ #define TX_HDCP_CONFIG3_DDC_I2C_BUS_CLOCK_TIME_DIVIDER GENMASK(7, 0) -+ -+#define TX_HDCP_MODE 0x002F -+ #define TX_HDCP_MODE_CP_DESIRED BIT(7) -+ #define TX_HDCP_MODE_ESS_CONFIG BIT(6) -+ #define TX_HDCP_MODE_SET_AVMUTE BIT(5) -+ #define TX_HDCP_MODE_CLEAR_AVMUTE BIT(4) -+ #define TX_HDCP_MODE_HDCP_1_1 BIT(3) -+ #define TX_HDCP_MODE_VSYNC_HSYNC_FORCED_POLARITY_SELECT BIT(2) -+ #define TX_HDCP_MODE_FORCED_VSYNC_POLARITY BIT(1) -+ #define TX_HDCP_MODE_FORCED_HSYNC_POLARITY BIT(0) -+ -+// Video config, part 1 -+#define TX_VIDEO_ACTIVE_PIXELS_0 0x0030 -+#define TX_VIDEO_ACTIVE_PIXELS_1 0x0031 -+#define TX_VIDEO_FRONT_PIXELS 0x0032 -+#define TX_VIDEO_HSYNC_PIXELS 0x0033 -+#define TX_VIDEO_BACK_PIXELS 0x0034 -+#define TX_VIDEO_ACTIVE_LINES_0 0x0035 -+#define TX_VIDEO_ACTIVE_LINES_1 0x0036 -+#define TX_VIDEO_EOF_LINES 0x0037 -+#define TX_VIDEO_VSYNC_LINES 0x0038 -+#define TX_VIDEO_SOF_LINES 0x0039 -+#define TX_VIDEO_DTV_TIMING 0x003A -+ #define TX_VIDEO_DTV_TIMING_FORCE_DTV_TIMING_AUTO BIT(7) -+ #define TX_VIDEO_DTV_TIMING_FORCE_VIDEO_SCAN BIT(6) -+ #define TX_VIDEO_DTV_TIMING_FORCE_VIDEO_FIELD BIT(5) -+ #define TX_VIDEO_DTV_TIMING_DISABLE_VIC39_CORRECTION BIT(4) -+ -+#define TX_VIDEO_DTV_MODE 0x003B -+ #define TX_VIDEO_DTV_MODE_FORCED_DEFAULT_PHASE BIT(7) -+ #define TX_VIDEO_DTV_MODE_COLOR_DEPTH GENMASK(1, 0) -+ -+#define TX_VIDEO_DTV_FORMAT0 0x003C -+#define TX_VIDEO_DTV_FORMAT1 0x003D -+#define TX_VIDEO_PIXEL_PACK 0x003F -+// video config, part 2 -+#define TX_VIDEO_CSC_COEFF_B0 0x0040 -+#define TX_VIDEO_CSC_COEFF_B1 0x0041 -+#define TX_VIDEO_CSC_COEFF_R0 0x0042 -+#define TX_VIDEO_CSC_COEFF_R1 0x0043 -+#define TX_VIDEO_CSC_COEFF_CB0 0x0044 -+#define TX_VIDEO_CSC_COEFF_CB1 0x0045 -+#define TX_VIDEO_CSC_COEFF_CR0 0x0046 -+#define TX_VIDEO_CSC_COEFF_CR1 0x0047 -+#define TX_VIDEO_DTV_OPTION_L 0x0048 -+ #define TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_FORMAT GENMASK(7, 6) -+ #define TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_FORMAT GENMASK(5, 4) -+ #define TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_DEPTH GENMASK(3, 2) -+ #define TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_DEPTH GENMASK(1, 0) -+ -+#define TX_VIDEO_DTV_OPTION_H 0x0049 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235 0x0 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_240 0x1 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_1_254 0x2 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255 0x3 -+ #define TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE GENMASK(3, 2) -+ #define TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE GENMASK(1, 0) -+ -+#define TX_VIDEO_DTV_FILTER 0x004A -+#define TX_VIDEO_DTV_DITHER 0x004B -+#define TX_VIDEO_DTV_DEDITHER 0x004C -+#define TX_VIDEO_PROC_CONFIG0 0x004E -+#define TX_VIDEO_PROC_CONFIG1 0x004F -+ -+// Audio config -+#define TX_AUDIO_FORMAT 0x0058 -+ #define TX_AUDIO_FORMAT_SPDIF_OR_I2S BIT(7) -+ #define TX_AUDIO_FORMAT_I2S_2_OR_8_CH BIT(6) -+ #define TX_AUDIO_FORMAT_I2S_FORMAT GENMASK(5, 4) -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_MASK GENMASK(3, 2) -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_16 0x1 -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_20 0x2 -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_24 0x3 -+ #define TX_AUDIO_FORMAT_WS_POLARITY BIT(1) -+ #define TX_AUDIO_FORMAT_I2S_ONE_BIT_OR_I2S BIT(0) -+ #define TX_AUDIO_FORMAT_SPDIF_CHANNEL_STATUS_FROM_DATA_OR_REG BIT(0) -+ -+#define TX_AUDIO_SPDIF 0x0059 -+ #define TX_AUDIO_SPDIF_ENABLE BIT(0) -+#define TX_AUDIO_I2S 0x005A -+ #define TX_AUDIO_I2S_ENABLE BIT(0) -+#define TX_AUDIO_FIFO 0x005B -+ #define TX_AUDIO_FIFO_FIFO_DEPTH_MASK GENMASK(7, 4) -+ #define TX_AUDIO_FIFO_FIFO_DEPTH_512 0x4 -+ #define TX_AUDIO_FIFO_CRITICAL_THRESHOLD_MASK GENMASK(3, 2) -+ #define TX_AUDIO_FIFO_CRITICAL_THRESHOLD_DEPTH_DIV16 0x2 -+ #define TX_AUDIO_FIFO_NORMAL_THRESHOLD_MASK GENMASK(1, 0) -+ #define TX_AUDIO_FIFO_NORMAL_THRESHOLD_DEPTH_DIV8 0x1 -+#define TX_AUDIO_LIPSYNC 0x005C -+ #define TX_AUDIO_LIPSYNC_NORMALIZED_LIPSYNC_PARAM GENMASK(7, 0) -+#define TX_AUDIO_CONTROL 0x005D -+ #define TX_AUDIO_CONTROL_FORCED_AUDIO_FIFO_CLEAR BIT(7) -+ #define TX_AUDIO_CONTROL_AUTO_AUDIO_FIFO_CLEAR BIT(6) -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_MASK GENMASK(5, 4) -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_AUDIO_SAMPLE_PACKET 0x0 -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_ONE_BIT_AUDIO 0x1 -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_HBR_AUDIO_PACKET 0x2 -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_DST_AUDIO_PACKET 0x3 -+ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_VALID BIT(2) -+ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_USER BIT(1) -+ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_FLAT BIT(0) -+#define TX_AUDIO_HEADER 0x005E -+ #define TX_AUDIO_HEADER_AUDIO_SAMPLE_PACKET_HEADER_LAYOUT1 BIT(7) -+ #define TX_AUDIO_HEADER_SET_NORMAL_DOUBLE_IN_DST_PACKET_HEADER BIT(6) -+#define TX_AUDIO_SAMPLE 0x005F -+ #define TX_AUDIO_SAMPLE_CHANNEL_VALID GENMASK(7, 0) -+#define TX_AUDIO_VALID 0x0060 -+#define TX_AUDIO_USER 0x0061 -+#define TX_AUDIO_PACK 0x0062 -+ #define TX_AUDIO_PACK_AUDIO_SAMPLE_PACKETS_ENABLE BIT(0) -+#define TX_AUDIO_CONTROL_MORE 0x0064 -+ #define TX_AUDIO_CONTROL_MORE_ENABLE BIT(0) -+ -+// tmds config -+#define TX_TMDS_MODE 0x0068 -+ #define TX_TMDS_MODE_FORCED_HDMI BIT(7) -+ #define TX_TMDS_MODE_HDMI_CONFIG BIT(6) -+ #define TX_TMDS_MODE_BIT_SWAP BIT(3) -+ #define TX_TMDS_MODE_CHANNEL_SWAP GENMASK(2, 0) -+ -+#define TX_TMDS_CONFIG0 0x006C -+#define TX_TMDS_CONFIG1 0x006D -+ -+// packet config -+#define TX_PACKET_ALLOC_ACTIVE_1 0x0078 -+#define TX_PACKET_ALLOC_ACTIVE_2 0x0079 -+#define TX_PACKET_ALLOC_EOF_1 0x007A -+#define TX_PACKET_ALLOC_EOF_2 0x007B -+#define TX_PACKET_ALLOC_SOF_1 0x007C -+#define TX_PACKET_ALLOC_SOF_2 0x007D -+#define TX_PACKET_CONTROL_1 0x007E -+ #define TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING BIT(7) -+ #define TX_PACKET_CONTROL_1_PACKET_ALLOC_MODE BIT(6) -+ #define TX_PACKET_CONTROL_1_PACKET_START_LATENCY GENMASK(5, 0) -+ -+#define TX_PACKET_CONTROL_2 0x007F -+ #define TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE BIT(3) -+ #define TX_PACKET_CONTROL_2_HORIZONTAL_GC_PACKET_TRANSPORT_EN BIT(1) -+ -+#define TX_CORE_EDID_CONFIG_MORE 0x0080 -+ #define TX_CORE_EDID_CONFIG_MORE_KEEP_EDID_ERROR BIT(1) -+ #define TX_CORE_EDID_CONFIG_MORE_SYS_TRIGGER_CONFIG_SEMI_MANU BIT(0) -+ -+#define TX_CORE_ALLOC_VSYNC_0 0x0081 -+#define TX_CORE_ALLOC_VSYNC_1 0x0082 -+#define TX_CORE_ALLOC_VSYNC_2 0x0083 -+#define TX_MEM_PD_REG0 0x0084 -+ -+// core config -+#define TX_CORE_DATA_CAPTURE_1 0x00F0 -+#define TX_CORE_DATA_CAPTURE_2 0x00F1 -+ #define TX_CORE_DATA_CAPTURE_2_AUDIO_SOURCE_SELECT GENMASK(7, 6) -+ #define TX_CORE_DATA_CAPTURE_2_EXTERNAL_PACKET_ENABLE BIT(5) -+ #define TX_CORE_DATA_CAPTURE_2_INTERNAL_PACKET_ENABLE BIT(4) -+ #define TX_CORE_DATA_CAPTURE_2_AFE_FIFO_SRC_LANE1 GENMASK(3, 2) -+ #define TX_CORE_DATA_CAPTURE_2_AFE_FIFO_SRC_LANE0 GENMASK(1, 0) -+ -+#define TX_CORE_DATA_MONITOR_1 0x00F2 -+ #define TX_CORE_DATA_MONITOR_1_LANE1 BIT(7) -+ #define TX_CORE_DATA_MONITOR_1_SELECT_LANE1 GENMASK(6, 4) -+ #define TX_CORE_DATA_MONITOR_1_LANE0 BIT(3) -+ #define TX_CORE_DATA_MONITOR_1_SELECT_LANE0 GENMASK(2, 0) -+ -+#define TX_CORE_DATA_MONITOR_2 0x00F3 -+ #define TX_CORE_DATA_MONITOR_2_MONITOR_SELECT GENMASK(2, 0) -+ -+#define TX_CORE_CALIB_MODE 0x00F4 -+#define TX_CORE_CALIB_SAMPLE_DELAY 0x00F5 -+#define TX_CORE_CALIB_VALUE_AUTO 0x00F6 -+#define TX_CORE_CALIB_VALUE 0x00F7 -+ -+// system config 4 -+#define TX_SYS4_TX_CKI_DDR 0x00A0 -+#define TX_SYS4_TX_CKO_DDR 0x00A1 -+#define TX_SYS4_RX_CKI_DDR 0x00A2 -+#define TX_SYS4_RX_CKO_DDR 0x00A3 -+#define TX_SYS4_CONNECT_SEL_0 0x00A4 -+#define TX_SYS4_CONNECT_SEL_1 0x00A5 -+ #define TX_SYS4_CONNECT_SEL_1_TX_CONNECT_SEL_UPPER_CHANNEL_DATA BIT(6) -+ -+#define TX_SYS4_CONNECT_SEL_2 0x00A6 -+#define TX_SYS4_CONNECT_SEL_3 0x00A7 -+#define TX_SYS4_CK_INV_VIDEO 0x00A8 -+ #define TX_SYS4_CK_INV_VIDEO_TMDS_CLK_PATTERN BIT(4) -+#define TX_SYS4_CK_INV_AUDIO 0x00A9 -+#define TX_SYS4_CK_INV_AFE 0x00AA -+#define TX_SYS4_CK_INV_CH01 0x00AB -+#define TX_SYS4_CK_INV_CH2 0x00AC -+#define TX_SYS4_CK_CEC 0x00AD -+#define TX_SYS4_CK_SOURCE_1 0x00AE -+#define TX_SYS4_CK_SOURCE_2 0x00AF -+ -+#define TX_IEC60958_SUB1_OFFSET 0x00B0 -+#define TX_IEC60958_SUB2_OFFSET 0x00C8 -+ -+// system config 5 -+#define TX_SYS5_TX_SOFT_RESET_1 0x00E0 -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN BIT(7) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN BIT(6) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN BIT(5) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN BIT(4) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN BIT(3) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 BIT(2) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 BIT(1) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0 BIT(0) -+ -+#define TX_SYS5_TX_SOFT_RESET_2 0x00E1 -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN BIT(7) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN BIT(6) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN BIT(5) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN BIT(4) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST BIT(3) -+ #define TX_SYS5_TX_SOFT_RESET_2_TX_DDC_HDCP_RSTN BIT(2) -+ #define TX_SYS5_TX_SOFT_RESET_2_TX_DDC_EDID_RSTN BIT(1) -+ #define TX_SYS5_TX_SOFT_RESET_2_TX_DIG_RESET_N_CH3 BIT(0) -+ -+#define TX_SYS5_RX_SOFT_RESET_1 0x00E2 -+#define TX_SYS5_RX_SOFT_RESET_2 0x00E3 -+#define TX_SYS5_RX_SOFT_RESET_3 0x00E4 -+#define TX_SYS5_SSTL_BIDIR_IN 0x00E5 -+#define TX_SYS5_SSTL_IN 0x00E6 -+#define TX_SYS5_SSTL_DIFF_IN 0x00E7 -+#define TX_SYS5_FIFO_CONFIG 0x00E8 -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_BYPASS BIT(6) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_BYPASS BIT(5) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_BYPASS BIT(4) -+ #define TX_SYS5_FIFO_CONFIG_CLK_CHANNEL3_OUTPUT_ENABLE BIT(3) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_ENABLE BIT(2) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_ENABLE BIT(1) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_ENABLE BIT(0) -+ -+#define TX_SYS5_FIFO_SAMP01_CFG 0x00E9 -+#define TX_SYS5_FIFO_SAMP23_CFG 0x00EA -+#define TX_SYS5_CONNECT_FIFO_CFG 0x00EB -+#define TX_SYS5_IO_CALIB_CONTROL 0x00EC -+#define TX_SYS5_SSTL_BIDIR_OUT 0x00ED -+#define TX_SYS5_SSTL_OUT 0x00EE -+#define TX_SYS5_SSTL_DIFF_OUT 0x00EF -+ -+// HDCP shadow register -+#define TX_HDCP_SHW_BKSV_0 0x0100 -+#define TX_HDCP_SHW_BKSV_1 0x0101 -+#define TX_HDCP_SHW_BKSV_2 0x0102 -+#define TX_HDCP_SHW_BKSV_3 0x0103 -+#define TX_HDCP_SHW_BKSV_4 0x0104 -+#define TX_HDCP_SHW_RI1_0 0x0108 -+#define TX_HDCP_SHW_RI1_1 0x0109 -+#define TX_HDCP_SHW_PJ1 0x010A -+#define TX_HDCP_SHW_AKSV_0 0x0110 -+#define TX_HDCP_SHW_AKSV_1 0x0111 -+#define TX_HDCP_SHW_AKSV_2 0x0112 -+#define TX_HDCP_SHW_AKSV_3 0x0113 -+#define TX_HDCP_SHW_AKSV_4 0x0114 -+#define TX_HDCP_SHW_AINFO 0x0115 -+#define TX_HDCP_SHW_AN_0 0x0118 -+#define TX_HDCP_SHW_AN_1 0x0119 -+#define TX_HDCP_SHW_AN_2 0x011A -+#define TX_HDCP_SHW_AN_3 0x011B -+#define TX_HDCP_SHW_AN_4 0x011C -+#define TX_HDCP_SHW_AN_5 0x011D -+#define TX_HDCP_SHW_AN_6 0x011E -+#define TX_HDCP_SHW_AN_7 0x011F -+#define TX_HDCP_SHW_V1_H0_0 0x0120 -+#define TX_HDCP_SHW_V1_H0_1 0x0121 -+#define TX_HDCP_SHW_V1_H0_2 0x0122 -+#define TX_HDCP_SHW_V1_H0_3 0x0123 -+#define TX_HDCP_SHW_V1_H1_0 0x0124 -+#define TX_HDCP_SHW_V1_H1_1 0x0125 -+#define TX_HDCP_SHW_V1_H1_2 0x0126 -+#define TX_HDCP_SHW_V1_H1_3 0x0127 -+#define TX_HDCP_SHW_V1_H2_0 0x0128 -+#define TX_HDCP_SHW_V1_H2_1 0x0129 -+#define TX_HDCP_SHW_V1_H2_2 0x012A -+#define TX_HDCP_SHW_V1_H2_3 0x012B -+#define TX_HDCP_SHW_V1_H3_0 0x012C -+#define TX_HDCP_SHW_V1_H3_1 0x012D -+#define TX_HDCP_SHW_V1_H3_2 0x012E -+#define TX_HDCP_SHW_V1_H3_3 0x012F -+#define TX_HDCP_SHW_V1_H4_0 0x0130 -+#define TX_HDCP_SHW_V1_H4_1 0x0131 -+#define TX_HDCP_SHW_V1_H4_2 0x0132 -+#define TX_HDCP_SHW_V1_H4_3 0x0133 -+#define TX_HDCP_SHW_BCAPS 0x0140 -+#define TX_HDCP_SHW_BSTATUS_0 0x0141 -+#define TX_HDCP_SHW_BSTATUS_1 0x0142 -+#define TX_HDCP_SHW_KSV_FIFO 0x0143 -+ -+// system status 0 -+#define TX_SYSST0_CONNECT_FIFO 0x0180 -+#define TX_SYSST0_PLL_MONITOR 0x0181 -+#define TX_SYSST0_AFE_FIFO 0x0182 -+#define TX_SYSST0_ROM_STATUS 0x018F -+ -+// hdcp status -+#define TX_HDCP_ST_AUTHENTICATION 0x0190 -+#define TX_HDCP_ST_FRAME_COUNT 0x0191 -+#define TX_HDCP_ST_STATUS_0 0x0192 -+#define TX_HDCP_ST_STATUS_1 0x0193 -+#define TX_HDCP_ST_STATUS_2 0x0194 -+#define TX_HDCP_ST_STATUS_3 0x0195 -+#define TX_HDCP_ST_EDID_STATUS 0x0196 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS GENMASK(7, 6) -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_NO_SINK_ATTACHED 0x0 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_READING_EDID 0x1 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_DVI_MODE 0x2 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_HDMI_MODE 0x3 -+ #define TX_HDCP_ST_EDID_STATUS_EDID_DATA_READY BIT(4) -+ #define TX_HDCP_ST_EDID_STATUS_HPD_STATUS BIT(1) -+ -+#define TX_HDCP_ST_MEM_STATUS 0x0197 -+#define TX_HDCP_ST_ST_MODE 0x019F -+ -+// video status -+#define TX_VIDEO_ST_ACTIVE_PIXELS_1 0x01A0 -+#define TX_VIDEO_ST_ACTIVE_PIXELS_2 0x01A1 -+#define TX_VIDEO_ST_FRONT_PIXELS 0x01A2 -+#define TX_VIDEO_ST_HSYNC_PIXELS 0x01A3 -+#define TX_VIDEO_ST_BACK_PIXELS 0x01A4 -+#define TX_VIDEO_ST_ACTIVE_LINES_1 0x01A5 -+#define TX_VIDEO_ST_ACTIVE_LINES_2 0x01A6 -+#define TX_VIDEO_ST_EOF_LINES 0x01A7 -+#define TX_VIDEO_ST_VSYNC_LINES 0x01A8 -+#define TX_VIDEO_ST_SOF_LINES 0x01A9 -+#define TX_VIDEO_ST_DTV_TIMING 0x01AA -+#define TX_VIDEO_ST_DTV_MODE 0x01AB -+// audio status -+#define TX_VIDEO_ST_AUDIO_STATUS 0x01AC -+#define TX_AFE_STATUS_0 0x01AE -+#define TX_AFE_STATUS_1 0x01AF -+ -+#define TX_IEC60958_ST_SUB1_OFFSET 0x01B0 -+#define TX_IEC60958_ST_SUB2_OFFSET 0x01C8 -+ -+// system status 1 -+#define TX_SYSST1_CALIB_BIT_RESULT_0 0x01E0 -+#define TX_SYSST1_CALIB_BIT_RESULT_1 0x01E1 -+//HDMI_STATUS_OUT[7:0] -+#define TX_HDMI_PHY_READBACK_0 0x01E2 -+//HDMI_COMP_OUT[4] -+//HDMI_STATUS_OUT[11:8] -+#define TX_HDMI_PHY_READBACK_1 0x01E3 -+#define TX_SYSST1_CALIB_BIT_RESULT_4 0x01E4 -+#define TX_SYSST1_CALIB_BIT_RESULT_5 0x01E5 -+#define TX_SYSST1_CALIB_BIT_RESULT_6 0x01E6 -+#define TX_SYSST1_CALIB_BIT_RESULT_7 0x01E7 -+#define TX_SYSST1_CALIB_BUS_RESULT_0 0x01E8 -+#define TX_SYSST1_CALIB_BUS_RESULT_1 0x01E9 -+#define TX_SYSST1_CALIB_BUS_RESULT_2 0x01EA -+#define TX_SYSST1_CALIB_BUS_RESULT_3 0x01EB -+#define TX_SYSST1_CALIB_BUS_RESULT_4 0x01EC -+#define TX_SYSST1_CALIB_BUS_RESULT_5 0x01ED -+#define TX_SYSST1_CALIB_BUS_RESULT_6 0x01EE -+#define TX_SYSST1_CALIB_BUS_RESULT_7 0x01EF -+ -+// Packet status -+#define TX_PACKET_ST_REQUEST_STATUS_1 0x01F0 -+#define TX_PACKET_ST_REQUEST_STATUS_2 0x01F1 -+#define TX_PACKET_ST_REQUEST_MISSED_1 0x01F2 -+#define TX_PACKET_ST_REQUEST_MISSED_2 0x01F3 -+#define TX_PACKET_ST_ENCODE_STATUS_0 0x01F4 -+#define TX_PACKET_ST_ENCODE_STATUS_1 0x01F5 -+#define TX_PACKET_ST_ENCODE_STATUS_2 0x01F6 -+#define TX_PACKET_ST_TIMER_STATUS 0x01F7 -+ -+// tmds status -+#define TX_TMDS_ST_CLOCK_METER_1 0x01F8 -+#define TX_TMDS_ST_CLOCK_METER_2 0x01F9 -+#define TX_TMDS_ST_CLOCK_METER_3 0x01FA -+#define TX_TMDS_ST_TMDS_STATUS_1 0x01FC -+#define TX_TMDS_ST_TMDS_STATUS_2 0x01FD -+#define TX_TMDS_ST_TMDS_STATUS_3 0x01FE -+#define TX_TMDS_ST_TMDS_STATUS_4 0x01FF -+ -+// Packet register -+#define TX_PKT_REG_SPD_INFO_BASE_ADDR 0x0200 -+#define TX_PKT_REG_VEND_INFO_BASE_ADDR 0x0220 -+#define TX_PKT_REG_MPEG_INFO_BASE_ADDR 0x0240 -+#define TX_PKT_REG_AVI_INFO_BASE_ADDR 0x0260 -+#define TX_PKT_REG_AUDIO_INFO_BASE_ADDR 0x0280 -+#define TX_PKT_REG_ACP_INFO_BASE_ADDR 0x02A0 -+#define TX_PKT_REG_ISRC1_BASE_ADDR 0x02C0 -+#define TX_PKT_REG_ISRC2_BASE_ADDR 0x02E0 -+#define TX_PKT_REG_EXCEPT0_BASE_ADDR 0x0300 -+#define TX_PKT_REG_EXCEPT1_BASE_ADDR 0x0320 -+#define TX_PKT_REG_EXCEPT2_BASE_ADDR 0x0340 -+#define TX_PKT_REG_EXCEPT3_BASE_ADDR 0x0360 -+#define TX_PKT_REG_EXCEPT4_BASE_ADDR 0x0380 -+#define TX_PKT_REG_GAMUT_P0_BASE_ADDR 0x03A0 -+#define TX_PKT_REG_GAMUT_P1_1_BASE_ADDR 0x03C0 -+#define TX_PKT_REG_GAMUT_P1_2_BASE_ADDR 0x03E0 -+ -+#define TX_RX_EDID_OFFSET 0x0600 -+ -+/* HDMI OTHER registers */ -+ -+#define HDMI_OTHER_CTRL0 0x8000 -+#define HDMI_OTHER_CTRL1 0x8001 -+ #define HDMI_OTHER_CTRL1_POWER_ON BIT(15) -+ #define HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON BIT(13) -+ -+#define HDMI_OTHER_STATUS0 0x8002 -+#define HDMI_OTHER_CTRL2 0x8003 -+#define HDMI_OTHER_INTR_MASKN 0x8004 -+ #define HDMI_OTHER_INTR_MASKN_TX_EDID_INT_RISE BIT(2) -+ #define HDMI_OTHER_INTR_MASKN_TX_HPD_INT_FALL BIT(1) -+ #define HDMI_OTHER_INTR_MASKN_TX_HPD_INT_RISE BIT(0) -+ -+#define HDMI_OTHER_INTR_STAT 0x8005 -+ #define HDMI_OTHER_INTR_STAT_EDID_RISING BIT(2) -+ #define HDMI_OTHER_INTR_STAT_HPD_FALLING BIT(1) -+ #define HDMI_OTHER_INTR_STAT_HPD_RISING BIT(0) -+ -+#define HDMI_OTHER_INTR_STAT_CLR 0x8006 -+ #define HDMI_OTHER_INTR_STAT_CLR_EDID_RISING BIT(2) -+ #define HDMI_OTHER_INTR_STAT_CLR_HPD_FALLING BIT(1) -+ #define HDMI_OTHER_INTR_STAT_CLR_HPD_RISING BIT(0) -+ -+#define HDMI_OTHER_AVI_INTR_MASKN0 0x8008 -+#define HDMI_OTHER_AVI_INTR_MASKN1 0x8009 -+#define HDMI_OTHER_RX_AINFO_INTR_MASKN0 0x800a -+#define HDMI_OTHER_RX_AINFO_INTR_MASKN1 0x800b -+#define HDMI_OTHER_RX_PACKET_INTR_CLR 0x800c -+ -+#endif /* __MESON_TRANSWITCH_HDMI_H__ */ -diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c -index 2a82119eb58e..a2c1bf1aed77 100644 ---- a/drivers/gpu/drm/meson/meson_vclk.c -+++ b/drivers/gpu/drm/meson/meson_vclk.c -@@ -732,6 +732,11 @@ meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq) - return MODE_CLOCK_HIGH; - } - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ return MODE_OK; -+ - if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od)) - return MODE_OK; - -@@ -784,6 +789,11 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq, - return MODE_CLOCK_HIGH; - } - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ return MODE_OK; -+ - for (i = 0 ; params[i].pixel_freq ; ++i) { - DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n", - i, params[i].pixel_freq, -@@ -1024,6 +1034,128 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq, - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); - } - -+static int meson_vclk_set_rate_exclusive(struct meson_drm *priv, -+ enum vpu_bulk_clk_id clk_id, -+ unsigned int rate_khz) -+{ -+ struct clk *clk = priv->vid_clks[clk_id].clk; -+ int ret; -+ -+ ret = clk_set_rate_exclusive(clk, rate_khz * 1000UL); -+ if (ret) -+ return ret; -+ -+ priv->vid_clk_rate_exclusive[clk_id] = true; -+ -+ return 0; -+} -+ -+static void meson_vclk_disable_ccf(struct meson_drm *priv) -+{ -+ unsigned int i; -+ -+ /* allow all clocks to be changed in _enable again */ -+ for (i = 0; i < VPU_VID_CLK_NUM; i++) { -+ if (!priv->vid_clk_rate_exclusive[i]) -+ continue; -+ -+ clk_rate_exclusive_put(priv->vid_clks[i].clk); -+ priv->vid_clk_rate_exclusive[i] = false; -+ } -+ -+ if (priv->clk_dac_enabled) { -+ clk_disable(priv->clk_dac); -+ priv->clk_dac_enabled = false; -+ } -+ -+ if (priv->clk_venc_enabled) { -+ clk_disable(priv->clk_venc); -+ priv->clk_venc_enabled = false; -+ } -+} -+ -+static int meson_vclk_enable_ccf(struct meson_drm *priv, unsigned int target, -+ bool hdmi_use_enci, unsigned int phy_freq, -+ unsigned int dac_freq, unsigned int venc_freq) -+{ -+ enum vpu_bulk_clk_id venc_clk_id, dac_clk_id; -+ int ret; -+ -+ if (target == MESON_VCLK_TARGET_CVBS || hdmi_use_enci) -+ venc_clk_id = VPU_VID_CLK_CTS_ENCI; -+ else -+ venc_clk_id = VPU_VID_CLK_CTS_ENCP; -+ -+ if (target == MESON_VCLK_TARGET_CVBS) -+ dac_clk_id = VPU_VID_CLK_CTS_VDAC0; -+ else -+ dac_clk_id = VPU_VID_CLK_HDMI_TX_PIXEL; -+ -+ /* -+ * The TMDS clock also updates the PLL. Protect the PLL rate so all -+ * following clocks are derived from the PLL setting which matches the -+ * TMDS clock. -+ */ -+ ret = meson_vclk_set_rate_exclusive(priv, VPU_VID_CLK_TMDS, phy_freq); -+ if (ret) { -+ dev_err(priv->dev, "Failed to set TMDS clock to %ukHz: %d\n", -+ phy_freq, ret); -+ goto out_enable_clocks; -+ } -+ -+ /* -+ * The DAC clock may be derived from a parent of the VENC clock so we -+ * must protect the VENC clock from changing it's rate. This works -+ * because the DAC freq can be divided by the VENC clock. -+ */ -+ ret = meson_vclk_set_rate_exclusive(priv, venc_clk_id, venc_freq); -+ if (ret) { -+ dev_warn(priv->dev, -+ "Failed to set VENC clock to %ukHz while TMDS clock is %ukHz: %d\n", -+ venc_freq, phy_freq, ret); -+ goto out_enable_clocks; -+ } -+ -+ priv->clk_venc = priv->vid_clks[venc_clk_id].clk; -+ -+ /* -+ * after changing any of the VID_PLL_* clocks (which can happen when -+ * update the VENC clock rate) we need to assert and then de-assert the -+ * VID_DIVIDER_CNTL_* reset lines. -+ */ -+ reset_control_bulk_assert(VPU_RESET_VID_PLL_NUM, priv->vid_pll_resets); -+ reset_control_bulk_deassert(VPU_RESET_VID_PLL_NUM, priv->vid_pll_resets); -+ -+ ret = meson_vclk_set_rate_exclusive(priv, dac_clk_id, dac_freq); -+ if (ret) { -+ dev_warn(priv->dev, -+ "Failed to set pixel clock to %ukHz while TMDS clock is %ukHz: %d\n", -+ dac_freq, phy_freq, ret); -+ goto out_enable_clocks; -+ } -+ -+ priv->clk_dac = priv->vid_clks[dac_clk_id].clk; -+ -+out_enable_clocks: -+ ret = clk_enable(priv->clk_venc); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to re-enable the VENC clock at %ukHz: %d\n", -+ venc_freq, ret); -+ else -+ priv->clk_venc_enabled = true; -+ -+ ret = clk_enable(priv->clk_dac); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to re-enable the pixel clock at %ukHz: %d\n", -+ dac_freq, ret); -+ else -+ priv->clk_dac_enabled = true; -+ -+ return ret; -+} -+ - void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int phy_freq, unsigned int vclk_freq, - unsigned int venc_freq, unsigned int dac_freq, -@@ -1034,6 +1166,20 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int hdmi_tx_div; - unsigned int venc_div; - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ /* CVBS video clocks are generated off a 1296MHz base clock */ -+ if (target == MESON_VCLK_TARGET_CVBS) -+ phy_freq = 1296000; -+ -+ dev_err(priv->dev, "%s(target: %u, phy: %u, dac: %u, venc: %u, hdmi_use_enci: %u)\n", __func__, target, phy_freq, dac_freq, venc_freq, hdmi_use_enci); -+ meson_vclk_disable_ccf(priv); -+ meson_vclk_enable_ccf(priv, target, hdmi_use_enci, phy_freq, -+ dac_freq, venc_freq); -+ return; -+ } -+ - if (target == MESON_VCLK_TARGET_CVBS) { - meson_venci_cvbs_clock_config(priv); - return; -diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c -index 3c55ed003359..4acabe394f42 100644 ---- a/drivers/gpu/drm/meson/meson_venc.c -+++ b/drivers/gpu/drm/meson/meson_venc.c -@@ -1749,31 +1749,56 @@ void meson_venc_enable_vsync(struct meson_drm *priv) - { - writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, - priv->io_base + _REG(VENC_INTCTRL)); -- regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); -+ -+ if (priv->intr_clks[0].clk) { -+ if (!priv->intr_clks_enabled) { -+ int ret; -+ -+ ret = clk_bulk_enable(VPU_INTR_CLK_NUM, priv->intr_clks); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to enable the interrupt clocks\n"); -+ else -+ priv->intr_clks_enabled = true; -+ } -+ } else { -+ regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); -+ } - } - - void meson_venc_disable_vsync(struct meson_drm *priv) - { -- regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); -+ if (priv->intr_clks[0].clk) { -+ if (priv->intr_clks_enabled) { -+ clk_bulk_disable(VPU_INTR_CLK_NUM, priv->intr_clks); -+ priv->intr_clks_enabled = false; -+ } -+ } else { -+ regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); -+ } -+ - writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL)); - } - - void meson_venc_init(struct meson_drm *priv) - { -- /* Disable CVBS VDAC */ -- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8); -- } else { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); -+ if (priv->hhi) { -+ /* Disable CVBS VDAC */ -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { -+ regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); -+ regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8); -+ } else { -+ regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); -+ regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); -+ } - } - - /* Power Down Dacs */ - writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); - - /* Disable HDMI PHY */ -- regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); -+ if (priv->hhi) -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); - - /* Disable HDMI */ - writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI | -diff --git a/drivers/gpu/drm/meson/meson_venc_cvbs.c b/drivers/gpu/drm/meson/meson_venc_cvbs.c -deleted file mode 100644 -index f1747fde1fe0..000000000000 ---- a/drivers/gpu/drm/meson/meson_venc_cvbs.c -+++ /dev/null -@@ -1,293 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0-or-later --/* -- * Copyright (C) 2016 BayLibre, SAS -- * Author: Neil Armstrong -- * Copyright (C) 2015 Amlogic, Inc. All rights reserved. -- * Copyright (C) 2014 Endless Mobile -- * -- * Written by: -- * Jasper St. Pierre -- */ -- --#include --#include -- --#include --#include --#include --#include --#include -- --#include "meson_registers.h" --#include "meson_vclk.h" --#include "meson_venc_cvbs.h" -- --/* HHI VDAC Registers */ --#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ --#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */ --#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ --#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */ -- --struct meson_venc_cvbs { -- struct drm_encoder encoder; -- struct drm_connector connector; -- struct meson_drm *priv; --}; --#define encoder_to_meson_venc_cvbs(x) \ -- container_of(x, struct meson_venc_cvbs, encoder) -- --#define connector_to_meson_venc_cvbs(x) \ -- container_of(x, struct meson_venc_cvbs, connector) -- --/* Supported Modes */ -- --struct meson_cvbs_mode meson_cvbs_modes[MESON_CVBS_MODES_COUNT] = { -- { /* PAL */ -- .enci = &meson_cvbs_enci_pal, -- .mode = { -- DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, -- 720, 732, 795, 864, 0, 576, 580, 586, 625, 0, -- DRM_MODE_FLAG_INTERLACE), -- .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, -- }, -- }, -- { /* NTSC */ -- .enci = &meson_cvbs_enci_ntsc, -- .mode = { -- DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, -- 720, 739, 801, 858, 0, 480, 488, 494, 525, 0, -- DRM_MODE_FLAG_INTERLACE), -- .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, -- }, -- }, --}; -- --static const struct meson_cvbs_mode * --meson_cvbs_get_mode(const struct drm_display_mode *req_mode) --{ -- int i; -- -- for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) { -- struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i]; -- -- if (drm_mode_match(req_mode, &meson_mode->mode, -- DRM_MODE_MATCH_TIMINGS | -- DRM_MODE_MATCH_CLOCK | -- DRM_MODE_MATCH_FLAGS | -- DRM_MODE_MATCH_3D_FLAGS)) -- return meson_mode; -- } -- -- return NULL; --} -- --/* Connector */ -- --static void meson_cvbs_connector_destroy(struct drm_connector *connector) --{ -- drm_connector_cleanup(connector); --} -- --static enum drm_connector_status --meson_cvbs_connector_detect(struct drm_connector *connector, bool force) --{ -- /* FIXME: Add load-detect or jack-detect if possible */ -- return connector_status_connected; --} -- --static int meson_cvbs_connector_get_modes(struct drm_connector *connector) --{ -- struct drm_device *dev = connector->dev; -- struct drm_display_mode *mode; -- int i; -- -- for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) { -- struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i]; -- -- mode = drm_mode_duplicate(dev, &meson_mode->mode); -- if (!mode) { -- DRM_ERROR("Failed to create a new display mode\n"); -- return 0; -- } -- -- drm_mode_probed_add(connector, mode); -- } -- -- return i; --} -- --static int meson_cvbs_connector_mode_valid(struct drm_connector *connector, -- struct drm_display_mode *mode) --{ -- /* Validate the modes added in get_modes */ -- return MODE_OK; --} -- --static const struct drm_connector_funcs meson_cvbs_connector_funcs = { -- .detect = meson_cvbs_connector_detect, -- .fill_modes = drm_helper_probe_single_connector_modes, -- .destroy = meson_cvbs_connector_destroy, -- .reset = drm_atomic_helper_connector_reset, -- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, -- .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, --}; -- --static const --struct drm_connector_helper_funcs meson_cvbs_connector_helper_funcs = { -- .get_modes = meson_cvbs_connector_get_modes, -- .mode_valid = meson_cvbs_connector_mode_valid, --}; -- --/* Encoder */ -- --static void meson_venc_cvbs_encoder_destroy(struct drm_encoder *encoder) --{ -- drm_encoder_cleanup(encoder); --} -- --static const struct drm_encoder_funcs meson_venc_cvbs_encoder_funcs = { -- .destroy = meson_venc_cvbs_encoder_destroy, --}; -- --static int meson_venc_cvbs_encoder_atomic_check(struct drm_encoder *encoder, -- struct drm_crtc_state *crtc_state, -- struct drm_connector_state *conn_state) --{ -- if (meson_cvbs_get_mode(&crtc_state->mode)) -- return 0; -- -- return -EINVAL; --} -- --static void meson_venc_cvbs_encoder_disable(struct drm_encoder *encoder) --{ -- struct meson_venc_cvbs *meson_venc_cvbs = -- encoder_to_meson_venc_cvbs(encoder); -- struct meson_drm *priv = meson_venc_cvbs->priv; -- -- /* Disable CVBS VDAC */ -- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); -- } else { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); -- } --} -- --static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder) --{ -- struct meson_venc_cvbs *meson_venc_cvbs = -- encoder_to_meson_venc_cvbs(encoder); -- struct meson_drm *priv = meson_venc_cvbs->priv; -- -- /* VDAC0 source is not from ATV */ -- writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0, -- priv->io_base + _REG(VENC_VDAC_DACSEL0)); -- -- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); -- } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || -- meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); -- } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); -- } --} -- --static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder, -- struct drm_display_mode *mode, -- struct drm_display_mode *adjusted_mode) --{ -- const struct meson_cvbs_mode *meson_mode = meson_cvbs_get_mode(mode); -- struct meson_venc_cvbs *meson_venc_cvbs = -- encoder_to_meson_venc_cvbs(encoder); -- struct meson_drm *priv = meson_venc_cvbs->priv; -- -- if (meson_mode) { -- meson_venci_cvbs_mode_set(priv, meson_mode->enci); -- -- /* Setup 27MHz vclk2 for ENCI and VDAC */ -- meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS, -- MESON_VCLK_CVBS, MESON_VCLK_CVBS, -- MESON_VCLK_CVBS, MESON_VCLK_CVBS, -- true); -- } --} -- --static const struct drm_encoder_helper_funcs -- meson_venc_cvbs_encoder_helper_funcs = { -- .atomic_check = meson_venc_cvbs_encoder_atomic_check, -- .disable = meson_venc_cvbs_encoder_disable, -- .enable = meson_venc_cvbs_encoder_enable, -- .mode_set = meson_venc_cvbs_encoder_mode_set, --}; -- --static bool meson_venc_cvbs_connector_is_available(struct meson_drm *priv) --{ -- struct device_node *remote; -- -- remote = of_graph_get_remote_node(priv->dev->of_node, 0, 0); -- if (!remote) -- return false; -- -- of_node_put(remote); -- return true; --} -- --int meson_venc_cvbs_create(struct meson_drm *priv) --{ -- struct drm_device *drm = priv->drm; -- struct meson_venc_cvbs *meson_venc_cvbs; -- struct drm_connector *connector; -- struct drm_encoder *encoder; -- int ret; -- -- if (!meson_venc_cvbs_connector_is_available(priv)) { -- dev_info(drm->dev, "CVBS Output connector not available\n"); -- return 0; -- } -- -- meson_venc_cvbs = devm_kzalloc(priv->dev, sizeof(*meson_venc_cvbs), -- GFP_KERNEL); -- if (!meson_venc_cvbs) -- return -ENOMEM; -- -- meson_venc_cvbs->priv = priv; -- encoder = &meson_venc_cvbs->encoder; -- connector = &meson_venc_cvbs->connector; -- -- /* Connector */ -- -- drm_connector_helper_add(connector, -- &meson_cvbs_connector_helper_funcs); -- -- ret = drm_connector_init(drm, connector, &meson_cvbs_connector_funcs, -- DRM_MODE_CONNECTOR_Composite); -- if (ret) { -- dev_err(priv->dev, "Failed to init CVBS connector\n"); -- return ret; -- } -- -- connector->interlace_allowed = 1; -- -- /* Encoder */ -- -- drm_encoder_helper_add(encoder, &meson_venc_cvbs_encoder_helper_funcs); -- -- ret = drm_encoder_init(drm, encoder, &meson_venc_cvbs_encoder_funcs, -- DRM_MODE_ENCODER_TVDAC, "meson_venc_cvbs"); -- if (ret) { -- dev_err(priv->dev, "Failed to init CVBS encoder\n"); -- return ret; -- } -- -- encoder->possible_crtcs = BIT(0); -- -- drm_connector_attach_encoder(connector, encoder); -- -- return 0; --} -diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c -index cd399b0b7181..bdfa342c4ca1 100644 ---- a/drivers/gpu/drm/meson/meson_viu.c -+++ b/drivers/gpu/drm/meson/meson_viu.c -@@ -448,13 +448,17 @@ void meson_viu_init(struct meson_drm *priv) - writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); - writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); - -- /* Set OSD alpha replace value */ -- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -- 0xff << OSD_REPLACE_SHIFT, -- priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); -- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -- 0xff << OSD_REPLACE_SHIFT, -- priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ /* Set OSD alpha replace value */ -+ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -+ 0xff << OSD_REPLACE_SHIFT, -+ priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); -+ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -+ 0xff << OSD_REPLACE_SHIFT, -+ priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); -+ } - - /* Disable VD1 AFBC */ - /* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/ -diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig -index db5d0cd757e3..53ea95336fc8 100644 ---- a/drivers/phy/amlogic/Kconfig -+++ b/drivers/phy/amlogic/Kconfig -@@ -2,6 +2,16 @@ - # - # Phy drivers for Amlogic platforms - # -+config PHY_MESON8_HDMI_TX -+ tristate "Meson8, Meson8b and Meson8m2 HDMI TX PHY driver" -+ depends on (ARCH_MESON && ARM) || COMPILE_TEST -+ depends on OF -+ select MFD_SYSCON -+ help -+ Enable this to support the HDMI TX PHYs found in Meson8, -+ Meson8b and Meson8m2 SoCs. -+ If unsure, say N. -+ - config PHY_MESON8B_USB2 - tristate "Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY driver" - default ARCH_MESON -@@ -15,6 +25,16 @@ config PHY_MESON8B_USB2 - Meson8b and GXBB SoCs. - If unsure, say N. - -+config PHY_MESON_CVBS_DAC -+ tristate "Amlogic Meson CVBS DAC PHY driver" -+ depends on ARCH_MESON || COMPILE_TEST -+ depends on OF -+ select MFD_SYSCON -+ help -+ Enable this to support the CVBS DAC (PHY) found in Amlogic -+ Meson SoCs. -+ If unsure, say N. -+ - config PHY_MESON_GXL_USB2 - tristate "Meson GXL and GXM USB2 PHY drivers" - default ARCH_MESON -diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile -index 8fa07fbd0d92..f5e1145e983b 100644 ---- a/drivers/phy/amlogic/Makefile -+++ b/drivers/phy/amlogic/Makefile -@@ -1,5 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0-only -+obj-$(CONFIG_PHY_MESON8_HDMI_TX) += phy-meson8-hdmi-tx.o - obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o -+obj-$(CONFIG_PHY_MESON_CVBS_DAC) += phy-meson-cvbs-dac.o - obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o - obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o - obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o -diff --git a/drivers/phy/amlogic/phy-meson-cvbs-dac.c b/drivers/phy/amlogic/phy-meson-cvbs-dac.c -new file mode 100644 -index 000000000000..3287d53c768a ---- /dev/null -+++ b/drivers/phy/amlogic/phy-meson-cvbs-dac.c -@@ -0,0 +1,310 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Copyright (C) 2016 BayLibre, SAS -+ * Copyright (C) 2021 Martin Blumenstingl -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define HHI_VDAC_CNTL0_MESON8 0x2F4 /* 0xbd offset in data sheet */ -+#define HHI_VDAC_CNTL1_MESON8 0x2F8 /* 0xbe offset in data sheet */ -+ -+#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */ -+#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */ -+ -+enum phy_meson_cvbs_dac_reg { -+ MESON_CDAC_CTRL_RESV1, -+ MESON_CDAC_CTRL_RESV2, -+ MESON_CDAC_VREF_ADJ, -+ MESON_CDAC_RL_ADJ, -+ MESON_CDAC_CLK_PHASE_SEL, -+ MESON_CDAC_DRIVER_ADJ, -+ MESON_CDAC_EXT_VREF_EN, -+ MESON_CDAC_BIAS_C, -+ MESON_VDAC_CNTL0_RESERVED, -+ MESON_CDAC_GSW, -+ MESON_CDAC_PWD, -+ MESON_VDAC_CNTL1_RESERVED, -+ MESON_CVBS_DAC_NUM_REGS -+}; -+ -+struct phy_meson_cvbs_dac_data { -+ const struct reg_field *reg_fields; -+ u8 cdac_ctrl_resv2_enable_val; -+ u8 cdac_vref_adj_enable_val; -+ u8 cdac_rl_adj_enable_val; -+ bool disable_ignore_cdac_pwd; -+ bool has_cvbs_trimming_nvmem_cell; -+}; -+ -+struct phy_meson_cvbs_dac_priv { -+ struct regmap_field *regs[MESON_CVBS_DAC_NUM_REGS]; -+ const struct phy_meson_cvbs_dac_data *data; -+ u8 cdac_gsw_enable_val; -+}; -+ -+static const struct reg_field phy_meson8_cvbs_dac_reg_fields[] = { -+ [MESON_CDAC_CTRL_RESV1] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 0, 7), -+ [MESON_CDAC_CTRL_RESV2] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 8, 15), -+ [MESON_CDAC_VREF_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 16, 20), -+ [MESON_CDAC_RL_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 21, 23), -+ [MESON_CDAC_CLK_PHASE_SEL] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 24, 24), -+ [MESON_CDAC_DRIVER_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 25, 25), -+ [MESON_CDAC_EXT_VREF_EN] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 26, 26), -+ [MESON_CDAC_BIAS_C] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 27, 27), -+ [MESON_VDAC_CNTL0_RESERVED] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 28, 31), -+ [MESON_CDAC_GSW] = REG_FIELD(HHI_VDAC_CNTL1_MESON8, 0, 2), -+ [MESON_CDAC_PWD] = REG_FIELD(HHI_VDAC_CNTL1_MESON8, 3, 3), -+ [MESON_VDAC_CNTL1_RESERVED] = REG_FIELD(HHI_VDAC_CNTL1_MESON8, 4, 31), -+}; -+ -+static const struct reg_field phy_meson_g12a_cvbs_dac_reg_fields[] = { -+ [MESON_CDAC_CTRL_RESV1] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 0, 7), -+ [MESON_CDAC_CTRL_RESV2] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 8, 15), -+ [MESON_CDAC_VREF_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 16, 20), -+ [MESON_CDAC_RL_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 21, 23), -+ [MESON_CDAC_CLK_PHASE_SEL] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 24, 24), -+ [MESON_CDAC_DRIVER_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 25, 25), -+ [MESON_CDAC_EXT_VREF_EN] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 26, 26), -+ [MESON_CDAC_BIAS_C] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 27, 27), -+ [MESON_VDAC_CNTL0_RESERVED] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 28, 31), -+ [MESON_CDAC_GSW] = REG_FIELD(HHI_VDAC_CNTL1_G12A, 0, 2), -+ [MESON_CDAC_PWD] = REG_FIELD(HHI_VDAC_CNTL1_G12A, 3, 3), -+ [MESON_VDAC_CNTL1_RESERVED] = REG_FIELD(HHI_VDAC_CNTL1_G12A, 4, 31), -+}; -+ -+static const struct phy_meson_cvbs_dac_data phy_meson8_cvbs_dac_data = { -+ .reg_fields = phy_meson8_cvbs_dac_reg_fields, -+ .cdac_ctrl_resv2_enable_val = 0x0, -+ .cdac_vref_adj_enable_val = 0x0, -+ .cdac_rl_adj_enable_val = 0x0, -+ .disable_ignore_cdac_pwd = false, -+ .has_cvbs_trimming_nvmem_cell = true, -+}; -+ -+static const struct phy_meson_cvbs_dac_data phy_meson_gxbb_cvbs_dac_data = { -+ .reg_fields = phy_meson8_cvbs_dac_reg_fields, -+ .cdac_ctrl_resv2_enable_val = 0x0, -+ .cdac_vref_adj_enable_val = 0x0, -+ .cdac_rl_adj_enable_val = 0x0, -+ .disable_ignore_cdac_pwd = false, -+ .has_cvbs_trimming_nvmem_cell = false, -+}; -+ -+static const struct phy_meson_cvbs_dac_data phy_meson_gxl_cvbs_dac_data = { -+ .reg_fields = phy_meson8_cvbs_dac_reg_fields, -+ .cdac_ctrl_resv2_enable_val = 0x0, -+ .cdac_vref_adj_enable_val = 0xf, -+ .cdac_rl_adj_enable_val = 0x0, -+ .disable_ignore_cdac_pwd = false, -+ .has_cvbs_trimming_nvmem_cell = false, -+}; -+ -+static const struct phy_meson_cvbs_dac_data phy_meson_g12a_cvbs_dac_data = { -+ .reg_fields = phy_meson_g12a_cvbs_dac_reg_fields, -+ .cdac_ctrl_resv2_enable_val = 0x60, -+ .cdac_vref_adj_enable_val = 0x10, -+ .cdac_rl_adj_enable_val = 0x4, -+ .disable_ignore_cdac_pwd = true, -+ .has_cvbs_trimming_nvmem_cell = false, -+}; -+ -+static int phy_meson_cvbs_dac_power_on(struct phy *phy) -+{ -+ struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy); -+ -+ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV1], 0x1); -+ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV2], -+ priv->data->cdac_ctrl_resv2_enable_val); -+ regmap_field_write(priv->regs[MESON_CDAC_VREF_ADJ], -+ priv->data->cdac_vref_adj_enable_val); -+ regmap_field_write(priv->regs[MESON_CDAC_RL_ADJ], -+ priv->data->cdac_rl_adj_enable_val); -+ regmap_field_write(priv->regs[MESON_CDAC_GSW], -+ priv->cdac_gsw_enable_val); -+ regmap_field_write(priv->regs[MESON_CDAC_PWD], 0x0); -+ -+ return 0; -+} -+ -+static int phy_meson_cvbs_dac_power_off(struct phy *phy) -+{ -+ struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy); -+ -+ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV1], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV2], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_VREF_ADJ], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_RL_ADJ], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_GSW], 0x0); -+ -+ if (priv->data->disable_ignore_cdac_pwd) -+ regmap_field_write(priv->regs[MESON_CDAC_PWD], 0x0); -+ else -+ regmap_field_write(priv->regs[MESON_CDAC_PWD], 0x1); -+ -+ return 0; -+} -+ -+static int phy_meson_cvbs_dac_init(struct phy *phy) -+{ -+ struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy); -+ -+ regmap_field_write(priv->regs[MESON_CDAC_CLK_PHASE_SEL], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_DRIVER_ADJ], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_EXT_VREF_EN], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_BIAS_C], 0x0); -+ regmap_field_write(priv->regs[MESON_VDAC_CNTL0_RESERVED], 0x0); -+ regmap_field_write(priv->regs[MESON_VDAC_CNTL1_RESERVED], 0x0); -+ -+ return phy_meson_cvbs_dac_power_off(phy); -+} -+ -+static const struct phy_ops phy_meson_cvbs_dac_ops = { -+ .init = phy_meson_cvbs_dac_init, -+ .power_on = phy_meson_cvbs_dac_power_on, -+ .power_off = phy_meson_cvbs_dac_power_off, -+ .owner = THIS_MODULE, -+}; -+ -+static u8 phy_meson_cvbs_trimming_version(u8 trimming1) -+{ -+ if ((trimming1 & 0xf0) == 0xa0) -+ return 5; -+ else if ((trimming1 & 0xf0) == 0x40) -+ return 2; -+ else if ((trimming1 & 0xc0) == 0x80) -+ return 1; -+ else if ((trimming1 & 0xc0) == 0x00) -+ return 0; -+ else -+ return 0xff; -+} -+ -+static int phy_meson_cvbs_read_trimming(struct device *dev, -+ struct phy_meson_cvbs_dac_priv *priv) -+{ -+ struct nvmem_cell *cell; -+ u8 *trimming; -+ size_t len; -+ -+ cell = devm_nvmem_cell_get(dev, "cvbs_trimming"); -+ if (IS_ERR(cell)) -+ return dev_err_probe(dev, PTR_ERR(cell), -+ "Failed to get the 'cvbs_trimming' nvmem-cell\n"); -+ -+ trimming = nvmem_cell_read(cell, &len); -+ if (IS_ERR(trimming)) -+ return dev_err_probe(dev, PTR_ERR(trimming), -+ "Failed to read the 'cvbs_trimming' nvmem-cell\n"); -+ -+ if (len != 2) -+ return dev_err_probe(dev, -EINVAL, -+ "Read the 'cvbs_trimming' nvmem-cell with invalid length\n"); -+ -+ switch (phy_meson_cvbs_trimming_version(trimming[1])) { -+ case 1: -+ case 2: -+ case 5: -+ priv->cdac_gsw_enable_val = trimming[0] & 0x7; -+ break; -+ default: -+ priv->cdac_gsw_enable_val = 0x0; -+ break; -+ } -+ -+ kfree(trimming); -+ -+ return 0; -+} -+ -+static int phy_meson_cvbs_dac_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct phy_meson_cvbs_dac_priv *priv; -+ struct phy_provider *phy_provider; -+ struct device *dev = &pdev->dev; -+ struct regmap *hhi; -+ struct phy *phy; -+ int ret; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->data = device_get_match_data(dev); -+ if (!priv->data) -+ return dev_err_probe(dev, -EINVAL, -+ "Could not find match data\n"); -+ -+ hhi = syscon_node_to_regmap(np->parent); -+ if (IS_ERR(hhi)) -+ return PTR_ERR(hhi); -+ -+ if (priv->data->has_cvbs_trimming_nvmem_cell) { -+ ret = phy_meson_cvbs_read_trimming(dev, priv); -+ if (ret) -+ return ret; -+ } -+ -+ ret = devm_regmap_field_bulk_alloc(dev, hhi, priv->regs, -+ priv->data->reg_fields, -+ MESON_CVBS_DAC_NUM_REGS); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "Failed to create regmap fields\n"); -+ -+ phy = devm_phy_create(dev, np, &phy_meson_cvbs_dac_ops); -+ if (IS_ERR(phy)) -+ return PTR_ERR(phy); -+ -+ phy_set_drvdata(phy, priv); -+ -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id phy_meson_cvbs_dac_of_match[] = { -+ { -+ .compatible = "amlogic,meson8-cvbs-dac", -+ .data = &phy_meson8_cvbs_dac_data, -+ }, -+ { -+ .compatible = "amlogic,meson-gxbb-cvbs-dac", -+ .data = &phy_meson_gxbb_cvbs_dac_data, -+ }, -+ { -+ .compatible = "amlogic,meson-gxl-cvbs-dac", -+ .data = &phy_meson_gxl_cvbs_dac_data, -+ }, -+ { -+ .compatible = "amlogic,meson-g12a-cvbs-dac", -+ .data = &phy_meson_g12a_cvbs_dac_data, -+ }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, phy_meson_cvbs_dac_of_match); -+ -+static struct platform_driver phy_meson_cvbs_dac_driver = { -+ .probe = phy_meson_cvbs_dac_probe, -+ .driver = { -+ .name = "phy-meson-cvbs-dac", -+ .of_match_table = phy_meson_cvbs_dac_of_match, -+ }, -+}; -+module_platform_driver(phy_meson_cvbs_dac_driver); -+ -+MODULE_AUTHOR("Martin Blumenstingl "); -+MODULE_DESCRIPTION("Amlogic Meson CVBS DAC driver"); -+MODULE_LICENSE("GPL v2"); -diff --git a/drivers/phy/amlogic/phy-meson8-hdmi-tx.c b/drivers/phy/amlogic/phy-meson8-hdmi-tx.c -new file mode 100644 -index 000000000000..f9a6572c27d8 ---- /dev/null -+++ b/drivers/phy/amlogic/phy-meson8-hdmi-tx.c -@@ -0,0 +1,160 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Meson8, Meson8b and Meson8m2 HDMI TX PHY. -+ * -+ * Copyright (C) 2021 Martin Blumenstingl -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * Unfortunately there is no detailed documentation available for the -+ * HHI_HDMI_PHY_CNTL0 register. CTL0 and CTL1 is all we know about. -+ * Magic register values in the driver below are taken from the vendor -+ * BSP / kernel. -+ */ -+#define HHI_HDMI_PHY_CNTL0 0x3a0 -+ #define HHI_HDMI_PHY_CNTL0_HDMI_CTL1 GENMASK(31, 16) -+ #define HHI_HDMI_PHY_CNTL0_HDMI_CTL0 GENMASK(15, 0) -+ -+#define HHI_HDMI_PHY_CNTL1 0x3a4 -+ #define HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE BIT(1) -+ #define HHI_HDMI_PHY_CNTL1_SOFT_RESET BIT(0) -+ -+#define HHI_HDMI_PHY_CNTL2 0x3a8 -+ -+struct phy_meson8_hdmi_tx_priv { -+ struct regmap *hhi; -+ struct clk *tmds_clk; -+}; -+ -+static int phy_meson8_hdmi_tx_init(struct phy *phy) -+{ -+ struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy); -+ -+ return clk_prepare_enable(priv->tmds_clk); -+} -+ -+static int phy_meson8_hdmi_tx_exit(struct phy *phy) -+{ -+ struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy); -+ -+ clk_disable_unprepare(priv->tmds_clk); -+ -+ return 0; -+} -+ -+static int phy_meson8_hdmi_tx_power_on(struct phy *phy) -+{ -+ struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy); -+ unsigned int i; -+ u16 hdmi_ctl0; -+ -+ if (clk_get_rate(priv->tmds_clk) >= 2970UL * 1000 * 1000) -+ hdmi_ctl0 = 0x1e8b; -+ else -+ hdmi_ctl0 = 0x4d0b; -+ -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, -+ FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL1, 0x08c3) | -+ FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL0, hdmi_ctl0)); -+ -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, 0x0); -+ -+ /* Reset three times, just like the vendor driver does */ -+ for (i = 0; i < 3; i++) { -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, -+ HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE | -+ HHI_HDMI_PHY_CNTL1_SOFT_RESET); -+ usleep_range(1000, 2000); -+ -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, -+ HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE); -+ usleep_range(1000, 2000); -+ } -+ -+ return 0; -+} -+ -+static int phy_meson8_hdmi_tx_power_off(struct phy *phy) -+{ -+ struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy); -+ -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, -+ FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL1, 0x0841) | -+ FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL0, 0x8d00)); -+ -+ return 0; -+} -+ -+static const struct phy_ops phy_meson8_hdmi_tx_ops = { -+ .init = phy_meson8_hdmi_tx_init, -+ .exit = phy_meson8_hdmi_tx_exit, -+ .power_on = phy_meson8_hdmi_tx_power_on, -+ .power_off = phy_meson8_hdmi_tx_power_off, -+ .owner = THIS_MODULE, -+}; -+ -+static int phy_meson8_hdmi_tx_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct phy_meson8_hdmi_tx_priv *priv; -+ struct phy_provider *phy_provider; -+ struct resource *res; -+ struct phy *phy; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) -+ return -EINVAL; -+ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->hhi = syscon_node_to_regmap(np->parent); -+ if (IS_ERR(priv->hhi)) -+ return PTR_ERR(priv->hhi); -+ -+ priv->tmds_clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->tmds_clk)) -+ return PTR_ERR(priv->tmds_clk); -+ -+ phy = devm_phy_create(&pdev->dev, np, &phy_meson8_hdmi_tx_ops); -+ if (IS_ERR(phy)) -+ return PTR_ERR(phy); -+ -+ phy_set_drvdata(phy, priv); -+ -+ phy_provider = devm_of_phy_provider_register(&pdev->dev, -+ of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id phy_meson8_hdmi_tx_of_match[] = { -+ { .compatible = "amlogic,meson8-hdmi-tx-phy" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, phy_meson8_hdmi_tx_of_match); -+ -+static struct platform_driver phy_meson8_hdmi_tx_driver = { -+ .probe = phy_meson8_hdmi_tx_probe, -+ .driver = { -+ .name = "phy-meson8-hdmi-tx", -+ .of_match_table = phy_meson8_hdmi_tx_of_match, -+ }, -+}; -+module_platform_driver(phy_meson8_hdmi_tx_driver); -+ -+MODULE_AUTHOR("Martin Blumenstingl "); -+MODULE_DESCRIPTION("Meson8, Meson8b and Meson8m2 HDMI TX PHY driver"); -+MODULE_LICENSE("GPL v2"); -diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h -index f33781338eda..78aa07fd7cc0 100644 ---- a/include/dt-bindings/clock/meson8b-clkc.h -+++ b/include/dt-bindings/clock/meson8b-clkc.h -@@ -105,6 +105,16 @@ - #define CLKID_PERIPH 126 - #define CLKID_AXI 128 - #define CLKID_L2_DRAM 130 -+#define CLKID_HDMI_PLL_HDMI_OUT 132 -+#define CLKID_VID_PLL_FINAL_DIV 137 -+#define CLKID_VCLK_IN_SEL 138 -+#define CLKID_VCLK2_IN_SEL 149 -+#define CLKID_CTS_ENCT 161 -+#define CLKID_CTS_ENCP 163 -+#define CLKID_CTS_ENCI 165 -+#define CLKID_HDMI_TX_PIXEL 167 -+#define CLKID_CTS_ENCL 169 -+#define CLKID_CTS_VDAC0 171 - #define CLKID_HDMI_SYS 174 - #define CLKID_VPU 190 - #define CLKID_VDEC_1 196 --- -2.34.1 - diff --git a/patch/kernel/meson-current b/patch/kernel/meson-current index 2f8d67256..76bf5f824 120000 --- a/patch/kernel/meson-current +++ b/patch/kernel/meson-current @@ -1 +1 @@ -archive/meson-5.15 \ No newline at end of file +archive/meson-6.1 \ No newline at end of file