archr/hardkernel-uboot
0
0
Fork 0
mirror of https://github.com/archr-linux/hardkernel-uboot.git synced 2026-03-31 15:05:07 -07:00
Code Issues Packages Projects Releases Wiki Activity

Remove legacy NAND and disk on chip references from boards.

Browse Source 
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Scott Wood
2009-07-16 19:08:04 -05:00
parent be33b046b5
commit 2419169f57
43 changed files with 0 additions and 1053 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
board/delta/nand.c
View File

@@ -23,7 +23,6 @@
#include <common.h>
#if defined(CONFIG_CMD_NAND)
#if !defined(CONFIG_NAND_LEGACY)
#include <nand.h>
#include <asm/arch/pxa-regs.h>
@@ -550,7 +549,4 @@ int board_nand_init(struct nand_chip *nand)
return 0;
}
#else
#error "U-Boot legacy NAND support not available for Monahans DFC."
#endif
#endif

50
board/esd/common/auto_update.c
View File

@@ -27,9 +27,6 @@
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
#if defined(CONFIG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
#endif
#include <fat.h>
#include <part.h>
@@ -58,20 +55,6 @@ extern int flash_sect_erase(ulong, ulong);
extern int flash_sect_protect (int, ulong, ulong);
extern int flash_write (char *, ulong, ulong);
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
/* references to names in cmd_nand.c */
#define NANDRW_READ 0x01
#define NANDRW_WRITE 0x00
#define NANDRW_JFFS2 0x02
#define NANDRW_JFFS2_SKIP 0x04
extern struct nand_chip nand_dev_desc[];
extern int nand_legacy_rw(struct nand_chip* nand, int cmd,
size_t start, size_t len,
size_t * retlen, u_char * buf);
extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs,
size_t len, int clean);
#endif
extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
int au_check_cksum_valid(int i, long nbytes)
@@ -158,9 +141,6 @@ int au_do_update(int i, long sz)
int off, rc;
uint nbytes;
int k;
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
int total;
#endif
hdr = (image_header_t *)LOAD_ADDR;
#if defined(CONFIG_FIT)
@@ -240,15 +220,6 @@ int au_do_update(int i, long sz)
au_image[i].name);
debug ("flash_sect_erase(%lx, %lx);\n", start, end);
flash_sect_erase (start, end);
} else {
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
printf ("Updating NAND FLASH with image %s\n",
au_image[i].name);
debug ("nand_legacy_erase(%lx, %lx);\n", start, end);
rc = nand_legacy_erase (nand_dev_desc, start,
end - start + 1, 0);
debug ("nand_legacy_erase returned %x\n", rc);
#endif
}
udelay(10000);
@@ -273,18 +244,7 @@ int au_do_update(int i, long sz)
rc = flash_write ((char *)addr, start,
(nbytes + 1) & ~1);
} else {
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
debug ("nand_legacy_rw(%p, %lx, %x)\n",
addr, start, nbytes);
rc = nand_legacy_rw (nand_dev_desc,
NANDRW_WRITE | NANDRW_JFFS2,
start, nbytes, (size_t *)&total,
(uchar *)addr);
debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n",
rc, total, nbytes);
#else
rc = -1;
#endif
}
if (rc != 0) {
printf ("Flashing failed due to error %d\n", rc);
@@ -297,16 +257,6 @@ int au_do_update(int i, long sz)
if (au_image[i].type != AU_NAND) {
rc = crc32 (0, (uchar *)(start + off),
image_get_data_size (hdr));
} else {
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
rc = nand_legacy_rw (nand_dev_desc,
NANDRW_READ | NANDRW_JFFS2 |
NANDRW_JFFS2_SKIP,
start, nbytes, (size_t *)&total,
(uchar *)addr);
rc = crc32 (0, (uchar *)(addr + off),
image_get_data_size (hdr));
#endif
}
if (rc != image_get_dcrc (hdr)) {
printf ("Image %s Bad Data Checksum After COPY\n",

15
board/g2000/g2000.c
View File

@@ -148,21 +148,6 @@ phys_size_t initdram (int board_type)
return ret;
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CONFIG_SYS_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif
#if 0 /* test-only !!! */
int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{

16
board/netphone/netphone.c
View File

@@ -597,22 +597,6 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen;
totlen = nand_probe(CONFIG_SYS_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)

15
board/netta/netta.c
View File

@@ -555,21 +555,6 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_init(void)

16
board/netta2/netta2.c
View File

@@ -595,22 +595,6 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen;
totlen = nand_probe(CONFIG_SYS_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)

15
board/netvia/netvia.c
View File

@@ -415,18 +415,3 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif

23
board/omap2420h4/omap2420h4.c
View File

@@ -31,10 +31,6 @@
#include <asm/arch/mem.h>
#include <i2c.h>
#include <asm/mach-types.h>
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -846,22 +842,3 @@ void update_mux(u32 btype,u32 mtype)
}
}
}
#if defined(CONFIG_CMD_NAND)
void nand_init(void)
{
extern flash_info_t flash_info[];
nand_probe(CONFIG_SYS_NAND_ADDR);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
#ifdef CONFIG_SYS_JFFS2_MEM_NAND
flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */
flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
#endif
}
#endif

11
board/samsung/smdk6400/smdk6400.c
View File

@@ -107,17 +107,6 @@ ulong virt_to_phy_smdk6400(ulong addr)
}
#endif
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_SYS_NAND_LEGACY)
#include <linux/mtd/nand.h>
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CONFIG_SYS_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN)
print_size(nand_dev_desc[0].totlen, "\n");
}
#endif
ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI boot flash */

5
board/sixnet/sixnet.c
View File

@@ -33,11 +33,6 @@
# include <status_led.h>
#endif
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
#endif
DECLARE_GLOBAL_DATA_PTR;
#define ORMASK(size) ((-size) & OR_AM_MSK)

16
board/stxxtc/stxxtc.c
View File

@@ -574,22 +574,6 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen;
totlen = nand_probe(CONFIG_SYS_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)

4
board/zylonite/nand.c
View File

@@ -23,7 +23,6 @@
#include <common.h>
#if defined(CONFIG_CMD_NAND)
#ifdef CONFIG_NEW_NAND_CODE
#include <nand.h>
#include <asm/arch/pxa-regs.h>
@@ -554,7 +553,4 @@ int board_nand_init(struct nand_chip *nand)
return 0;
}
#else
#error "U-Boot legacy NAND support not available for Monahans DFC."
#endif
#endif

4
include/configs/BMW.h
View File

@@ -81,13 +81,9 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DOC
#define CONFIG_CMD_ELF
/* CONFIG_CMD_DOC required legacy NAND support */
#define CONFIG_NAND_LEGACY
#if 0
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */

8
include/configs/CATcenter.h
View File

@@ -209,16 +209,8 @@
/* For CATcenter there is only NAND on the module */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define NAND_NO_RB
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */

10
include/configs/CPU86.h
View File

@@ -145,15 +145,6 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*-----------------------------------------------------------------------
* Disk-On-Chip configuration
*/
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
/*-----------------------------------------------------------------------
* Miscellaneous configuration options
*/
@@ -179,7 +170,6 @@
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS

4
include/configs/CPU87.h
View File

@@ -182,7 +182,6 @@
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
@@ -190,9 +189,6 @@
#define CONFIG_CMD_PCI
#endif
#define CONFIG_NAND_LEGACY
/*
* Miscellaneous configurable options
*/

20
include/configs/G2000.h
View File

@@ -196,32 +196,12 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CONFIG_SYS_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#endif
/*-----------------------------------------------------------------------

17
include/configs/GEN860T.h
View File

@@ -244,10 +244,6 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_BEDBUG
#if !defined(CONFIG_SC)
#define CONFIG_CMD_DOC
#endif
#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif
@@ -279,9 +275,6 @@
#define CONFIG_FPGA_VIRTEX2
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_NAND_LEGACY
/*
* Verbose help from command monitor.
*/
@@ -737,16 +730,6 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Disk On Chip (millenium) configuration
*/
#if !defined(CONFIG_SC)
#define CONFIG_SYS_MAX_DOC_DEVICE 1
#undef CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
#undef CONFIG_SYS_DOC_PASSIVE_PROBE
#endif
/*
* FEC interrupt assignment
*/

10
include/configs/MIP405.h
View File

@@ -84,12 +84,9 @@
#if !defined(CONFIG_MIP405T)
#define CONFIG_CMD_USB
#define CONFIG_CMD_DOC
#endif
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/**************************************************************
@@ -383,13 +380,6 @@
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */
/************************************************************
* Disk-On-Chip configuration
************************************************************/
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CONFIG_SYS_DOC_SHORT_TIMEOUT
#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
/************************************************************
* Keyboard support
************************************************************/

86
include/configs/NETPHONE.h
View File

@@ -497,95 +497,9 @@
#define DSP_BASE 0xF1000000
#define NAND_BASE 0xF1010000
/****************************************************************/
/* NAND */
#define CONFIG_NAND_LEGACY
#define CONFIG_SYS_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
#define NAND_DISABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
} while(0)
#define NAND_ENABLE_CE(nand) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
} while(0)
#define NAND_CTL_CLRALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
} while(0)
#define NAND_CTL_SETALE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
} while(0)
#define NAND_CTL_SETCLE(nandptr) \
do { \
(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
} while(0)
#if CONFIG_NETPHONE_VERSION == 1
#define NAND_WAIT_READY(nand) \
do { \
int _tries = 0; \
while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
if (++_tries > 100000) \
break; \
} while (0)
#elif CONFIG_NETPHONE_VERSION == 2
#define NAND_WAIT_READY(nand) \
do { \
int _tries = 0; \
while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
if (++_tries > 100000) \
break; \
} while (0)
#endif
#define WRITE_NAND_COMMAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND_ADDRESS(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define READ_NAND(adr) \
((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
#define CONFIG_SYS_DIRECT_NAND_TFTP
/*****************************************************************************/

Some files were not shown because too many files have changed in this diff Show More