mirror of
https://github.com/archr-linux/Arch-R.git
synced 2026-03-31 14:41:55 -07:00
Jernej Skrabec
67 lines
2.2 KiB
Diff
67 lines
2.2 KiB
Diff
From edfe1a6c99aff85e97dc1600355a66bbcb417531 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Thu, 12 Oct 2023 20:25:42 +0200
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Subject: [PATCH 22/25] clk: sunxi-ng: h6: Reparent CPUX during PLL CPUX rate
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change
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While PLL CPUX clock rate change when CPU is running from it works in
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vast majority of cases, now and then it causes instability. This leads
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to system crashes and other undefined behaviour. After a lot of testing
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(30+ hours) while also doing a lot of frequency switches, we can't
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observe any instability issues anymore when doing reparenting to stable
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clock like 24 MHz oscillator.
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Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
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Link: https://forum.libreelec.tv/thread/27295-orange-pi-3-lts-freezes/
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Reported-by: Chad Wagner <wagnerch42@gmail.com>
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Tested-by: Chad Wagner <wagnerch42@gmail.com>
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 19 +++++++++++++++++--
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1 file changed, 17 insertions(+), 2 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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index 42568c616181..892df807275c 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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@@ -1181,11 +1181,18 @@ static const u32 usb2_clk_regs[] = {
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SUN50I_H6_USB3_CLK_REG,
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};
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+static struct ccu_mux_nb sun50i_h6_cpu_nb = {
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+ .common = &cpux_clk.common,
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+ .cm = &cpux_clk.mux,
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+ .delay_us = 1,
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+ .bypass_index = 0, /* index of 24 MHz oscillator */
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+};
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+
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static int sun50i_h6_ccu_probe(struct platform_device *pdev)
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{
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void __iomem *reg;
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+ int i, ret;
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u32 val;
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- int i;
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reg = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg))
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@@ -1252,7 +1259,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
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val |= BIT(24);
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writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG);
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- return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc);
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+ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc);
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+ if (ret)
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+ return ret;
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+
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+ /* Reparent CPU during PLL CPUX rate changes */
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+ ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
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+ &sun50i_h6_cpu_nb);
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+
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+ return 0;
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}
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static const struct of_device_id sun50i_h6_ccu_ids[] = {
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--
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2.42.0
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