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786MHz failed the hardware boot test on the Soysauce: the screen lights and the SoC resets in a loop before U-Boot, meaning the TPL DDR training does not converge at that speed on these chips (dArkOS only reaches 786 via the BSP dmc driver's runtime retraining, which is gentler than a fixed cold init). 666MHz keeps twice the bandwidth of the old 333MHz baseline; 528 (dArkOS's powersave floor) is the next step down if any board still fails. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>