diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0120-20250728_konradybcio_gpu_cc_power_requirements_reality_check.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0120-20250728_konradybcio_gpu_cc_power_requirements_reality_check.patch new file mode 100644 index 0000000000..4f96196809 --- /dev/null +++ b/projects/ROCKNIX/devices/SM8550/patches/linux/0120-20250728_konradybcio_gpu_cc_power_requirements_reality_check.patch @@ -0,0 +1,39 @@ +From git@z Thu Jan 1 00:00:00 1970 +Subject: [PATCH RFC 22/24] arm64: dts: qcom: sm8550: Describe GPU_CC power + plumbing requirements +From: Konrad Dybcio +Date: Mon, 28 Jul 2025 18:16:22 +0200 +Message-Id: <20250728-topic-gpucc_power_plumbing-v1-22-09c2480fe3e6@oss.qualcomm.com> +MIME-Version: 1.0 +Content-Type: text/plain; charset="utf-8" +Content-Transfer-Encoding: 7bit + +A number of power rails must be powered on in order for GPU_CC to +function. Ensure that's conveyed to the OS. + +Fixes: 9f7579423d2d ("arm64: dts: qcom: sm8550: Add graphics clock controller") +Signed-off-by: Konrad Dybcio +--- + arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi +index 45713d46f3c52487d2638b7ab194c111f58679ce..28eade49526dc9bb0a7b211f96dd350873489029 100644 +--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi ++++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi +@@ -2572,6 +2572,12 @@ gpucc: clock-controller@3d90000 { + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; ++ ++ power-domains = <&rpmhpd RPMHPD_CX>, ++ <&rpmhpd RPMHPD_MX>, ++ <&rpmhpd RPMHPD_GFX>, ++ <&rpmhpd RPMHPD_MXC>; ++ + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; +-- +2.50.1 + diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0122-interconnect__qcom__sm8550__Enable_QoS_configuration.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0122-interconnect__qcom__sm8550__Enable_QoS_configuration.patch new file mode 100644 index 0000000000..b8bff53855 --- /dev/null +++ b/projects/ROCKNIX/devices/SM8550/patches/linux/0122-interconnect__qcom__sm8550__Enable_QoS_configuration.patch @@ -0,0 +1,606 @@ +From 3153e9661a2279861e5a4af40d7af42d56d3311f Mon Sep 17 00:00:00 2001 +From: map220v +Date: Fri, 8 Aug 2025 17:20:23 +0000 +Subject: [PATCH] interconnect: qcom: sm8550: Enable QoS configuration + +--- + drivers/interconnect/qcom/sm8550.c | 295 +++++++++++++++++++++++++++++ + 1 file changed, 295 insertions(+) + +diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c +index fdb97d1f1d07..cba6dc8ab819 100644 +--- a/drivers/interconnect/qcom/sm8550.c ++++ b/drivers/interconnect/qcom/sm8550.c +@@ -25,6 +25,13 @@ static struct qcom_icc_node qhm_qspi = { + .id = SM8550_MASTER_QSPI_0, + .channels = 1, + .buswidth = 4, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xb000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A1NOC_SNOC }, + }; +@@ -34,6 +41,13 @@ static struct qcom_icc_node qhm_qup1 = { + .id = SM8550_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xc000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A1NOC_SNOC }, + }; +@@ -43,6 +57,13 @@ static struct qcom_icc_node xm_sdc4 = { + .id = SM8550_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xd000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A1NOC_SNOC }, + }; +@@ -52,6 +73,13 @@ static struct qcom_icc_node xm_ufs_mem = { + .id = SM8550_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 16, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xe000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A1NOC_SNOC }, + }; +@@ -61,6 +89,13 @@ static struct qcom_icc_node xm_usb3_0 = { + .id = SM8550_MASTER_USB3_0, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xf000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A1NOC_SNOC }, + }; +@@ -70,6 +105,13 @@ static struct qcom_icc_node qhm_qdss_bam = { + .id = SM8550_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x12000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A2NOC_SNOC }, + }; +@@ -79,6 +121,13 @@ static struct qcom_icc_node qhm_qup2 = { + .id = SM8550_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x13000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A2NOC_SNOC }, + }; +@@ -88,6 +137,13 @@ static struct qcom_icc_node qxm_crypto = { + .id = SM8550_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x15000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 1, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A2NOC_SNOC }, + }; +@@ -97,6 +153,13 @@ static struct qcom_icc_node qxm_ipa = { + .id = SM8550_MASTER_IPA, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x16000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 1, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A2NOC_SNOC }, + }; +@@ -115,6 +178,13 @@ static struct qcom_icc_node xm_qdss_etr_0 = { + .id = SM8550_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x17000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A2NOC_SNOC }, + }; +@@ -124,6 +194,13 @@ static struct qcom_icc_node xm_qdss_etr_1 = { + .id = SM8550_MASTER_QDSS_ETR_1, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x18000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A2NOC_SNOC }, + }; +@@ -133,6 +210,13 @@ static struct qcom_icc_node xm_sdc2 = { + .id = SM8550_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x19000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_A2NOC_SNOC }, + }; +@@ -219,6 +303,13 @@ static struct qcom_icc_node alm_gpu_tcu = { + .id = SM8550_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xb1000 }, ++ .prio_fwd_disable = 1, ++ .prio = 1, ++ .urg_fwd = 0, ++ }, + .num_links = 2, + .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + }; +@@ -228,6 +319,13 @@ static struct qcom_icc_node alm_sys_tcu = { + .id = SM8550_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xb3000 }, ++ .prio_fwd_disable = 1, ++ .prio = 6, ++ .urg_fwd = 0, ++ }, + .num_links = 2, + .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + }; +@@ -247,6 +345,13 @@ static struct qcom_icc_node qnm_gpu = { + .id = SM8550_MASTER_GFX3D, + .channels = 2, + .buswidth = 32, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 2, ++ .port_offsets = { 0x31000, 0x71000 }, ++ .prio_fwd_disable = 1, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 2, + .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + }; +@@ -256,6 +361,13 @@ static struct qcom_icc_node qnm_lpass_gemnoc = { + .id = SM8550_MASTER_LPASS_GEM_NOC, + .channels = 1, + .buswidth = 16, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xb5000 }, ++ .prio_fwd_disable = 0, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 3, + .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, + SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, +@@ -276,6 +388,13 @@ static struct qcom_icc_node qnm_mnoc_hf = { + .id = SM8550_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 2, ++ .port_offsets = { 0x33000, 0x73000 }, ++ .prio_fwd_disable = 0, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 2, + .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + }; +@@ -285,6 +404,13 @@ static struct qcom_icc_node qnm_mnoc_sf = { + .id = SM8550_MASTER_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 2, ++ .port_offsets = { 0x35000, 0x75000 }, ++ .prio_fwd_disable = 0, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 2, + .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + }; +@@ -294,6 +420,13 @@ static struct qcom_icc_node qnm_nsp_gemnoc = { + .id = SM8550_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 2, ++ .port_offsets = { 0x37000, 0x77000 }, ++ .prio_fwd_disable = 1, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 2, + .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + }; +@@ -303,6 +436,13 @@ static struct qcom_icc_node qnm_pcie = { + .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xb7000 }, ++ .prio_fwd_disable = 0, ++ .prio = 2, ++ .urg_fwd = 1, ++ }, + .num_links = 2, + .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + }; +@@ -312,6 +452,13 @@ static struct qcom_icc_node qnm_snoc_gc = { + .id = SM8550_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xb9000 }, ++ .prio_fwd_disable = 0, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_LLCC }, + }; +@@ -321,6 +468,13 @@ static struct qcom_icc_node qnm_snoc_sf = { + .id = SM8550_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xbb000 }, ++ .prio_fwd_disable = 0, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 3, + .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, + SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, +@@ -367,6 +521,13 @@ static struct qcom_icc_node qnm_camnoc_hf = { + .id = SM8550_MASTER_CAMNOC_HF, + .channels = 2, + .buswidth = 32, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 2, ++ .port_offsets = { 0x28000, 0x29000 }, ++ .prio_fwd_disable = 0, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC }, + }; +@@ -376,6 +537,13 @@ static struct qcom_icc_node qnm_camnoc_icp = { + .id = SM8550_MASTER_CAMNOC_ICP, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x2a000 }, ++ .prio_fwd_disable = 1, ++ .prio = 4, ++ .urg_fwd = 1, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + }; +@@ -385,6 +553,13 @@ static struct qcom_icc_node qnm_camnoc_sf = { + .id = SM8550_MASTER_CAMNOC_SF, + .channels = 2, + .buswidth = 32, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 2, ++ .port_offsets = { 0x2b000, 0x2c000 }, ++ .prio_fwd_disable = 0, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + }; +@@ -394,6 +569,13 @@ static struct qcom_icc_node qnm_mdp = { + .id = SM8550_MASTER_MDP, + .channels = 2, + .buswidth = 32, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 2, ++ .port_offsets = { 0x2d000, 0x2e000 }, ++ .prio_fwd_disable = 0, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC }, + }; +@@ -412,6 +594,13 @@ static struct qcom_icc_node qnm_video = { + .id = SM8550_MASTER_VIDEO, + .channels = 2, + .buswidth = 32, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 2, ++ .port_offsets = { 0x30000, 0x31000 }, ++ .prio_fwd_disable = 0, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + }; +@@ -421,6 +610,13 @@ static struct qcom_icc_node qnm_video_cv_cpu = { + .id = SM8550_MASTER_VIDEO_CV_PROC, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x32000 }, ++ .prio_fwd_disable = 1, ++ .prio = 4, ++ .urg_fwd = 1, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + }; +@@ -430,6 +626,13 @@ static struct qcom_icc_node qnm_video_cvp = { + .id = SM8550_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 32, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x33000 }, ++ .prio_fwd_disable = 0, ++ .prio = 0, ++ .urg_fwd = 1, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + }; +@@ -439,6 +642,13 @@ static struct qcom_icc_node qnm_video_v_cpu = { + .id = SM8550_MASTER_VIDEO_V_PROC, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x34000 }, ++ .prio_fwd_disable = 1, ++ .prio = 4, ++ .urg_fwd = 1, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + }; +@@ -475,6 +685,13 @@ static struct qcom_icc_node xm_pcie3_0 = { + .id = SM8550_MASTER_PCIE_0, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xb000 }, ++ .prio_fwd_disable = 1, ++ .prio = 3, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC }, + }; +@@ -484,6 +701,13 @@ static struct qcom_icc_node xm_pcie3_1 = { + .id = SM8550_MASTER_PCIE_1, + .channels = 1, + .buswidth = 16, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0xc000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC }, + }; +@@ -493,6 +717,13 @@ static struct qcom_icc_node qhm_gic = { + .id = SM8550_MASTER_GIC_AHB, + .channels = 1, + .buswidth = 4, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x1c000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF }, + }; +@@ -520,6 +751,13 @@ static struct qcom_icc_node xm_gic = { + .id = SM8550_MASTER_GIC, + .channels = 1, + .buswidth = 8, ++ .qosbox = &(const struct qcom_icc_qosbox) { ++ .num_ports = 1, ++ .port_offsets = { 0x1d000 }, ++ .prio_fwd_disable = 1, ++ .prio = 2, ++ .urg_fwd = 0, ++ }, + .num_links = 1, + .links = { SM8550_SLAVE_SNOC_GEM_NOC_GC }, + }; +@@ -1295,11 +1533,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, + }; + ++static const struct regmap_config sm8550_aggre1_noc_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x14400, ++ .fast_io = true, ++}; ++ + static const struct qcom_icc_desc sm8550_aggre1_noc = { ++ .config = &sm8550_aggre1_noc_regmap_config, + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), + .bcms = aggre1_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), ++ .qos_requires_clocks = true, + }; + + static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { +@@ -1318,11 +1566,21 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, + }; + ++static const struct regmap_config sm8550_aggre2_noc_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x1e400, ++ .fast_io = true, ++}; ++ + static const struct qcom_icc_desc sm8550_aggre2_noc = { ++ .config = &sm8550_aggre2_noc_regmap_config, + .nodes = aggre2_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), + .bcms = aggre2_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), ++ .qos_requires_clocks = true, + }; + + static struct qcom_icc_bcm * const clk_virt_bcms[] = { +@@ -1454,7 +1712,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, + }; + ++static const struct regmap_config sm8550_gem_noc_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0xbb800, ++ .fast_io = true, ++}; ++ + static const struct qcom_icc_desc sm8550_gem_noc = { ++ .config = &sm8550_gem_noc_regmap_config, + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, +@@ -1545,7 +1812,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, + }; + ++static const struct regmap_config sm8550_mmss_noc_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x5b800, ++ .fast_io = true, ++}; ++ + static const struct qcom_icc_desc sm8550_mmss_noc = { ++ .config = &sm8550_mmss_noc_regmap_config, + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, +@@ -1580,11 +1856,21 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { + [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, + }; + ++static const struct regmap_config sm8550_pcie_anoc_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x12200, ++ .fast_io = true, ++}; ++ + static const struct qcom_icc_desc sm8550_pcie_anoc = { ++ .config = &sm8550_pcie_anoc_regmap_config, + .nodes = pcie_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), + .bcms = pcie_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), ++ .qos_requires_clocks = true, + }; + + static struct qcom_icc_bcm * const system_noc_bcms[] = { +@@ -1603,7 +1889,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = { + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + }; + ++static const struct regmap_config sm8550_system_noc_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x1d080, ++ .fast_io = true, ++}; ++ + static const struct qcom_icc_desc sm8550_system_noc = { ++ .config = &sm8550_system_noc_regmap_config, + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms,