diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0032_drm-panel--Add-panel-driver-for-Chipone-ICNA3512-b.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0032_drm-panel--Add-panel-driver-for-Chipone-ICNA3512-b.patch index 6d4db21c84..f64bd07ae8 100644 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0032_drm-panel--Add-panel-driver-for-Chipone-ICNA3512-b.patch +++ b/projects/ROCKNIX/devices/SM8550/patches/linux/0032_drm-panel--Add-panel-driver-for-Chipone-ICNA3512-b.patch @@ -50,7 +50,7 @@ new file mode 100644 index 000000000000..cbda976df1db --- /dev/null +++ b/drivers/gpu/drm/panel/panel-chipone-icna3512.c -@@ -0,0 +1,473 @@ +@@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Chipone ICNA3512 Driver IC panels driver @@ -84,7 +84,7 @@ index 000000000000..cbda976df1db + enum drm_panel_orientation orientation; + + struct gpio_desc *reset_gpio; -+ struct regulator_bulk_data supplies[3]; ++ struct regulator_bulk_data *supplies; +}; + +struct panel_desc { @@ -103,6 +103,14 @@ index 000000000000..cbda976df1db + struct drm_dsc_config dsc; +}; + ++static const struct regulator_bulk_data panel_supplies[] = { ++ { .supply = "vdd" }, ++ { .supply = "vddio" }, ++ { .supply = "vci" }, ++ { .supply = "disp" }, ++ { .supply = "blvdd" }, ++}; ++ +static inline struct panel_info *to_panel_info(struct drm_panel *panel) +{ + return container_of(panel, struct panel_info, panel); @@ -132,73 +140,61 @@ index 000000000000..cbda976df1db + +static int icna3512_init_sequence(struct panel_info *pinfo) +{ -+ struct mipi_dsi_device *dsi = pinfo->dsi; -+ struct device *dev = &dsi->dev; -+ int ret; ++ struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->dsi }; + + int cur_mode = icna3512_get_current_mode(pinfo); + int cur_vrefresh = drm_mode_vrefresh(&pinfo->desc->modes[cur_mode]); + -+ mipi_dsi_dcs_write_seq(dsi, 0x9F, 0x01); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9F, 0x01); + if (cur_vrefresh == 120) { -+ -+ mipi_dsi_dcs_write_seq(dsi, 0xB3, ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB3, + 0x00, 0xE0, 0xA0, 0x10, 0xC8, 0x00, 0x02, 0x83, + 0x00, 0x10, 0x14, 0x00, 0x00, 0xC3, 0x00, 0x10, + 0x14, 0x00, 0x00, 0xE0, 0x10, 0x10, 0x9C, 0x00, + 0x00, 0xE0, 0xA0, 0x10, 0xC8, 0x22, 0x18, 0x18, + 0x18, 0x18, 0x18); -+ mipi_dsi_dcs_write_seq(dsi, 0x9F, 0x07); -+ mipi_dsi_dcs_write_seq(dsi, 0xB5, ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9F, 0x07); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB5, + 0x04, 0x0C, 0x08, 0x0C, 0x04, 0x00, 0xC4); -+ mipi_dsi_dcs_write_seq(dsi, 0xD9, ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD9, + 0x88, 0x40, 0x40, 0x88, 0x40, 0x40, 0x00, 0xEB, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); -+ mipi_dsi_dcs_write_seq(dsi, 0xCE, ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCE, + 0x01, 0x01, 0x01, 0x01, 0x04, 0x09, 0x2C); -+ mipi_dsi_dcs_write_seq(dsi, 0x48, 0x00); -+ mipi_dsi_dcs_write_seq(dsi, 0x48, 0x30); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x00); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x30); + } + else { -+ mipi_dsi_dcs_write_seq(dsi, 0xB3, ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB3, + 0x00, 0xE0, 0xA0, 0x10, 0xC8, 0x00); -+ mipi_dsi_dcs_write_seq(dsi, 0x9F, 0x07); -+ mipi_dsi_dcs_write_seq(dsi, 0xB2, ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9F, 0x07); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB2, + 0x04, 0x18, 0x08, 0x0C, 0x02, 0x00, 0xC4); -+ mipi_dsi_dcs_write_seq(dsi, 0xD3, ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD3, + 0x88, 0x4A, 0x4A, 0x88, 0x4A, 0x4A, 0x00, 0xEB, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); -+ mipi_dsi_dcs_write_seq(dsi, 0xCB, ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCB, + 0x01, 0x01, 0x01, 0x01, 0x04, 0x09, 0x2C); -+ mipi_dsi_dcs_write_seq(dsi, 0x48, 0x30); -+ mipi_dsi_dcs_write_seq(dsi, 0x48, 0x00); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x30); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x00); + } + -+ mipi_dsi_dcs_write_seq(dsi, 0x9C, 0xA5, 0xA5); -+ mipi_dsi_dcs_write_seq(dsi, 0xFD, 0x5A, 0x5A); -+ mipi_dsi_dcs_write_seq(dsi, 0x48, 0x00); -+ mipi_dsi_dcs_write_seq(dsi, 0x53, 0xE0); -+ mipi_dsi_dcs_write_seq(dsi, 0x35, 0x00); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9C, 0xA5, 0xA5); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFD, 0x5A, 0x5A); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x00); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0xE0); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x00); + -+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi); -+ if (ret < 0) { -+ dev_err(dev, "failed to exit sleep mode: %d\n", ret); -+ return ret; -+ } ++ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + -+ mipi_dsi_dcs_write_seq(dsi, 0x51, 0x0D, 0xBB); -+ mipi_dsi_dcs_write_seq(dsi, 0x9F, 0x0F); -+ mipi_dsi_dcs_write_seq(dsi, 0xCE, 0x22); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0D, 0xBB); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9F, 0x0F); ++ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCE, 0x22); + -+ msleep(120); ++ mipi_dsi_msleep(&dsi_ctx, 120); ++ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + -+ ret = mipi_dsi_dcs_set_display_on(dsi); -+ if (ret < 0) { -+ dev_err(dev, "failed to set display on: %d\n", ret); -+ return ret; -+ } -+ -+ return 0; ++ return dsi_ctx.accum_err; +} + +static const struct drm_display_mode icna3512_modes[] = { @@ -266,7 +262,7 @@ index 000000000000..cbda976df1db + struct drm_dsc_picture_parameter_set pps; + int ret; + -+ ret = regulator_bulk_enable(ARRAY_SIZE(pinfo->supplies), pinfo->supplies); ++ ret = regulator_bulk_enable(ARRAY_SIZE(panel_supplies), pinfo->supplies); + if (ret < 0) { + dev_err(panel->dev, "failed to enable regulators: %d\n", ret); + return ret; @@ -276,7 +272,7 @@ index 000000000000..cbda976df1db + + ret = pinfo->desc->init_sequence(pinfo); + if (ret < 0) { -+ regulator_bulk_disable(ARRAY_SIZE(pinfo->supplies), pinfo->supplies); ++ regulator_bulk_disable(ARRAY_SIZE(panel_supplies), pinfo->supplies); + dev_err(panel->dev, "failed to initialize panel: %d\n", ret); + return ret; + } @@ -302,21 +298,14 @@ index 000000000000..cbda976df1db +static int icna3512_disable(struct drm_panel *panel) +{ + struct panel_info *pinfo = to_panel_info(panel); -+ int ret; ++ struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->dsi }; + -+ ret = mipi_dsi_dcs_set_display_off(pinfo->dsi); -+ if (ret < 0) -+ dev_err(&pinfo->dsi->dev, "failed to set display off: %d\n", ret); ++ mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); ++ mipi_dsi_msleep(&dsi_ctx, 50); ++ mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); ++ mipi_dsi_msleep(&dsi_ctx, 120); + -+ msleep(50); -+ -+ ret = mipi_dsi_dcs_enter_sleep_mode(pinfo->dsi); -+ if (ret < 0) -+ dev_err(&pinfo->dsi->dev, "failed to enter sleep mode: %d\n", ret); -+ -+ msleep(120); -+ -+ return 0; ++ return dsi_ctx.accum_err; +} + +static int icna3512_unprepare(struct drm_panel *panel) @@ -324,7 +313,7 @@ index 000000000000..cbda976df1db + struct panel_info *pinfo = to_panel_info(panel); + + gpiod_set_value_cansleep(pinfo->reset_gpio, 1); -+ regulator_bulk_disable(ARRAY_SIZE(pinfo->supplies), pinfo->supplies); ++ regulator_bulk_disable(ARRAY_SIZE(panel_supplies), pinfo->supplies); + + return 0; +} @@ -451,14 +440,11 @@ index 000000000000..cbda976df1db + if (!pinfo) + return -ENOMEM; + -+ pinfo->supplies[0].supply = "blvdd"; -+ pinfo->supplies[1].supply = "iovdd"; -+ pinfo->supplies[2].supply = "vdd"; -+ -+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pinfo->supplies), -+ pinfo->supplies); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "failed to get regulators\n"); ++ ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(panel_supplies), ++ panel_supplies, &pinfo->supplies); ++ if (ret < 0){ ++ return dev_err_probe(dev, ret, "Failed to get regulators\n"); ++ } + + pinfo->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(pinfo->reset_gpio)) @@ -480,24 +466,24 @@ index 000000000000..cbda976df1db + + pinfo->panel.prepare_prev_first = true; + -+ pinfo->panel.backlight = icna3512_create_backlight(dsi); ++ pinfo->panel.backlight = icna3512_create_backlight(dsi); + if (IS_ERR(pinfo->panel.backlight)) + return dev_err_probe(dev, PTR_ERR(pinfo->panel.backlight), + "Failed to create backlight\n"); + + drm_panel_add(&pinfo->panel); + -+ pinfo->dsi->lanes = pinfo->desc->lanes; -+ pinfo->dsi->format = pinfo->desc->format; -+ pinfo->dsi->mode_flags = pinfo->desc->mode_flags; -+ pinfo->dsi->dsc = &pinfo->desc->dsc; ++ pinfo->dsi->lanes = pinfo->desc->lanes; ++ pinfo->dsi->format = pinfo->desc->format; ++ pinfo->dsi->mode_flags = pinfo->desc->mode_flags; ++ pinfo->dsi->dsc = &pinfo->desc->dsc; + -+ ret = mipi_dsi_attach(pinfo->dsi); -+ if (ret < 0){ ++ ret = mipi_dsi_attach(pinfo->dsi); ++ if (ret < 0){ + dev_err_probe(dev, ret, "Failed to attach to DSI host\n"); + drm_panel_remove(&pinfo->panel); -+ return ret; -+ } ++ return ret; ++ } + + return 0; +} diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0055-wifi-ath12k-fix-ring-buffer-corruption.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0055-wifi-ath12k-fix-ring-buffer-corruption.patch deleted file mode 100644 index 33f06d047a..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0055-wifi-ath12k-fix-ring-buffer-corruption.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 39e8716585accb8c07fbaffa078d2e5d47ee3e04 Mon Sep 17 00:00:00 2001 -From: Johan Hovold -Date: Fri, 21 Mar 2025 10:52:19 +0100 -Subject: [PATCH] wifi: ath12k: fix ring-buffer corruption - -Users of the Lenovo ThinkPad X13s have reported that Wi-Fi sometimes -breaks and the log fills up with errors like: - - ath11k_pci 0006:01:00.0: HTC Rx: insufficient length, got 1484, expected 1492 - ath11k_pci 0006:01:00.0: HTC Rx: insufficient length, got 1460, expected 1484 - -which based on a quick look at the ath11k driver seemed to indicate some -kind of ring-buffer corruption. - -Miaoqing Pan tracked it down to the host seeing the updated destination -ring head pointer before the updated descriptor, and the error handling -for that in turn leaves the ring buffer in an inconsistent state. - -While this has not yet been observed with ath12k, the ring-buffer -implementation is very similar to the ath11k one and it suffers from the -same bugs. - -Add the missing memory barrier to make sure that the descriptor is read -after the head pointer to address the root cause of the corruption while -fixing up the error handling in case there are ever any (ordering) bugs -on the device side. - -Note that the READ_ONCE() are only needed to avoid compiler mischief in -case the ring-buffer helpers are ever inlined. - -Tested-on: WCN7850 hw2.0 WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3 - -Fixes: d889913205cf ("wifi: ath12k: driver for Qualcomm Wi-Fi 7 devices") -Cc: stable@vger.kernel.org # 6.3 -Link: https://bugzilla.kernel.org/show_bug.cgi?id=218623 -Link: https://lore.kernel.org/20250310010217.3845141-3-quic_miaoqing@quicinc.com -Cc: Miaoqing Pan -Signed-off-by: Johan Hovold -Signed-off-by: map220v ---- - drivers/net/wireless/ath/ath12k/ce.c | 11 +++++------ - drivers/net/wireless/ath/ath12k/hal.c | 4 ++-- - 2 files changed, 7 insertions(+), 8 deletions(-) - -diff --git a/drivers/net/wireless/ath/ath12k/ce.c b/drivers/net/wireless/ath/ath12k/ce.c -index be0d669d31fc..740586fe49d1 100644 ---- a/drivers/net/wireless/ath/ath12k/ce.c -+++ b/drivers/net/wireless/ath/ath12k/ce.c -@@ -343,11 +343,10 @@ static int ath12k_ce_completed_recv_next(struct ath12k_ce_pipe *pipe, - goto err; - } - -+ /* Make sure descriptor is read after the head pointer. */ -+ dma_rmb(); -+ - *nbytes = ath12k_hal_ce_dst_status_get_length(desc); -- if (*nbytes == 0) { -- ret = -EIO; -- goto err; -- } - - *skb = pipe->dest_ring->skb[sw_index]; - pipe->dest_ring->skb[sw_index] = NULL; -@@ -380,8 +379,8 @@ static void ath12k_ce_recv_process_cb(struct ath12k_ce_pipe *pipe) - dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, - max_nbytes, DMA_FROM_DEVICE); - -- if (unlikely(max_nbytes < nbytes)) { -- ath12k_warn(ab, "rxed more than expected (nbytes %d, max %d)", -+ if (unlikely(max_nbytes < nbytes || nbytes == 0)) { -+ ath12k_warn(ab, "unexpected rx length (nbytes %d, max %d)", - nbytes, max_nbytes); - dev_kfree_skb_any(skb); - continue; -diff --git a/drivers/net/wireless/ath/ath12k/hal.c b/drivers/net/wireless/ath/ath12k/hal.c -index cd59ff8e6c7b..91d5126ca149 100644 ---- a/drivers/net/wireless/ath/ath12k/hal.c -+++ b/drivers/net/wireless/ath/ath12k/hal.c -@@ -1962,7 +1962,7 @@ u32 ath12k_hal_ce_dst_status_get_length(struct hal_ce_srng_dst_status_desc *desc - { - u32 len; - -- len = le32_get_bits(desc->flags, HAL_CE_DST_STATUS_DESC_FLAGS_LEN); -+ len = le32_get_bits(READ_ONCE(desc->flags), HAL_CE_DST_STATUS_DESC_FLAGS_LEN); - desc->flags &= ~cpu_to_le32(HAL_CE_DST_STATUS_DESC_FLAGS_LEN); - - return len; -@@ -2132,7 +2132,7 @@ void ath12k_hal_srng_access_begin(struct ath12k_base *ab, struct hal_srng *srng) - srng->u.src_ring.cached_tp = - *(volatile u32 *)srng->u.src_ring.tp_addr; - else -- srng->u.dst_ring.cached_hp = *srng->u.dst_ring.hp_addr; -+ srng->u.dst_ring.cached_hp = READ_ONCE(*srng->u.dst_ring.hp_addr); - } - - /* Update cached ring head/tail pointers to HW. ath12k_hal_srng_access_begin() - \ No newline at end of file diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0057_devm--regulator--bulk--get--const.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0057_devm--regulator--bulk--get--const.patch deleted file mode 100644 index 66346840a4..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0057_devm--regulator--bulk--get--const.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 67794516240e8d25a5878fc56e37b0a95be62a67 Mon Sep 17 00:00:00 2001 -From: Teguh Sobirin -Date: Fri, 28 Feb 2025 16:12:24 +0800 -Subject: [PATCH] drm/panel/panel-chipone-icna3512: - devm_regulator_bulk_get_const - -Signed-off-by: Teguh Sobirin ---- - .../gpu/drm/panel/panel-chipone-icna3512.c | 29 +++++++++++-------- - 1 file changed, 17 insertions(+), 12 deletions(-) - -diff --git a/drivers/gpu/drm/panel/panel-chipone-icna3512.c b/drivers/gpu/drm/panel/panel-chipone-icna3512.c -index cbda976df1dbca..9fd37f9a17062e 100644 ---- a/drivers/gpu/drm/panel/panel-chipone-icna3512.c -+++ b/drivers/gpu/drm/panel/panel-chipone-icna3512.c -@@ -31,7 +31,7 @@ struct panel_info { - enum drm_panel_orientation orientation; - - struct gpio_desc *reset_gpio; -- struct regulator_bulk_data supplies[3]; -+ struct regulator_bulk_data *supplies; - }; - - struct panel_desc { -@@ -50,6 +50,14 @@ struct panel_desc { - struct drm_dsc_config dsc; - }; - -+static const struct regulator_bulk_data panel_supplies[] = { -+ { .supply = "vdd" }, -+ { .supply = "vddio" }, -+ { .supply = "vci" }, -+ { .supply = "disp" }, -+ { .supply = "blvdd" }, -+}; -+ - static inline struct panel_info *to_panel_info(struct drm_panel *panel) - { - return container_of(panel, struct panel_info, panel); -@@ -213,7 +221,7 @@ static int icna3512_prepare(struct drm_panel *panel) - struct drm_dsc_picture_parameter_set pps; - int ret; - -- ret = regulator_bulk_enable(ARRAY_SIZE(pinfo->supplies), pinfo->supplies); -+ ret = regulator_bulk_enable(ARRAY_SIZE(panel_supplies), pinfo->supplies); - if (ret < 0) { - dev_err(panel->dev, "failed to enable regulators: %d\n", ret); - return ret; -@@ -223,7 +231,7 @@ static int icna3512_prepare(struct drm_panel *panel) - - ret = pinfo->desc->init_sequence(pinfo); - if (ret < 0) { -- regulator_bulk_disable(ARRAY_SIZE(pinfo->supplies), pinfo->supplies); -+ regulator_bulk_disable(ARRAY_SIZE(panel_supplies), pinfo->supplies); - dev_err(panel->dev, "failed to initialize panel: %d\n", ret); - return ret; - } -@@ -271,7 +279,7 @@ static int icna3512_unprepare(struct drm_panel *panel) - struct panel_info *pinfo = to_panel_info(panel); - - gpiod_set_value_cansleep(pinfo->reset_gpio, 1); -- regulator_bulk_disable(ARRAY_SIZE(pinfo->supplies), pinfo->supplies); -+ regulator_bulk_disable(ARRAY_SIZE(panel_supplies), pinfo->supplies); - - return 0; - } -@@ -398,14 +406,11 @@ static int icna3512_probe(struct mipi_dsi_device *dsi) - if (!pinfo) - return -ENOMEM; - -- pinfo->supplies[0].supply = "blvdd"; -- pinfo->supplies[1].supply = "iovdd"; -- pinfo->supplies[2].supply = "vdd"; -- -- ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pinfo->supplies), -- pinfo->supplies); -- if (ret < 0) -- return dev_err_probe(dev, ret, "failed to get regulators\n"); -+ ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(panel_supplies), -+ panel_supplies, &pinfo->supplies); -+ if (ret < 0){ -+ return dev_err_probe(dev, ret, "Failed to get regulators\n"); -+ } - - pinfo->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); - if (IS_ERR(pinfo->reset_gpio)) diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0110_20250115_neil_armstrong_arm64_dts_qcom_sm8_56_50_performance_related_changes.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0110_20250115_neil_armstrong_arm64_dts_qcom_sm8_56_50_performance_related_changes.patch deleted file mode 100644 index f915347499..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0110_20250115_neil_armstrong_arm64_dts_qcom_sm8_56_50_performance_related_changes.patch +++ /dev/null @@ -1,3285 +0,0 @@ -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH 1/10] arm64: dts: qcom: sm8550: use ICC tag for all - interconnect phandles -From: Neil Armstrong -Date: Wed, 15 Jan 2025 14:43:53 +0100 -Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-1-eaa8b10e2af7@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Use the proper QCOM_ICC_TAG_ define instead of passing 0 in all -interconnect paths phandle third argument. - -Use QCOM_ICC_TAG_ALWAYS which is the fallback mask if 0 is used -as third phandle argument. - -Signed-off-by: Neil Armstrong -Acked-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/sm8550.dtsi | 387 +++++++++++++++++++++++------------ - 1 file changed, 258 insertions(+), 129 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi -index eac8de4005d82f246bc50f64f09515631d895c99..cc754684bf05b99d39e3987312a200b479e8de2c 100644 ---- a/arch/arm64/boot/dts/qcom/sm8550.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi -@@ -331,7 +331,8 @@ firmware { - scm: scm { - compatible = "qcom,scm-sm8550", "qcom,scm"; - qcom,dload-mode = <&tcsr 0x19000>; -- interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - }; - }; - -@@ -850,9 +851,12 @@ i2c8: i2c@880000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, - <&gpi_dma2 1 0 QCOM_GPI_I2C>; -@@ -868,9 +872,12 @@ spi8: spi@880000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, - <&gpi_dma2 1 0 QCOM_GPI_SPI>; -@@ -890,9 +897,12 @@ i2c9: i2c@884000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, - <&gpi_dma2 1 1 QCOM_GPI_I2C>; -@@ -908,9 +918,12 @@ spi9: spi@884000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, - <&gpi_dma2 1 1 QCOM_GPI_SPI>; -@@ -930,9 +943,12 @@ i2c10: i2c@888000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, - <&gpi_dma2 1 2 QCOM_GPI_I2C>; -@@ -948,9 +964,12 @@ spi10: spi@888000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, - <&gpi_dma2 1 2 QCOM_GPI_SPI>; -@@ -970,9 +989,12 @@ i2c11: i2c@88c000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, - <&gpi_dma2 1 3 QCOM_GPI_I2C>; -@@ -988,9 +1010,12 @@ spi11: spi@88c000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, - <&gpi_dma2 1 3 QCOM_GPI_I2C>; -@@ -1010,9 +1035,12 @@ i2c12: i2c@890000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, - <&gpi_dma2 1 4 QCOM_GPI_I2C>; -@@ -1028,9 +1056,12 @@ spi12: spi@890000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, - <&gpi_dma2 1 4 QCOM_GPI_I2C>; -@@ -1050,9 +1081,12 @@ i2c13: i2c@894000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, - <&gpi_dma2 1 5 QCOM_GPI_I2C>; -@@ -1068,9 +1102,12 @@ spi13: spi@894000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, - <&gpi_dma2 1 5 QCOM_GPI_SPI>; -@@ -1088,8 +1125,10 @@ uart14: serial@898000 { - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; - interrupts = ; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1104,9 +1143,12 @@ i2c15: i2c@89c000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, - <&gpi_dma2 1 7 QCOM_GPI_I2C>; -@@ -1122,9 +1164,12 @@ spi15: spi@89c000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, -- <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, - <&gpi_dma2 1 7 QCOM_GPI_SPI>; -@@ -1156,8 +1201,10 @@ i2c_hub_0: i2c@980000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1173,8 +1220,10 @@ i2c_hub_1: i2c@984000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1190,8 +1239,10 @@ i2c_hub_2: i2c@988000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1207,8 +1258,10 @@ i2c_hub_3: i2c@98c000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1224,8 +1277,10 @@ i2c_hub_4: i2c@990000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1241,8 +1296,10 @@ i2c_hub_5: i2c@994000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1258,8 +1315,10 @@ i2c_hub_6: i2c@998000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1275,8 +1334,10 @@ i2c_hub_7: i2c@99c000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1292,8 +1353,10 @@ i2c_hub_8: i2c@9a0000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1309,8 +1372,10 @@ i2c_hub_9: i2c@9a4000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1347,7 +1412,8 @@ qupv3_id_0: geniqup@ac0000 { - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - iommus = <&apps_smmu 0xa3 0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core"; - dma-coherent; - #address-cells = <2>; -@@ -1364,9 +1430,12 @@ i2c0: i2c@a80000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, - <&gpi_dma1 1 0 QCOM_GPI_I2C>; -@@ -1382,9 +1451,12 @@ spi0: spi@a80000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, - <&gpi_dma1 1 0 QCOM_GPI_SPI>; -@@ -1404,9 +1476,12 @@ i2c1: i2c@a84000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, - <&gpi_dma1 1 1 QCOM_GPI_I2C>; -@@ -1422,9 +1497,12 @@ spi1: spi@a84000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, - <&gpi_dma1 1 1 QCOM_GPI_SPI>; -@@ -1444,9 +1522,12 @@ i2c2: i2c@a88000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, - <&gpi_dma1 1 2 QCOM_GPI_I2C>; -@@ -1462,9 +1543,12 @@ spi2: spi@a88000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, - <&gpi_dma1 1 2 QCOM_GPI_SPI>; -@@ -1484,9 +1568,12 @@ i2c3: i2c@a8c000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, - <&gpi_dma1 1 3 QCOM_GPI_I2C>; -@@ -1502,9 +1589,12 @@ spi3: spi@a8c000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, - <&gpi_dma1 1 3 QCOM_GPI_SPI>; -@@ -1524,9 +1614,12 @@ i2c4: i2c@a90000 { - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, - <&gpi_dma1 1 4 QCOM_GPI_I2C>; -@@ -1542,9 +1635,12 @@ spi4: spi@a90000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, - <&gpi_dma1 1 4 QCOM_GPI_SPI>; -@@ -1562,9 +1658,12 @@ i2c5: i2c@a94000 { - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_data_clk>; - interrupts = ; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, - <&gpi_dma1 1 5 QCOM_GPI_I2C>; -@@ -1582,9 +1681,12 @@ spi5: spi@a94000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, - <&gpi_dma1 1 5 QCOM_GPI_SPI>; -@@ -1602,9 +1704,12 @@ i2c6: i2c@a98000 { - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_data_clk>; - interrupts = ; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, - <&gpi_dma1 1 6 QCOM_GPI_I2C>; -@@ -1622,9 +1727,12 @@ spi6: spi@a98000 { - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, -- <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, - <&gpi_dma1 1 6 QCOM_GPI_SPI>; -@@ -1643,8 +1751,10 @@ uart7: serial@a9c000 { - pinctrl-0 = <&qup_uart7_default>; - interrupts = ; - interconnect-names = "qup-core", "qup-config"; -- interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; -+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS -+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; - status = "disabled"; - }; - }; -@@ -1768,8 +1878,10 @@ pcie0: pcie@1c00000 { - "ddrss_sf_tbu", - "noc_aggr"; - -- interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; -+ interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - msi-map = <0x0 &gic_its 0x1400 0x1>, -@@ -1891,8 +2003,10 @@ pcie1: pcie@1c08000 { - assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; - assigned-clock-rates = <19200000>; - -- interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; -+ interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - msi-map = <0x0 &gic_its 0x1480 0x1>, -@@ -1969,7 +2083,8 @@ crypto: crypto@1dfa000 { - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x480 0x0>, - <&apps_smmu 0x481 0x0>; -- interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "memory"; - }; - -@@ -2013,8 +2128,10 @@ ufs_mem_hc: ufshc@1d84000 { - dma-coherent; - - operating-points-v2 = <&ufs_opp_table>; -- interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; -+ interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; - - interconnect-names = "ufs-ddr", "cpu-ufs"; - clock-names = "core_clk", -@@ -2314,8 +2431,10 @@ ipa: ipa@3f40000 { - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - -- interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; -+ interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "memory", - "config"; - -@@ -2349,7 +2468,8 @@ remoteproc_mpss: remoteproc@4080000 { - <&rpmhpd RPMHPD_MSS>; - power-domain-names = "cx", "mss"; - -- interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - - memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; - -@@ -2390,7 +2510,8 @@ remoteproc_adsp: remoteproc@6800000 { - <&rpmhpd RPMHPD_LMX>; - power-domain-names = "lcx", "lmx"; - -- interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - - memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; - -@@ -2848,8 +2969,10 @@ sdhc_2: mmc@8804000 { - power-domains = <&rpmhpd RPMHPD_CX>; - operating-points-v2 = <&sdhc2_opp_table>; - -- interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; -+ interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "sdhc-ddr", "cpu-sdhc"; - bus-width = <4>; - dma-coherent; -@@ -3020,7 +3143,8 @@ mdss: display-subsystem@ae00000 { - - power-domains = <&dispcc MDSS_GDSC>; - -- interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "mdp0-mem"; - - iommus = <&apps_smmu 0x1c00 0x2>; -@@ -3493,8 +3617,10 @@ usb_1: usb@a6f8800 { - - resets = <&gcc GCC_USB30_PRIM_BCR>; - -- interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; -+ interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "usb-ddr", "apps-usb"; - - status = "disabled"; -@@ -4617,7 +4743,8 @@ pmu@24091000 { - compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; - reg = <0 0x24091000 0 0x1000>; - interrupts = ; -- interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; -+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; - - operating-points-v2 = <&llcc_bwmon_opp_table>; - -@@ -4666,7 +4793,8 @@ pmu@240b6400 { - compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; - reg = <0 0x240b6400 0 0x600>; - interrupts = ; -- interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; -+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; - - operating-points-v2 = <&cpu_bwmon_opp_table>; - -@@ -4750,7 +4878,8 @@ remoteproc_cdsp: remoteproc@32300000 { - <&rpmhpd RPMHPD_NSP>; - power-domain-names = "cx", "mxc", "nsp"; - -- interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; -+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - - memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; - --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH 2/10] arm64: dts: qcom: sm8550: set CPU interconnect paths - as ACTIVE_ONLY -From: Neil Armstrong -Date: Wed, 15 Jan 2025 14:43:54 +0100 -Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-2-eaa8b10e2af7@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -In all interconnect paths involving the cpu (MASTER_APPSS_PROC), use -the QCOM_ICC_TAG_ACTIVE_ONLY which will only retain the vote if -the CPU is online, leaving the firmware disabling the path when the -CPUs goes in suspend-idle. - -Signed-off-by: Neil Armstrong -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/sm8550.dtsi | 184 +++++++++++++++++------------------ - 1 file changed, 92 insertions(+), 92 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi -index cc754684bf05b99d39e3987312a200b479e8de2c..a04a405a3f78f34fddf14a26a6996148cf60c85f 100644 ---- a/arch/arm64/boot/dts/qcom/sm8550.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi -@@ -853,8 +853,8 @@ i2c8: i2c@880000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -874,8 +874,8 @@ spi8: spi@880000 { - pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -899,8 +899,8 @@ i2c9: i2c@884000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -920,8 +920,8 @@ spi9: spi@884000 { - pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -945,8 +945,8 @@ i2c10: i2c@888000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -966,8 +966,8 @@ spi10: spi@888000 { - pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -991,8 +991,8 @@ i2c11: i2c@88c000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1012,8 +1012,8 @@ spi11: spi@88c000 { - pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1037,8 +1037,8 @@ i2c12: i2c@890000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1058,8 +1058,8 @@ spi12: spi@890000 { - pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1083,8 +1083,8 @@ i2c13: i2c@894000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1104,8 +1104,8 @@ spi13: spi@894000 { - pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1127,8 +1127,8 @@ uart14: serial@898000 { - interrupts = ; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1145,8 +1145,8 @@ i2c15: i2c@89c000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1166,8 +1166,8 @@ spi15: spi@89c000 { - pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1203,8 +1203,8 @@ i2c_hub_0: i2c@980000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1222,8 +1222,8 @@ i2c_hub_1: i2c@984000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1241,8 +1241,8 @@ i2c_hub_2: i2c@988000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1260,8 +1260,8 @@ i2c_hub_3: i2c@98c000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1279,8 +1279,8 @@ i2c_hub_4: i2c@990000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1298,8 +1298,8 @@ i2c_hub_5: i2c@994000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1317,8 +1317,8 @@ i2c_hub_6: i2c@998000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1336,8 +1336,8 @@ i2c_hub_7: i2c@99c000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1355,8 +1355,8 @@ i2c_hub_8: i2c@9a0000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1374,8 +1374,8 @@ i2c_hub_9: i2c@9a4000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; -@@ -1432,8 +1432,8 @@ i2c0: i2c@a80000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1453,8 +1453,8 @@ spi0: spi@a80000 { - pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1478,8 +1478,8 @@ i2c1: i2c@a84000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1499,8 +1499,8 @@ spi1: spi@a84000 { - pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1524,8 +1524,8 @@ i2c2: i2c@a88000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1545,8 +1545,8 @@ spi2: spi@a88000 { - pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1570,8 +1570,8 @@ i2c3: i2c@a8c000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1591,8 +1591,8 @@ spi3: spi@a8c000 { - pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1616,8 +1616,8 @@ i2c4: i2c@a90000 { - #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1637,8 +1637,8 @@ spi4: spi@a90000 { - pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1660,8 +1660,8 @@ i2c5: i2c@a94000 { - interrupts = ; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1683,8 +1683,8 @@ spi5: spi@a94000 { - pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1706,8 +1706,8 @@ i2c6: i2c@a98000 { - interrupts = ; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1729,8 +1729,8 @@ spi6: spi@a98000 { - pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config", "qup-memory"; -@@ -1753,8 +1753,8 @@ uart7: serial@a9c000 { - interconnect-names = "qup-core", "qup-config"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; - status = "disabled"; - }; - }; -@@ -1880,8 +1880,8 @@ pcie0: pcie@1c00000 { - - interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - msi-map = <0x0 &gic_its 0x1400 0x1>, -@@ -2005,8 +2005,8 @@ pcie1: pcie@1c08000 { - - interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "pcie-mem", "cpu-pcie"; - - msi-map = <0x0 &gic_its 0x1480 0x1>, -@@ -2130,8 +2130,8 @@ ufs_mem_hc: ufshc@1d84000 { - operating-points-v2 = <&ufs_opp_table>; - interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; - - interconnect-names = "ufs-ddr", "cpu-ufs"; - clock-names = "core_clk", -@@ -2433,8 +2433,8 @@ ipa: ipa@3f40000 { - - interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "memory", - "config"; - -@@ -2971,8 +2971,8 @@ sdhc_2: mmc@8804000 { - - interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "sdhc-ddr", "cpu-sdhc"; - bus-width = <4>; - dma-coherent; -@@ -3619,8 +3619,8 @@ usb_1: usb@a6f8800 { - - interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "usb-ddr", "apps-usb"; - - status = "disabled"; --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH 3/10] arm64: dts: qcom: sm8550: add OPP table support to - PCIe -From: Neil Armstrong -Date: Wed, 15 Jan 2025 14:43:55 +0100 -Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-3-eaa8b10e2af7@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -The PCIe bus interconnect path can be scaled depending on the -PCIe link established, add the OPP table with all the possible -link speeds and the associated power domain level. - -Signed-off-by: Neil Armstrong -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/sm8550.dtsi | 89 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 89 insertions(+) - -diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi -index a04a405a3f78f34fddf14a26a6996148cf60c85f..4b3c51fad9f19a1ec1e5d563a18fec9633a4e4ae 100644 ---- a/arch/arm64/boot/dts/qcom/sm8550.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi -@@ -1897,8 +1897,49 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - phys = <&pcie0_phy>; - phy-names = "pciephy"; - -+ operating-points-v2 = <&pcie0_opp_table>; -+ - status = "disabled"; - -+ pcie0_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ /* GEN 1 x1 */ -+ opp-2500000 { -+ opp-hz = /bits/ 64 <2500000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <250000 1>; -+ }; -+ -+ /* GEN 1 x2 and GEN 2 x1 */ -+ opp-5000000 { -+ opp-hz = /bits/ 64 <5000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <500000 1>; -+ }; -+ -+ /* GEN 2 x2 */ -+ opp-10000000 { -+ opp-hz = /bits/ 64 <10000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <1000000 1>; -+ }; -+ -+ /* GEN 3 x1 */ -+ opp-8000000 { -+ opp-hz = /bits/ 64 <8000000>; -+ required-opps = <&rpmhpd_opp_nom>; -+ opp-peak-kBps = <984500 1>; -+ }; -+ -+ /* GEN 3 x2 */ -+ opp-16000000 { -+ opp-hz = /bits/ 64 <16000000>; -+ required-opps = <&rpmhpd_opp_nom>; -+ opp-peak-kBps = <1969000 1>; -+ }; -+ }; -+ - pcieport0: pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; -@@ -2023,8 +2064,56 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - phys = <&pcie1_phy>; - phy-names = "pciephy"; - -+ operating-points-v2 = <&pcie1_opp_table>; -+ - status = "disabled"; - -+ pcie1_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ /* GEN 1 x1 */ -+ opp-2500000 { -+ opp-hz = /bits/ 64 <2500000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <250000 1>; -+ }; -+ -+ /* GEN 1 x2 and GEN 2 x1 */ -+ opp-5000000 { -+ opp-hz = /bits/ 64 <5000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <500000 1>; -+ }; -+ -+ /* GEN 2 x2 */ -+ opp-10000000 { -+ opp-hz = /bits/ 64 <10000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <1000000 1>; -+ }; -+ -+ /* GEN 3 x1 */ -+ opp-8000000 { -+ opp-hz = /bits/ 64 <8000000>; -+ required-opps = <&rpmhpd_opp_nom>; -+ opp-peak-kBps = <984500 1>; -+ }; -+ -+ /* GEN 3 x2 and GEN 4 x1 */ -+ opp-16000000 { -+ opp-hz = /bits/ 64 <16000000>; -+ required-opps = <&rpmhpd_opp_nom>; -+ opp-peak-kBps = <1969000 1>; -+ }; -+ -+ /* GEN 4 x2 */ -+ opp-32000000 { -+ opp-hz = /bits/ 64 <32000000>; -+ required-opps = <&rpmhpd_opp_nom>; -+ opp-peak-kBps = <3938000 1>; -+ }; -+ }; -+ - pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH 4/10] arm64: dts: qcom: sm8550: add QUP serial engines OPP - tables -From: Neil Armstrong -Date: Wed, 15 Jan 2025 14:43:56 +0100 -Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-4-eaa8b10e2af7@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -The QUP Serial Engines requires different power domain level -depending on their working frequency, add the required OPP -table with the level associated with all possible frequencies. - -For the "I2C Hub" serial engines, sinse they only support a -single Operating Point, only add a single power domain level -property. - -Signed-off-by: Neil Armstrong ---- - arch/arm64/boot/dts/qcom/sm8550.dtsi | 122 +++++++++++++++++++++++++++++++++++ - 1 file changed, 122 insertions(+) - -diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi -index 4b3c51fad9f19a1ec1e5d563a18fec9633a4e4ae..d02d80d731b9a8746655af6da236307760a8f662 100644 ---- a/arch/arm64/boot/dts/qcom/sm8550.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi -@@ -348,6 +348,48 @@ mc_virt: interconnect-1 { - qcom,bcm-voters = <&apps_bcm_voter>; - }; - -+ qup_opp_table_100mhz: opp-table-qup100mhz { -+ compatible = "operating-points-v2"; -+ -+ opp-75000000 { -+ opp-hz = /bits/ 64 <75000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ }; -+ -+ opp-100000000 { -+ opp-hz = /bits/ 64 <100000000>; -+ required-opps = <&rpmhpd_opp_svs>; -+ }; -+ }; -+ -+ qup_opp_table_120mhz: opp-table-qup120mhz { -+ compatible = "operating-points-v2"; -+ -+ opp-75000000 { -+ opp-hz = /bits/ 64 <75000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ }; -+ -+ opp-120000000 { -+ opp-hz = /bits/ 64 <120000000>; -+ required-opps = <&rpmhpd_opp_svs>; -+ }; -+ }; -+ -+ qup_opp_table_125mhz: opp-table-qup125mhz { -+ compatible = "operating-points-v2"; -+ -+ opp-75000000 { -+ opp-hz = /bits/ 64 <75000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ }; -+ -+ opp-125000000 { -+ opp-hz = /bits/ 64 <125000000>; -+ required-opps = <&rpmhpd_opp_svs>; -+ }; -+ }; -+ - memory@a0000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ -@@ -861,6 +903,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, - <&gpi_dma2 1 0 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - status = "disabled"; - }; - -@@ -882,6 +926,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, - <&gpi_dma2 1 0 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -907,6 +953,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, - <&gpi_dma2 1 1 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - status = "disabled"; - }; - -@@ -928,6 +976,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, - <&gpi_dma2 1 1 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -953,6 +1003,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, - <&gpi_dma2 1 2 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - status = "disabled"; - }; - -@@ -974,6 +1026,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, - <&gpi_dma2 1 2 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -999,6 +1053,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, - <&gpi_dma2 1 3 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - status = "disabled"; - }; - -@@ -1020,6 +1076,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, - <&gpi_dma2 1 3 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1045,6 +1103,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, - <&gpi_dma2 1 4 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - status = "disabled"; - }; - -@@ -1066,6 +1126,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, - <&gpi_dma2 1 4 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1091,6 +1153,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, - <&gpi_dma2 1 5 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - status = "disabled"; - }; - -@@ -1112,6 +1176,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, - <&gpi_dma2 1 5 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1130,6 +1196,8 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_125mhz>; - status = "disabled"; - }; - -@@ -1153,6 +1221,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, - <&gpi_dma2 1 7 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - status = "disabled"; - }; - -@@ -1174,6 +1244,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, - <&gpi_dma2 1 7 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1206,6 +1278,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ required-opps = <&rpmhpd_opp_low_svs>; - status = "disabled"; - }; - -@@ -1225,6 +1299,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ required-opps = <&rpmhpd_opp_low_svs>; - status = "disabled"; - }; - -@@ -1244,6 +1320,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ required-opps = <&rpmhpd_opp_low_svs>; - status = "disabled"; - }; - -@@ -1263,6 +1341,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ required-opps = <&rpmhpd_opp_low_svs>; - status = "disabled"; - }; - -@@ -1282,6 +1362,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ required-opps = <&rpmhpd_opp_low_svs>; - status = "disabled"; - }; - -@@ -1301,6 +1383,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ required-opps = <&rpmhpd_opp_low_svs>; - status = "disabled"; - }; - -@@ -1320,6 +1404,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ required-opps = <&rpmhpd_opp_low_svs>; - status = "disabled"; - }; - -@@ -1339,6 +1425,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ required-opps = <&rpmhpd_opp_low_svs>; - status = "disabled"; - }; - -@@ -1358,6 +1446,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ required-opps = <&rpmhpd_opp_low_svs>; - status = "disabled"; - }; - -@@ -1377,6 +1467,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", "qup-config"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ required-opps = <&rpmhpd_opp_low_svs>; - status = "disabled"; - }; - }; -@@ -1440,6 +1532,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, - <&gpi_dma1 1 0 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - status = "disabled"; - }; - -@@ -1461,6 +1555,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, - <&gpi_dma1 1 0 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1486,6 +1582,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, - <&gpi_dma1 1 1 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - status = "disabled"; - }; - -@@ -1507,6 +1605,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, - <&gpi_dma1 1 1 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_120mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1532,6 +1632,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, - <&gpi_dma1 1 2 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - status = "disabled"; - }; - -@@ -1553,6 +1655,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, - <&gpi_dma1 1 2 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1578,6 +1682,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, - <&gpi_dma1 1 3 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - status = "disabled"; - }; - -@@ -1599,6 +1705,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, - <&gpi_dma1 1 3 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1624,6 +1732,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, - <&gpi_dma1 1 4 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - status = "disabled"; - }; - -@@ -1645,6 +1755,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, - <&gpi_dma1 1 4 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1668,6 +1780,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, - <&gpi_dma1 1 5 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1691,6 +1805,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, - <&gpi_dma1 1 5 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1714,6 +1830,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, - <&gpi_dma1 1 6 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1737,6 +1855,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, - <&gpi_dma1 1 6 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -1755,6 +1875,8 @@ uart7: serial@a9c000 { - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ operating-points-v2 = <&qup_opp_table_100mhz>; - status = "disabled"; - }; - }; --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH 5/10] arm64: dts: qcom: sm8650: use ICC tag for IPA - interconnect phandles -From: Neil Armstrong -Date: Wed, 15 Jan 2025 14:43:57 +0100 -Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-5-eaa8b10e2af7@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Use the proper QCOM_ICC_TAG_ define instead of passing 0 in the IPA -interconnect paths phandle third argument - -Signed-off-by: Neil Armstrong -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi -index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..0658982a748ef4d9df0fe12ecc68c4c23e3c2566 100644 ---- a/arch/arm64/boot/dts/qcom/sm8650.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi -@@ -2889,8 +2889,10 @@ ipa: ipa@3f40000 { - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - -- interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, -- <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; -+ interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "memory", - "config"; - --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH 6/10] arm64: dts: qcom: sm8650: set CPU interconnect paths - as ACTIVE_ONLY -From: Neil Armstrong -Date: Wed, 15 Jan 2025 14:43:58 +0100 -Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-6-eaa8b10e2af7@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -In all interconnect paths involving the cpu (MASTER_APPSS_PROC), use -the QCOM_ICC_TAG_ACTIVE_ONLY which will only retain the vote if -the CPU is online, leaving the firmware disabling the path when the -CPUs goes in suspend-idle. - -Signed-off-by: Neil Armstrong -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/sm8650.dtsi | 180 +++++++++++++++++------------------ - 1 file changed, 90 insertions(+), 90 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi -index 0658982a748ef4d9df0fe12ecc68c4c23e3c2566..a72087d5255899fba03ac90a3f0241ee3905504e 100644 ---- a/arch/arm64/boot/dts/qcom/sm8650.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi -@@ -881,8 +881,8 @@ i2c8: i2c@880000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -914,8 +914,8 @@ spi8: spi@880000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -947,8 +947,8 @@ i2c9: i2c@884000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -980,8 +980,8 @@ spi9: spi@884000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1013,8 +1013,8 @@ i2c10: i2c@888000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1046,8 +1046,8 @@ spi10: spi@888000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1079,8 +1079,8 @@ i2c11: i2c@88c000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1112,8 +1112,8 @@ spi11: spi@88c000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1145,8 +1145,8 @@ i2c12: i2c@890000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1178,8 +1178,8 @@ spi12: spi@890000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1211,8 +1211,8 @@ i2c13: i2c@894000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1244,8 +1244,8 @@ spi13: spi@894000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1277,8 +1277,8 @@ uart14: serial@898000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1299,8 +1299,8 @@ uart15: serial@89c000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1337,8 +1337,8 @@ i2c_hub_0: i2c@980000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1364,8 +1364,8 @@ i2c_hub_1: i2c@984000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1391,8 +1391,8 @@ i2c_hub_2: i2c@988000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1418,8 +1418,8 @@ i2c_hub_3: i2c@98c000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1445,8 +1445,8 @@ i2c_hub_4: i2c@990000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1472,8 +1472,8 @@ i2c_hub_5: i2c@994000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1499,8 +1499,8 @@ i2c_hub_6: i2c@998000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1526,8 +1526,8 @@ i2c_hub_7: i2c@99c000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1553,8 +1553,8 @@ i2c_hub_8: i2c@9a0000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1580,8 +1580,8 @@ i2c_hub_9: i2c@9a4000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "qup-core", - "qup-config"; - -@@ -1656,8 +1656,8 @@ i2c0: i2c@a80000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1689,8 +1689,8 @@ spi0: spi@a80000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1722,8 +1722,8 @@ i2c1: i2c@a84000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1755,8 +1755,8 @@ spi1: spi@a84000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1788,8 +1788,8 @@ i2c2: i2c@a88000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1821,8 +1821,8 @@ spi2: spi@a88000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1854,8 +1854,8 @@ i2c3: i2c@a8c000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1887,8 +1887,8 @@ spi3: spi@a8c000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1920,8 +1920,8 @@ i2c4: i2c@a90000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1953,8 +1953,8 @@ spi4: spi@a90000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -1986,8 +1986,8 @@ i2c5: i2c@a94000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -2019,8 +2019,8 @@ spi5: spi@a94000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -2052,8 +2052,8 @@ i2c6: i2c@a98000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -2085,8 +2085,8 @@ spi6: spi@a98000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -2118,8 +2118,8 @@ i2c7: i2c@a9c000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -2151,8 +2151,8 @@ spi7: spi@a9c000 { - - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", -@@ -2301,8 +2301,8 @@ pcie0: pcie@1c00000 { - - interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "pcie-mem", - "cpu-pcie"; - -@@ -2440,8 +2440,8 @@ pcie1: pcie@1c08000 { - - interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "pcie-mem", - "cpu-pcie"; - -@@ -2609,8 +2609,8 @@ ufs_mem_hc: ufshc@1d84000 { - - interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "ufs-ddr", - "cpu-ufs"; - -@@ -2891,8 +2891,8 @@ ipa: ipa@3f40000 { - - interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "memory", - "config"; - -@@ -3474,8 +3474,8 @@ sdhc_2: mmc@8804000 { - - interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -- &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "sdhc-ddr", - "cpu-sdhc"; - --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH 7/10] arm64: dts: qcom: sm8650: add USB interconnect paths -From: Neil Armstrong -Date: Wed, 15 Jan 2025 14:43:59 +0100 -Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-7-eaa8b10e2af7@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Add the interconnect paths for the USB controller. - -Signed-off-by: Neil Armstrong -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi -index a72087d5255899fba03ac90a3f0241ee3905504e..5982fd4d66d903d638f0eeaaac221f3007abf68b 100644 ---- a/arch/arm64/boot/dts/qcom/sm8650.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi -@@ -4148,6 +4148,13 @@ usb_1: usb@a6f8800 { - - resets = <&gcc GCC_USB30_PRIM_BCR>; - -+ interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; -+ interconnect-names = "usb-ddr", -+ "apps-usb"; -+ - power-domains = <&gcc USB30_PRIM_GDSC>; - required-opps = <&rpmhpd_opp_nom>; - --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH 8/10] arm64: dts: qcom: sm8650: add OPP table support to - PCIe -From: Neil Armstrong -Date: Wed, 15 Jan 2025 14:44:00 +0100 -Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-8-eaa8b10e2af7@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -The PCIe bus interconnect path can be scaled depending on the -PCIe link established, add the OPP table with all the possible -link speeds and the associated power domain level. - -Signed-off-by: Neil Armstrong -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/sm8650.dtsi | 89 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 89 insertions(+) - -diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi -index 5982fd4d66d903d638f0eeaaac221f3007abf68b..737d1901ca10fe0a49ae4685d0363be74cc0668d 100644 ---- a/arch/arm64/boot/dts/qcom/sm8650.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi -@@ -2308,6 +2308,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - - power-domains = <&gcc PCIE_0_GDSC>; - -+ operating-points-v2 = <&pcie0_opp_table>; -+ - iommu-map = <0 &apps_smmu 0x1400 0x1>, - <0x100 &apps_smmu 0x1401 0x1>; - -@@ -2338,6 +2340,45 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - - status = "disabled"; - -+ pcie0_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ /* GEN 1 x1 */ -+ opp-2500000 { -+ opp-hz = /bits/ 64 <2500000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <250000 1>; -+ }; -+ -+ /* GEN 1 x2 and GEN 2 x1 */ -+ opp-5000000 { -+ opp-hz = /bits/ 64 <5000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <500000 1>; -+ }; -+ -+ /* GEN 2 x2 */ -+ opp-10000000 { -+ opp-hz = /bits/ 64 <10000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <1000000 1>; -+ }; -+ -+ /* GEN 3 x1 */ -+ opp-8000000 { -+ opp-hz = /bits/ 64 <8000000>; -+ required-opps = <&rpmhpd_opp_nom>; -+ opp-peak-kBps = <984500 1>; -+ }; -+ -+ /* GEN 3 x2 */ -+ opp-16000000 { -+ opp-hz = /bits/ 64 <16000000>; -+ required-opps = <&rpmhpd_opp_nom>; -+ opp-peak-kBps = <1969000 1>; -+ }; -+ }; -+ - pcieport0: pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; -@@ -2447,6 +2488,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - - power-domains = <&gcc PCIE_1_GDSC>; - -+ operating-points-v2 = <&pcie1_opp_table>; -+ - iommu-map = <0 &apps_smmu 0x1480 0x1>, - <0x100 &apps_smmu 0x1481 0x1>; - -@@ -2477,6 +2520,52 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - - status = "disabled"; - -+ pcie1_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ /* GEN 1 x1 */ -+ opp-2500000 { -+ opp-hz = /bits/ 64 <2500000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <250000 1>; -+ }; -+ -+ /* GEN 1 x2 and GEN 2 x1 */ -+ opp-5000000 { -+ opp-hz = /bits/ 64 <5000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <500000 1>; -+ }; -+ -+ /* GEN 2 x2 */ -+ opp-10000000 { -+ opp-hz = /bits/ 64 <10000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <1000000 1>; -+ }; -+ -+ /* GEN 3 x1 */ -+ opp-8000000 { -+ opp-hz = /bits/ 64 <8000000>; -+ required-opps = <&rpmhpd_opp_nom>; -+ opp-peak-kBps = <984500 1>; -+ }; -+ -+ /* GEN 3 x2 and GEN 4 x1 */ -+ opp-16000000 { -+ opp-hz = /bits/ 64 <16000000>; -+ required-opps = <&rpmhpd_opp_nom>; -+ opp-peak-kBps = <1969000 1>; -+ }; -+ -+ /* GEN 4 x2 */ -+ opp-32000000 { -+ opp-hz = /bits/ 64 <32000000>; -+ required-opps = <&rpmhpd_opp_nom>; -+ opp-peak-kBps = <3938000 1>; -+ }; -+ }; -+ - pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH 9/10] arm64: dts: qcom: sm8650: add QUP serial engines OPP - tables -From: Neil Armstrong -Date: Wed, 15 Jan 2025 14:44:01 +0100 -Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-9-eaa8b10e2af7@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -The QUP Serial Engines requires different power domain level -depending on their working frequency, add the required OPP -table with the level associated with all possible frequencies. - -For the "I2C Hub" serial engines, sinse they only support a -single Operating Point, only add a single power domain level -property. - -Signed-off-by: Neil Armstrong ---- - arch/arm64/boot/dts/qcom/sm8650.dtsi | 216 +++++++++++++++++++++++++++++++++++ - 1 file changed, 216 insertions(+) - -diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi -index 737d1901ca10fe0a49ae4685d0363be74cc0668d..82be3f9051705507767023d7e195489852223ce3 100644 ---- a/arch/arm64/boot/dts/qcom/sm8650.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi -@@ -420,6 +420,62 @@ mc_virt: interconnect-1 { - qcom,bcm-voters = <&apps_bcm_voter>; - }; - -+ qup_opp_table_100mhz: opp-table-qup100mhz { -+ compatible = "operating-points-v2"; -+ -+ opp-75000000 { -+ opp-hz = /bits/ 64 <75000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ }; -+ -+ opp-100000000 { -+ opp-hz = /bits/ 64 <100000000>; -+ required-opps = <&rpmhpd_opp_svs>; -+ }; -+ }; -+ -+ qup_opp_table_120mhz: opp-table-qup120mhz { -+ compatible = "operating-points-v2"; -+ -+ opp-75000000 { -+ opp-hz = /bits/ 64 <75000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ }; -+ -+ opp-120000000 { -+ opp-hz = /bits/ 64 <120000000>; -+ required-opps = <&rpmhpd_opp_svs>; -+ }; -+ }; -+ -+ qup_opp_table_128mhz: opp-table-qup128mhz { -+ compatible = "operating-points-v2"; -+ -+ opp-75000000 { -+ opp-hz = /bits/ 64 <75000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ }; -+ -+ opp-128000000 { -+ opp-hz = /bits/ 64 <128000000>; -+ required-opps = <&rpmhpd_opp_svs>; -+ }; -+ }; -+ -+ qup_opp_table_240mhz: opp-table-qup240mhz { -+ compatible = "operating-points-v2"; -+ -+ opp-150000000 { -+ opp-hz = /bits/ 64 <150000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ }; -+ -+ opp-240000000 { -+ opp-hz = /bits/ 64 <240000000>; -+ required-opps = <&rpmhpd_opp_svs>; -+ }; -+ }; -+ - memory@a0000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ -@@ -889,6 +945,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, - <&gpi_dma2 1 0 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -922,6 +982,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, - <&gpi_dma2 1 0 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -955,6 +1019,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, - <&gpi_dma2 1 1 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -988,6 +1056,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, - <&gpi_dma2 1 1 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -1021,6 +1093,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, - <&gpi_dma2 1 2 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -1054,6 +1130,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, - <&gpi_dma2 1 2 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -1087,6 +1167,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, - <&gpi_dma2 1 3 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -1120,6 +1204,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, - <&gpi_dma2 1 3 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -1153,6 +1241,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, - <&gpi_dma2 1 4 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -1186,6 +1278,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, - <&gpi_dma2 1 4 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -1219,6 +1315,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, - <&gpi_dma2 1 5 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -1252,6 +1352,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, - <&gpi_dma2 1 5 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -1282,6 +1386,10 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_128mhz>; -+ - pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; - pinctrl-names = "default"; - -@@ -1304,6 +1412,10 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - pinctrl-0 = <&qup_uart15_default>; - pinctrl-names = "default"; - -@@ -1342,6 +1454,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ required-opps = <&rpmhpd_opp_low_svs>; -+ - pinctrl-0 = <&hub_i2c0_data_clk>; - pinctrl-names = "default"; - -@@ -1369,6 +1485,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ required-opps = <&rpmhpd_opp_low_svs>; -+ - pinctrl-0 = <&hub_i2c1_data_clk>; - pinctrl-names = "default"; - -@@ -1396,6 +1516,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ required-opps = <&rpmhpd_opp_low_svs>; -+ - pinctrl-0 = <&hub_i2c2_data_clk>; - pinctrl-names = "default"; - -@@ -1423,6 +1547,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ required-opps = <&rpmhpd_opp_low_svs>; -+ - pinctrl-0 = <&hub_i2c3_data_clk>; - pinctrl-names = "default"; - -@@ -1450,6 +1578,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ required-opps = <&rpmhpd_opp_low_svs>; -+ - pinctrl-0 = <&hub_i2c4_data_clk>; - pinctrl-names = "default"; - -@@ -1477,6 +1609,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ required-opps = <&rpmhpd_opp_low_svs>; -+ - pinctrl-0 = <&hub_i2c5_data_clk>; - pinctrl-names = "default"; - -@@ -1504,6 +1640,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ required-opps = <&rpmhpd_opp_low_svs>; -+ - pinctrl-0 = <&hub_i2c6_data_clk>; - pinctrl-names = "default"; - -@@ -1531,6 +1671,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ required-opps = <&rpmhpd_opp_low_svs>; -+ - pinctrl-0 = <&hub_i2c7_data_clk>; - pinctrl-names = "default"; - -@@ -1558,6 +1702,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ required-opps = <&rpmhpd_opp_low_svs>; -+ - pinctrl-0 = <&hub_i2c8_data_clk>; - pinctrl-names = "default"; - -@@ -1585,6 +1733,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - interconnect-names = "qup-core", - "qup-config"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ required-opps = <&rpmhpd_opp_low_svs>; -+ - pinctrl-0 = <&hub_i2c9_data_clk>; - pinctrl-names = "default"; - -@@ -1664,6 +1816,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, - <&gpi_dma1 1 0 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -1697,6 +1853,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, - <&gpi_dma1 1 0 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -1730,6 +1890,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, - <&gpi_dma1 1 1 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -1763,6 +1927,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, - <&gpi_dma1 1 1 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -1796,6 +1964,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_240mhz>; -+ - dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, - <&gpi_dma1 1 2 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -1829,6 +2001,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_240mhz>; -+ - dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, - <&gpi_dma1 1 2 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -1862,6 +2038,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, - <&gpi_dma1 1 3 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -1895,6 +2075,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, - <&gpi_dma1 1 3 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -1928,6 +2112,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, - <&gpi_dma1 1 4 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -1961,6 +2149,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, - <&gpi_dma1 1 4 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -1994,6 +2186,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, - <&gpi_dma1 1 5 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -2027,6 +2223,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, - <&gpi_dma1 1 5 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -2060,6 +2260,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, - <&gpi_dma1 1 6 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -2093,6 +2297,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_120mhz>; -+ - dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, - <&gpi_dma1 1 6 QCOM_GPI_SPI>; - dma-names = "tx", -@@ -2126,6 +2334,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, - <&gpi_dma1 1 7 QCOM_GPI_I2C>; - dma-names = "tx", -@@ -2159,6 +2371,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, - "qup-config", - "qup-memory"; - -+ power-domains = <&rpmhpd RPMHPD_CX>; -+ -+ operating-points-v2 = <&qup_opp_table_100mhz>; -+ - dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, - <&gpi_dma1 1 7 QCOM_GPI_SPI>; - dma-names = "tx", --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH 10/10] arm64: dts: qcom: sm8650: add UFS OPP table instead - of freq-table-hz property -From: Neil Armstrong -Date: Wed, 15 Jan 2025 14:44:02 +0100 -Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-10-eaa8b10e2af7@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Swich to an OPP table for the UFS frequency scaling instead of -the deprecated freq-table-hz property. - -The Operating Point table will also provide the associated -power domain level. - -Signed-off-by: Neil Armstrong -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/sm8650.dtsi | 50 ++++++++++++++++++++++++++++++------ - 1 file changed, 42 insertions(+), 8 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi -index 82be3f9051705507767023d7e195489852223ce3..483ae63e6032823e8cc13e8aeb6db70e3948f02d 100644 ---- a/arch/arm64/boot/dts/qcom/sm8650.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi -@@ -2900,14 +2900,6 @@ ufs_mem_hc: ufshc@1d84000 { - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; -- freq-table-hz = <100000000 403000000>, -- <0 0>, -- <0 0>, -- <100000000 403000000>, -- <100000000 403000000>, -- <0 0>, -- <0 0>, -- <0 0>; - - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; -@@ -2922,6 +2914,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - power-domains = <&gcc UFS_PHY_GDSC>; - required-opps = <&rpmhpd_opp_nom>; - -+ operating-points-v2 = <&ufs_opp_table>; -+ - iommus = <&apps_smmu 0x60 0>; - - lanes-per-direction = <2>; -@@ -2933,6 +2927,46 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - #reset-cells = <1>; - - status = "disabled"; -+ -+ ufs_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-100000000 { -+ opp-hz = /bits/ 64 <100000000>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>, -+ /bits/ 64 <100000000>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ }; -+ -+ opp-201500000 { -+ opp-hz = /bits/ 64 <201500000>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>, -+ /bits/ 64 <201500000>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>; -+ required-opps = <&rpmhpd_opp_svs>; -+ }; -+ -+ opp-403000000 { -+ opp-hz = /bits/ 64 <403000000>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>, -+ /bits/ 64 <403000000>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>, -+ /bits/ 64 <0>; -+ required-opps = <&rpmhpd_opp_nom>; -+ }; -+ }; - }; - - ice: crypto@1d88000 { --- -2.34.1 - diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0111_v5_20250227_neil_armstrong_dt_bindings_display_qcom_sm8_56_50_mdss_properly_document_the_interconnec.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0111_v5_20250227_neil_armstrong_dt_bindings_display_qcom_sm8_56_50_mdss_properly_document_the_interconnec.patch deleted file mode 100644 index 90f96aa632..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0111_v5_20250227_neil_armstrong_dt_bindings_display_qcom_sm8_56_50_mdss_properly_document_the_interconnec.patch +++ /dev/null @@ -1,85 +0,0 @@ -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 1/2] arm64: dts: qcom: sm8550: add missing cpu-cfg - interconnect path in the mdss node -From: Neil Armstrong -Date: Thu, 27 Feb 2025 10:00:32 +0100 -Message-Id: <20250227-topic-sm8x50-mdss-interconnect-bindings-fix-v5-1-bf6233c6ebe5@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -The bindings requires the mdp0-mem and the cpu-cfg interconnect path, -add the missing cpu-cfg path to fix the dtbs check error and also to ensure -that MDSS has enough bandwidth to let HLOS write config registers. - -Fixes: b8591df49cde ("arm64: dts: qcom: sm8550: correct MDSS interconnects") -Reviewed-by: Konrad Dybcio -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Neil Armstrong ---- - arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi -index d02d80d731b9a8746655af6da236307760a8f662..18bcb4ac6bd8433a0f10f4826f4c6958444c080f 100644 ---- a/arch/arm64/boot/dts/qcom/sm8550.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi -@@ -3355,8 +3355,10 @@ mdss: display-subsystem@ae00000 { - power-domains = <&dispcc MDSS_GDSC>; - - interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS -- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; -- interconnect-names = "mdp0-mem"; -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; -+ interconnect-names = "mdp0-mem", "cpu-cfg"; - - iommus = <&apps_smmu 0x1c00 0x2>; - --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 2/2] arm64: dts: qcom: sm8650: add missing cpu-cfg - interconnect path in the mdss node -From: Neil Armstrong -Date: Thu, 27 Feb 2025 10:00:33 +0100 -Message-Id: <20250227-topic-sm8x50-mdss-interconnect-bindings-fix-v5-2-bf6233c6ebe5@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -The bindings requires the mdp0-mem and the cpu-cfg interconnect path, -add the missing cpu-cfg path to fix the dtbs check error and also to ensure -that MDSS has enough bandwidth to let HLOS write config registers. - -Fixes: 9fa33cbca3d2 ("arm64: dts: qcom: sm8650: correct MDSS interconnects") -Reviewed-by: Konrad Dybcio -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Neil Armstrong ---- - arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi -index de960bcaf3ccf6e2be47bf63a02effbfb75241bf..719ad437756a499cee4170abccc83f2047f0f747 100644 ---- a/arch/arm64/boot/dts/qcom/sm8650.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi -@@ -4930,8 +4930,11 @@ mdss: display-subsystem@ae00000 { - resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; - - interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS -- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; -- interconnect-names = "mdp0-mem"; -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; -+ interconnect-names = "mdp0-mem", -+ "cpu-cfg"; - - power-domains = <&dispcc MDSS_GDSC>; - --- -2.34.1 - diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0140_v2_20250418_neil_armstrong_arm64_dts_qcom_sm8550_add_iris_dt_node.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0140_v2_20250418_neil_armstrong_arm64_dts_qcom_sm8550_add_iris_dt_node.patch deleted file mode 100644 index 048f0663bc..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0140_v2_20250418_neil_armstrong_arm64_dts_qcom_sm8550_add_iris_dt_node.patch +++ /dev/null @@ -1,172 +0,0 @@ -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v2] arm64: dts: qcom: sm8550: add iris DT node -From: Dikshita Agarwal -Date: Fri, 18 Apr 2025 14:45:22 +0200 -Message-Id: <20250418-topic-sm8x50-upstream-iris-8550-dt-v2-1-9218636acbdd@linaro.org> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Add DT entries for the sm8550 iris decoder. - -Since the firmware is required to be signed, only enable -on Qualcomm development boards where the firmware is -publicly distributed. - -Signed-off-by: Dikshita Agarwal -Signed-off-by: Neil Armstrong ---- -Changes in v2: -- Only enable on qcom dev boards -- Link to v1: https://lore.kernel.org/r/20250407-topic-sm8x50-upstream-iris-8550-dt-v1-1-1f7ab3083f49@linaro.org ---- - arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 5 +++ - arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 5 +++ - arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 5 +++ - arch/arm64/boot/dts/qcom/sm8550.dtsi | 76 +++++++++++++++++++++++++++++++++ - 4 files changed, 91 insertions(+) - -diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts -index 29bc1ddfc7b25f203c9f3b530610e45c44ae4fb2..866f4235ddb58a5e0776e34b9bb0277ef73236e5 100644 ---- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts -+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts -@@ -945,6 +945,11 @@ &ipa { - status = "okay"; - }; - -+&iris { -+ firmware-name = "qcom/vpu/vpu30_p4.mbn"; -+ status = "okay"; -+}; -+ - &gpi_dma1 { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts -index 5648ab60ba4c4bfaf5baa289969898277ee57cef..2362937729e8c5340d565b6199f6a6f9e29d2120 100644 ---- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts -+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts -@@ -672,6 +672,11 @@ fsa4480_sbu_mux: endpoint { - }; - }; - -+&iris { -+ firmware-name = "qcom/vpu/vpu30_p4.mbn"; -+ status = "okay"; -+}; -+ - &lpass_tlmm { - spkr_1_sd_n_active: spkr-1-sd-n-active-state { - pins = "gpio17"; -diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts -index 3a6cb279130489168f8d20a6e27808647debdb41..4f713127310be54361e29ddb97e7f209493109be 100644 ---- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts -+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts -@@ -779,6 +779,11 @@ &ipa { - status = "okay"; - }; - -+&iris { -+ firmware-name = "qcom/vpu/vpu30_p4.mbn"; -+ status = "okay"; -+}; -+ - &gpi_dma1 { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi -index f78d5292c5dd5ec88c8deb0ca6e5078511ac52b7..dbe01392b436d03ef58733a59f60c3021bac3e6b 100644 ---- a/arch/arm64/boot/dts/qcom/sm8550.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi -@@ -3220,6 +3220,82 @@ opp-202000000 { - }; - }; - -+ iris: video-codec@aa00000 { -+ compatible = "qcom,sm8550-iris"; -+ -+ reg = <0 0x0aa00000 0 0xf0000>; -+ interrupts = ; -+ -+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, -+ <&videocc VIDEO_CC_MVS0_GDSC>, -+ <&rpmhpd RPMHPD_MXC>, -+ <&rpmhpd RPMHPD_MMCX>; -+ power-domain-names = "venus", "vcodec0", "mxc", "mmcx"; -+ operating-points-v2 = <&iris_opp_table>; -+ -+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>, -+ <&videocc VIDEO_CC_MVS0C_CLK>, -+ <&videocc VIDEO_CC_MVS0_CLK>; -+ clock-names = "iface", "core", "vcodec0_core"; -+ -+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY -+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, -+ <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; -+ interconnect-names = "cpu-cfg", "video-mem"; -+ -+ /* FW load region */ -+ memory-region = <&video_mem>; -+ -+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; -+ reset-names = "bus"; -+ -+ iommus = <&apps_smmu 0x1940 0x0000>, -+ <&apps_smmu 0x1947 0x0000>; -+ dma-coherent; -+ -+ /* -+ * IRIS firmware is signed by vendors, only -+ * enable in boards where the proper signed firmware -+ * is available. -+ */ -+ status = "disabled"; -+ -+ iris_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-240000000 { -+ opp-hz = /bits/ 64 <240000000>; -+ required-opps = <&rpmhpd_opp_svs>, -+ <&rpmhpd_opp_low_svs>; -+ }; -+ -+ opp-338000000 { -+ opp-hz = /bits/ 64 <338000000>; -+ required-opps = <&rpmhpd_opp_svs>, -+ <&rpmhpd_opp_svs>; -+ }; -+ -+ opp-366000000 { -+ opp-hz = /bits/ 64 <366000000>; -+ required-opps = <&rpmhpd_opp_svs_l1>, -+ <&rpmhpd_opp_svs_l1>; -+ }; -+ -+ opp-444000000 { -+ opp-hz = /bits/ 64 <444000000>; -+ required-opps = <&rpmhpd_opp_turbo>, -+ <&rpmhpd_opp_turbo>; -+ }; -+ -+ opp-533333334 { -+ opp-hz = /bits/ 64 <533333334>; -+ required-opps = <&rpmhpd_opp_turbo_l1>, -+ <&rpmhpd_opp_turbo_l1>; -+ }; -+ }; -+ }; -+ - videocc: clock-controller@aaf0000 { - compatible = "qcom,sm8550-videocc"; - reg = <0 0x0aaf0000 0 0x10000>; - ---- -base-commit: 2bdde620f7f2bff2ff1cb7dc166859eaa0c78a7c -change-id: 20250407-topic-sm8x50-upstream-iris-8550-dt-2846b493e652 - -Best regards, --- -Neil Armstrong - diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0150_v2-drm-msm-adreno-Drop-fictional-address_space_size.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0150_v2-drm-msm-adreno-Drop-fictional-address_space_size.patch deleted file mode 100644 index a11c8cb6c8..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0150_v2-drm-msm-adreno-Drop-fictional-address_space_size.patch +++ /dev/null @@ -1,305 +0,0 @@ -From patchwork Mon Apr 21 17:21:43 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v2] drm/msm/adreno: Drop fictional address_space_size -From: Rob Clark -X-Patchwork-Id: 649467 -Message-Id: <20250421172144.168273-1-robdclark@gmail.com> -To: dri-devel@lists.freedesktop.org -Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, - Rob Clark , - Dmitry Baryshkov , - Rob Clark , Sean Paul , - Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten , - David Airlie , Simona Vetter , - linux-kernel@vger.kernel.org (open list) -Date: Mon, 21 Apr 2025 10:21:43 -0700 - -From: Rob Clark - -Really the only purpose of this was to limit the address space size to -4GB to avoid 32b rollover problems in 64b pointer math in older sqe fw. -So replace the address_space_size with a quirk limiting the address -space to 4GB. In all other cases, use the SMMU input address size (IAS) -to determine the address space size. - -v2: Properly account for vm_start - -Signed-off-by: Rob Clark -Reviewed-by: Dmitry Baryshkov ---- - drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 33 +++++++++++------------ - drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- - drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 ++++++++++--- - drivers/gpu/drm/msm/adreno/adreno_gpu.h | 4 ++- - 4 files changed, 36 insertions(+), 22 deletions(-) - -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c -index 53e2ff4406d8..f85b7e89bafb 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c -+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c -@@ -681,6 +681,7 @@ static const struct adreno_info a6xx_gpus[] = { - [ADRENO_FW_SQE] = "a630_sqe.fw", - }, - .gmem = (SZ_128K + SZ_4K), -+ .quirks = ADRENO_QUIRK_4GB_VA, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a6xx_gpu_init, - .zapfw = "a610_zap.mdt", -@@ -713,6 +714,7 @@ static const struct adreno_info a6xx_gpus[] = { - [ADRENO_FW_GMU] = "a630_gmu.bin", - }, - .gmem = SZ_512K, -+ .quirks = ADRENO_QUIRK_4GB_VA, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mdt", -@@ -743,7 +745,8 @@ static const struct adreno_info a6xx_gpus[] = { - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, -- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, -+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | -+ ADRENO_QUIRK_4GB_VA, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mbn", - .a6xx = &(const struct a6xx_info) { -@@ -769,7 +772,8 @@ static const struct adreno_info a6xx_gpus[] = { - }, - .gmem = SZ_512K, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, -- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, -+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | -+ ADRENO_QUIRK_4GB_VA, - .init = a6xx_gpu_init, - .a6xx = &(const struct a6xx_info) { - .protect = &a630_protect, -@@ -791,6 +795,7 @@ static const struct adreno_info a6xx_gpus[] = { - [ADRENO_FW_GMU] = "a619_gmu.bin", - }, - .gmem = SZ_512K, -+ .quirks = ADRENO_QUIRK_4GB_VA, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mdt", -@@ -815,6 +820,7 @@ static const struct adreno_info a6xx_gpus[] = { - [ADRENO_FW_GMU] = "a619_gmu.bin", - }, - .gmem = SZ_512K, -+ .quirks = ADRENO_QUIRK_4GB_VA, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mdt", -@@ -838,8 +844,9 @@ static const struct adreno_info a6xx_gpus[] = { - [ADRENO_FW_GMU] = "a619_gmu.bin", - }, - .gmem = SZ_512K, -+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | -+ ADRENO_QUIRK_4GB_VA, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, -- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a615_zap.mdt", - .a6xx = &(const struct a6xx_info) { -@@ -874,7 +881,6 @@ static const struct adreno_info a6xx_gpus[] = { - .gmu_cgc_mode = 0x00020200, - .prim_fifo_threshold = 0x00010000, - }, -- .address_space_size = SZ_16G, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 137, 1 }, -@@ -907,7 +913,6 @@ static const struct adreno_info a6xx_gpus[] = { - { /* sentinel */ }, - }, - }, -- .address_space_size = SZ_16G, - }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x06030001, -@@ -920,8 +925,9 @@ static const struct adreno_info a6xx_gpus[] = { - [ADRENO_FW_GMU] = "a630_gmu.bin", - }, - .gmem = SZ_1M, -+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | -+ ADRENO_QUIRK_4GB_VA, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, -- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a630_zap.mdt", - .a6xx = &(const struct a6xx_info) { -@@ -939,8 +945,9 @@ static const struct adreno_info a6xx_gpus[] = { - [ADRENO_FW_GMU] = "a640_gmu.bin", - }, - .gmem = SZ_1M, -+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | -+ ADRENO_QUIRK_4GB_VA, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, -- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a640_zap.mdt", - .a6xx = &(const struct a6xx_info) { -@@ -973,7 +980,6 @@ static const struct adreno_info a6xx_gpus[] = { - .gmu_cgc_mode = 0x00020202, - .prim_fifo_threshold = 0x00300200, - }, -- .address_space_size = SZ_16G, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 1, 1 }, -@@ -1000,7 +1006,6 @@ static const struct adreno_info a6xx_gpus[] = { - .gmu_cgc_mode = 0x00020000, - .prim_fifo_threshold = 0x00300200, - }, -- .address_space_size = SZ_16G, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06060300), - .family = ADRENO_6XX_GEN4, -@@ -1019,7 +1024,6 @@ static const struct adreno_info a6xx_gpus[] = { - .gmu_cgc_mode = 0x00020200, - .prim_fifo_threshold = 0x00300200, - }, -- .address_space_size = SZ_16G, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x06030500), - .family = ADRENO_6XX_GEN4, -@@ -1039,7 +1043,6 @@ static const struct adreno_info a6xx_gpus[] = { - .gmu_cgc_mode = 0x00020202, - .prim_fifo_threshold = 0x00200200, - }, -- .address_space_size = SZ_16G, - .speedbins = ADRENO_SPEEDBINS( - { 0, 0 }, - { 117, 0 }, -@@ -1056,8 +1059,9 @@ static const struct adreno_info a6xx_gpus[] = { - [ADRENO_FW_GMU] = "a640_gmu.bin", - }, - .gmem = SZ_2M, -+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | -+ ADRENO_QUIRK_4GB_VA, - .inactive_period = DRM_MSM_INACTIVE_PERIOD, -- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, - .init = a6xx_gpu_init, - .zapfw = "a640_zap.mdt", - .a6xx = &(const struct a6xx_info) { -@@ -1085,7 +1089,6 @@ static const struct adreno_info a6xx_gpus[] = { - .gmu_cgc_mode = 0x00020200, - .prim_fifo_threshold = 0x00800200, - }, -- .address_space_size = SZ_16G, - } - }; - DECLARE_ADRENO_GPULIST(a6xx); -@@ -1395,7 +1398,6 @@ static const struct adreno_info a7xx_gpus[] = { - .pwrup_reglist = &a7xx_pwrup_reglist, - .gmu_cgc_mode = 0x00020000, - }, -- .address_space_size = SZ_16G, - .preempt_record_size = 2860 * SZ_1K, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ -@@ -1429,7 +1431,6 @@ static const struct adreno_info a7xx_gpus[] = { - { /* sentinel */ }, - }, - }, -- .address_space_size = SZ_16G, - .preempt_record_size = 4192 * SZ_1K, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ -@@ -1451,7 +1452,6 @@ static const struct adreno_info a7xx_gpus[] = { - .gmu_chipid = 0x7050001, - .gmu_cgc_mode = 0x00020202, - }, -- .address_space_size = SZ_256G, - .preempt_record_size = 4192 * SZ_1K, - }, { - .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ -@@ -1484,7 +1484,6 @@ static const struct adreno_info a7xx_gpus[] = { - { /* sentinel */ }, - }, - }, -- .address_space_size = SZ_16G, - .preempt_record_size = 3572 * SZ_1K, - } - }; -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -index eeb8b5e582d5..129c33f0b027 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -@@ -2272,7 +2272,7 @@ a6xx_create_private_address_space(struct msm_gpu *gpu) - return ERR_CAST(mmu); - - return msm_gem_address_space_create(mmu, -- "gpu", 0x100000000ULL, -+ "gpu", ADRENO_VM_START, - adreno_private_address_space_size(gpu)); - } - -diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c -index 59cfed5acace..e80db01a01c0 100644 ---- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c -+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c -@@ -236,14 +236,27 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, - u64 adreno_private_address_space_size(struct msm_gpu *gpu) - { - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); -+ struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev); -+ const struct io_pgtable_cfg *ttbr1_cfg; - - if (address_space_size) - return address_space_size; - -- if (adreno_gpu->info->address_space_size) -- return adreno_gpu->info->address_space_size; -+ if (adreno_gpu->info->quirks & ADRENO_QUIRK_4GB_VA) -+ return SZ_4G; - -- return SZ_4G; -+ if (!adreno_smmu || !adreno_smmu->get_ttbr1_cfg) -+ return SZ_4G; -+ -+ ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie); -+ -+ /* -+ * Userspace VM is actually using TTBR0, but both are the same size, -+ * with b48 (sign bit) selecting which TTBRn to use. So if IAS is -+ * 48, the total (kernel+user) address space size is effectively -+ * 49 bits. But what userspace is control of is the lower 48. -+ */ -+ return BIT(ttbr1_cfg->ias) - ADRENO_VM_START; - } - - void adreno_check_and_reenable_stall(struct adreno_gpu *adreno_gpu) -diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h -index a1e2d9e87b75..2366a57b280f 100644 ---- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h -+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h -@@ -57,6 +57,7 @@ enum adreno_family { - #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) - #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) - #define ADRENO_QUIRK_PREEMPTION BIT(5) -+#define ADRENO_QUIRK_4GB_VA BIT(6) - - /* Helper for formating the chip_id in the way that userspace tools like - * crashdec expect. -@@ -104,7 +105,6 @@ struct adreno_info { - union { - const struct a6xx_info *a6xx; - }; -- u64 address_space_size; - /** - * @speedbins: Optional table of fuse to speedbin mappings - * -@@ -600,6 +600,8 @@ static inline int adreno_is_a7xx(struct adreno_gpu *gpu) - adreno_is_a740_family(gpu); - } - -+/* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */ -+#define ADRENO_VM_START 0x100000000ULL - u64 adreno_private_address_space_size(struct msm_gpu *gpu); - int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, - uint32_t param, uint64_t *value, uint32_t *len); diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0151_drm-msm-Be-more-robust-when-HFI-response-times-out.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0151_drm-msm-Be-more-robust-when-HFI-response-times-out.patch deleted file mode 100644 index 5114620b01..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0151_drm-msm-Be-more-robust-when-HFI-response-times-out.patch +++ /dev/null @@ -1,113 +0,0 @@ -From patchwork Thu Apr 24 13:30:17 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v2] drm/msm: Be more robust when HFI response times out -From: Connor Abbott -X-Patchwork-Id: 650013 -Message-Id: <20250424-msm-hfi-resp-fix-v2-1-3ce6adc86ebb@gmail.com> -To: Rob Clark , Sean Paul , - Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten -Cc: freedreno@lists.freedesktop.org, Connor Abbott -Date: Thu, 24 Apr 2025 09:30:17 -0400 - -If the GMU takes too long to respond to an HFI message, we may return -early. If the GMU does eventually respond, and then we send a second -message, we will see the response for the first, throw another error, -and keep going. But we don't currently wait for the interrupt from the -GMU again, so if the second response isn't there immediately we may -prematurely return. This can cause a continuous cycle of missed HFI -messages, and for reasons I don't quite understand the GMU does not shut -down properly when this happens. - -Fix this by waiting for the GMU interrupt when we see an empty queue. If -the GMU never responds then the queue really is empty and we quit. We -can't wait for the interrupt when we see a wrong response seqnum because -the GMU might have already queued both responses by the time we clear -the interrupt the first time so we do need to check the queue before -waiting on the interrupt again. - -Signed-off-by: Connor Abbott -Reviewed-by: Konrad Dybcio ---- -Changes in v2: -- Add back error print about the queue being empty if we timeout while - waiting for a message when the queue is empty. -- Link to v1: https://lore.kernel.org/r/20250422-msm-hfi-resp-fix-v1-1-b0ba02b93b91@gmail.com ---- - drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 35 ++++++++++++++++++++++++++--------- - 1 file changed, 26 insertions(+), 9 deletions(-) - - ---- -base-commit: 866e43b945bf98f8e807dfa45eca92f931f3a032 -change-id: 20250422-msm-hfi-resp-fix-58ab3a19554f - -Best regards, - -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c -index 0989aee3dd2cf9bc3405c3b25a595c22e6f06387..1bc40d667281a22a34e4f510b2a1333f9c5675c6 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c -+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c -@@ -100,12 +100,10 @@ static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, - return 0; - } - --static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, -- u32 *payload, u32 payload_size) -+static int a6xx_hfi_wait_for_msg_interrupt(struct a6xx_gmu *gmu, u32 id, u32 seqnum) - { -- struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE]; -- u32 val; - int ret; -+ u32 val; - - /* Wait for a response */ - ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, -@@ -122,6 +120,19 @@ static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, - gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, - A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ); - -+ return 0; -+} -+ -+static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, -+ u32 *payload, u32 payload_size) -+{ -+ struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE]; -+ int ret; -+ -+ ret = a6xx_hfi_wait_for_msg_interrupt(gmu, id, seqnum); -+ if (ret) -+ return ret; -+ - for (;;) { - struct a6xx_hfi_msg_response resp; - -@@ -129,12 +140,18 @@ static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, - ret = a6xx_hfi_queue_read(gmu, queue, (u32 *) &resp, - sizeof(resp) >> 2); - -- /* If the queue is empty our response never made it */ -+ /* If the queue is empty, there may have been previous missed -+ * responses that preceded the response to our packet. Wait -+ * further before we give up. -+ */ - if (!ret) { -- DRM_DEV_ERROR(gmu->dev, -- "The HFI response queue is unexpectedly empty\n"); -- -- return -ENOENT; -+ ret = a6xx_hfi_wait_for_msg_interrupt(gmu, id, seqnum); -+ if (ret) { -+ DRM_DEV_ERROR(gmu->dev, -+ "The HFI response queue is unexpectedly empty\n"); -+ return ret; -+ } -+ continue; - } - - if (HFI_HEADER_ID(resp.header) == HFI_F2H_MSG_ERROR) { diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0152_drm-msm-gpu-Fix-crash-when-throttling-GPU-immediately-during-boot.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0152_drm-msm-gpu-Fix-crash-when-throttling-GPU-immediately-during-boot.patch deleted file mode 100644 index 7ec20e83fb..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0152_drm-msm-gpu-Fix-crash-when-throttling-GPU-immediately-during-boot.patch +++ /dev/null @@ -1,93 +0,0 @@ -From patchwork Tue Apr 29 08:33:56 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: drm/msm/gpu: Fix crash when throttling GPU immediately during boot -From: Stephan Gerhold -X-Patchwork-Id: 650772 -Message-Id: - <20250429-drm-msm-gpu-hot-devfreq-boot-v1-1-8aa9c5f266b4@linaro.org> -To: Rob Clark -Cc: Sean Paul , Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten , - David Airlie , Simona Vetter , - Douglas Anderson , linux-arm-msm@vger.kernel.org, - dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, - linux-kernel@vger.kernel.org, Johan Hovold -Date: Tue, 29 Apr 2025 10:33:56 +0200 - -There is a small chance that the GPU is already hot during boot. In that -case, the call to of_devfreq_cooling_register() will immediately try to -apply devfreq cooling, as seen in the following crash: - - Unable to handle kernel paging request at virtual address 0000000000014110 - pc : a6xx_gpu_busy+0x1c/0x58 [msm] - lr : msm_devfreq_get_dev_status+0xbc/0x140 [msm] - Call trace: - a6xx_gpu_busy+0x1c/0x58 [msm] (P) - devfreq_simple_ondemand_func+0x3c/0x150 - devfreq_update_target+0x44/0xd8 - qos_max_notifier_call+0x30/0x84 - blocking_notifier_call_chain+0x6c/0xa0 - pm_qos_update_target+0xd0/0x110 - freq_qos_apply+0x3c/0x74 - apply_constraint+0x88/0x148 - __dev_pm_qos_update_request+0x7c/0xcc - dev_pm_qos_update_request+0x38/0x5c - devfreq_cooling_set_cur_state+0x98/0xf0 - __thermal_cdev_update+0x64/0xb4 - thermal_cdev_update+0x4c/0x58 - step_wise_manage+0x1f0/0x318 - __thermal_zone_device_update+0x278/0x424 - __thermal_cooling_device_register+0x2bc/0x308 - thermal_of_cooling_device_register+0x10/0x1c - of_devfreq_cooling_register_power+0x240/0x2bc - of_devfreq_cooling_register+0x14/0x20 - msm_devfreq_init+0xc4/0x1a0 [msm] - msm_gpu_init+0x304/0x574 [msm] - adreno_gpu_init+0x1c4/0x2e0 [msm] - a6xx_gpu_init+0x5c8/0x9c8 [msm] - adreno_bind+0x2a8/0x33c [msm] - ... - -At this point we haven't initialized the GMU at all yet, so we cannot read -the GMU registers inside a6xx_gpu_busy(). A similar issue was fixed before -in commit 6694482a70e9 ("drm/msm: Avoid unclocked GMU register access in -6xx gpu_busy"): msm_devfreq_init() does call devfreq_suspend_device(), but -unlike msm_devfreq_suspend(), it doesn't set the df->suspended flag -accordingly. This means the df->suspended flag does not match the actual -devfreq state after initialization and msm_devfreq_get_dev_status() will -end up accessing GMU registers, causing the crash. - -Fix this by setting df->suspended correctly during initialization. - -Cc: stable@vger.kernel.org -Fixes: 6694482a70e9 ("drm/msm: Avoid unclocked GMU register access in 6xx gpu_busy") -Signed-off-by: Stephan Gerhold -Reviewed-by: Douglas Anderson -Reviewed-by: Konrad Dybcio ---- - drivers/gpu/drm/msm/msm_gpu_devfreq.c | 1 + - 1 file changed, 1 insertion(+) - - ---- -base-commit: 33035b665157558254b3c21c3f049fd728e72368 -change-id: 20250428-drm-msm-gpu-hot-devfreq-boot-36184dbc7075 - -Best regards, - -diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c -index 6970b0f7f457c8535ecfeaa705db871594ae5fc4..2e1d5c3432728cde15d91f69da22bb915588fe86 100644 ---- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c -+++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c -@@ -156,6 +156,7 @@ void msm_devfreq_init(struct msm_gpu *gpu) - priv->gpu_devfreq_config.downdifferential = 10; - - mutex_init(&df->lock); -+ df->suspended = true; - - ret = dev_pm_qos_add_request(&gpu->pdev->dev, &df->boost_freq, - DEV_PM_QOS_MIN_FREQUENCY, 0); diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0153_v6_20250503_quic_akhilpo_support_for_gpu_acd_feature_on_adreno_x1_85.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0153_v6_20250503_quic_akhilpo_support_for_gpu_acd_feature_on_adreno_x1_85.patch deleted file mode 100644 index 54966f9717..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0153_v6_20250503_quic_akhilpo_support_for_gpu_acd_feature_on_adreno_x1_85.patch +++ /dev/null @@ -1,688 +0,0 @@ -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 1/7] drm/msm/adreno: Add support for ACD -From: Akhil P Oommen -Date: Sat, 03 May 2025 12:33:32 +0530 -Message-Id: <20250503-gpu-acd-v6-1-ab1b52866c64@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce -the power consumption. In some chipsets, it is also a requirement to -support higher GPU frequencies. This patch adds support for GPU ACD by -sending necessary data to GMU and AOSS. The feature support for the -chipset is detected based on devicetree data. - -Tested-by: Maya Matuszczyk -Tested-by: Anthony Ruhier -Reviewed-by: Konrad Dybcio -Signed-off-by: Akhil P Oommen ---- - drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 84 ++++++++++++++++++++++++++++++----- - drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + - drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 36 +++++++++++++++ - drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 21 +++++++++ - 4 files changed, 132 insertions(+), 10 deletions(-) - -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c -index c8711938a5f4478ea02e7a4b336291c91e591358..6bd6d7c67f98b38cb1d23f926b5e6ccbd7f2ec53 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c -+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c -@@ -1064,14 +1064,6 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) - - gmu->hung = false; - -- /* Notify AOSS about the ACD state (unimplemented for now => disable it) */ -- if (!IS_ERR(gmu->qmp)) { -- ret = qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}", -- 0 /* Hardcode ACD to be disabled for now */); -- if (ret) -- dev_err(gmu->dev, "failed to send GPU ACD state\n"); -- } -- - /* Turn on the resources */ - pm_runtime_get_sync(gmu->dev); - -@@ -1671,6 +1663,68 @@ static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) - return a6xx_gmu_rpmh_votes_init(gmu); - } - -+static int a6xx_gmu_acd_probe(struct a6xx_gmu *gmu) -+{ -+ struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); -+ struct a6xx_hfi_acd_table *cmd = &gmu->acd_table; -+ struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; -+ struct msm_gpu *gpu = &adreno_gpu->base; -+ int ret, i, cmd_idx = 0; -+ -+ cmd->version = 1; -+ cmd->stride = 1; -+ cmd->enable_by_level = 0; -+ -+ /* Skip freq = 0 and parse acd-level for rest of the OPPs */ -+ for (i = 1; i < gmu->nr_gpu_freqs; i++) { -+ struct dev_pm_opp *opp; -+ struct device_node *np; -+ unsigned long freq; -+ u32 val; -+ -+ freq = gmu->gpu_freqs[i]; -+ opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, freq, true); -+ np = dev_pm_opp_get_of_node(opp); -+ -+ ret = of_property_read_u32(np, "qcom,opp-acd-level", &val); -+ of_node_put(np); -+ dev_pm_opp_put(opp); -+ if (ret == -EINVAL) -+ continue; -+ else if (ret) { -+ DRM_DEV_ERROR(gmu->dev, "Unable to read acd level for freq %lu\n", freq); -+ return ret; -+ } -+ -+ cmd->enable_by_level |= BIT(i); -+ cmd->data[cmd_idx++] = val; -+ } -+ -+ cmd->num_levels = cmd_idx; -+ -+ /* It is a problem if qmp node is unavailable when ACD is required */ -+ if (cmd->enable_by_level && IS_ERR_OR_NULL(gmu->qmp)) { -+ DRM_DEV_ERROR(gmu->dev, "Unable to send ACD state to AOSS\n"); -+ return -EINVAL; -+ } -+ -+ /* Otherwise, nothing to do if qmp is unavailable */ -+ if (IS_ERR_OR_NULL(gmu->qmp)) -+ return 0; -+ -+ /* -+ * Notify AOSS about the ACD state. AOSS is supposed to assume that ACD is disabled on -+ * system reset. So it is harmless if we couldn't notify 'OFF' state -+ */ -+ ret = qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}", !!cmd->enable_by_level); -+ if (ret && cmd->enable_by_level) { -+ DRM_DEV_ERROR(gmu->dev, "Failed to send ACD state to AOSS\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ - static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) - { - int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); -@@ -1992,7 +2046,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) - gmu->qmp = qmp_get(gmu->dev); - if (IS_ERR(gmu->qmp) && adreno_is_a7xx(adreno_gpu)) { - ret = PTR_ERR(gmu->qmp); -- goto remove_device_link; -+ goto detach_gxpd; - } - - init_completion(&gmu->pd_gate); -@@ -2008,6 +2062,10 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) - /* Get the power levels for the GMU and GPU */ - a6xx_gmu_pwrlevels_probe(gmu); - -+ ret = a6xx_gmu_acd_probe(gmu); -+ if (ret) -+ goto detach_gxpd; -+ - /* Set up the HFI queues */ - a6xx_hfi_init(gmu); - -@@ -2018,7 +2076,13 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) - - return 0; - --remove_device_link: -+detach_gxpd: -+ if (!IS_ERR_OR_NULL(gmu->gxpd)) -+ dev_pm_domain_detach(gmu->gxpd, false); -+ -+ if (!IS_ERR_OR_NULL(gmu->qmp)) -+ qmp_put(gmu->qmp); -+ - device_link_del(link); - - detach_cxpd: -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h -index 0c888b326cfb485400118f3601fa5f1949b03374..b2d4489b40249b1916ab4a42c89e3f4bdc5c4af9 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h -+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h -@@ -93,6 +93,7 @@ struct a6xx_gmu { - int nr_gpu_freqs; - unsigned long gpu_freqs[GMU_MAX_GX_FREQS]; - u32 gx_arc_votes[GMU_MAX_GX_FREQS]; -+ struct a6xx_hfi_acd_table acd_table; - - int nr_gpu_bws; - unsigned long gpu_bw_table[GMU_MAX_GX_FREQS]; -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c -index 0989aee3dd2cf9bc3405c3b25a595c22e6f06387..b256092596fbab86d4eb8c17ac7c89cf94827105 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c -+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c -@@ -748,6 +748,38 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) - NULL, 0); - } - -+#define HFI_FEATURE_ACD 12 -+ -+static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu) -+{ -+ struct a6xx_hfi_acd_table *acd_table = &gmu->acd_table; -+ struct a6xx_hfi_msg_feature_ctrl msg = { -+ .feature = HFI_FEATURE_ACD, -+ .enable = 1, -+ .data = 0, -+ }; -+ int ret; -+ -+ if (!acd_table->enable_by_level) -+ return 0; -+ -+ /* Enable ACD feature at GMU */ -+ ret = a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), NULL, 0); -+ if (ret) { -+ DRM_DEV_ERROR(gmu->dev, "Unable to enable ACD (%d)\n", ret); -+ return ret; -+ } -+ -+ /* Send ACD table to GMU */ -+ ret = a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_ACD, acd_table, sizeof(*acd_table), NULL, 0); -+ if (ret) { -+ DRM_DEV_ERROR(gmu->dev, "Unable to ACD table (%d)\n", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ - static int a6xx_hfi_send_test(struct a6xx_gmu *gmu) - { - struct a6xx_hfi_msg_test msg = { 0 }; -@@ -845,6 +877,10 @@ int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state) - if (ret) - return ret; - -+ ret = a6xx_hfi_enable_acd(gmu); -+ if (ret) -+ return ret; -+ - ret = a6xx_hfi_send_core_fw_start(gmu); - if (ret) - return ret; -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h -index 52ba4a07d7b9a709289acd244a751ace9bdaab5d..653ef720e2da4d2b0793c0b76e994b6f6dc524c7 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h -+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h -@@ -151,12 +151,33 @@ struct a6xx_hfi_msg_test { - u32 header; - }; - -+#define HFI_H2F_MSG_ACD 7 -+#define MAX_ACD_STRIDE 2 -+ -+struct a6xx_hfi_acd_table { -+ u32 header; -+ u32 version; -+ u32 enable_by_level; -+ u32 stride; -+ u32 num_levels; -+ u32 data[16 * MAX_ACD_STRIDE]; -+}; -+ - #define HFI_H2F_MSG_START 10 - - struct a6xx_hfi_msg_start { - u32 header; - }; - -+#define HFI_H2F_FEATURE_CTRL 11 -+ -+struct a6xx_hfi_msg_feature_ctrl { -+ u32 header; -+ u32 feature; -+ u32 enable; -+ u32 data; -+}; -+ - #define HFI_H2F_MSG_CORE_FW_START 14 - - struct a6xx_hfi_msg_core_fw_start { --- -2.48.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 2/7] drm/msm/a6xx: Increase HFI response timeout -From: Akhil P Oommen -Date: Sat, 03 May 2025 12:33:33 +0530 -Message-Id: <20250503-gpu-acd-v6-2-ab1b52866c64@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -When ACD feature is enabled, it triggers some internal calibrations -which result in a pretty long delay during the first HFI perf vote. -So, increase the HFI response timeout to match the downstream driver. - -Tested-by: Maya Matuszczyk -Tested-by: Anthony Ruhier -Signed-off-by: Akhil P Oommen -Reviewed-by: Konrad Dybcio ---- - drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c -index b256092596fbab86d4eb8c17ac7c89cf94827105..d0ddae1617c3213a1bb2cb5c18b8653c5c1689e6 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c -+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c -@@ -109,7 +109,7 @@ static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, - - /* Wait for a response */ - ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, -- val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 5000); -+ val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 1000000); - - if (ret) { - DRM_DEV_ERROR(gmu->dev, --- -2.48.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 3/7] drm/msm: a6x: Rework qmp_get() error handling -From: Akhil P Oommen -Date: Sat, 03 May 2025 12:33:34 +0530 -Message-Id: <20250503-gpu-acd-v6-3-ab1b52866c64@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Fix the following for qmp_get() errors: - -1. Correctly handle probe defer for A6x GPUs -2. Ignore other errors because those are okay when GPU ACD is -not required. They are checked again during gpu acd probe. - -Reviewed-by: Konrad Dybcio -Tested-by: Maya Matuszczyk -Tested-by: Anthony Ruhier -Signed-off-by: Akhil P Oommen ---- - drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c -index 6bd6d7c67f98b38cb1d23f926b5e6ccbd7f2ec53..48b4ca8894ba38176481b62b7fd1406472369df1 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c -+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c -@@ -2043,9 +2043,10 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) - goto detach_cxpd; - } - -+ /* Other errors are handled during GPU ACD probe */ - gmu->qmp = qmp_get(gmu->dev); -- if (IS_ERR(gmu->qmp) && adreno_is_a7xx(adreno_gpu)) { -- ret = PTR_ERR(gmu->qmp); -+ if (PTR_ERR_OR_ZERO(gmu->qmp) == -EPROBE_DEFER) { -+ ret = -EPROBE_DEFER; - goto detach_gxpd; - } - --- -2.48.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 4/7] drm/msm/adreno: Add module param to disable ACD -From: Akhil P Oommen -Date: Sat, 03 May 2025 12:33:35 +0530 -Message-Id: <20250503-gpu-acd-v6-4-ab1b52866c64@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Add a module param to disable ACD which will help to quickly rule it -out for any GPU issues. - -Tested-by: Maya Matuszczyk -Tested-by: Anthony Ruhier -Reviewed-by: Konrad Dybcio -Signed-off-by: Akhil P Oommen ---- - drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++++++ - drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ - 2 files changed, 11 insertions(+) - -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c -index 48b4ca8894ba38176481b62b7fd1406472369df1..38c0f8ef85c3d260864541d83abe43e49c772c52 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c -+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c -@@ -1670,6 +1670,13 @@ static int a6xx_gmu_acd_probe(struct a6xx_gmu *gmu) - struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; - struct msm_gpu *gpu = &adreno_gpu->base; - int ret, i, cmd_idx = 0; -+ extern bool disable_acd; -+ -+ /* Skip ACD probe if requested via module param */ -+ if (disable_acd) { -+ DRM_DEV_ERROR(gmu->dev, "Skipping GPU ACD probe\n"); -+ return 0; -+ } - - cmd->version = 1; - cmd->stride = 1; -diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c -index 236b25c094cd5d462f4b6653de7b7910985cccb6..f5e1490d07c1868fa21cddb38de44c28af5ca0d5 100644 ---- a/drivers/gpu/drm/msm/adreno/adreno_device.c -+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c -@@ -24,6 +24,10 @@ int enable_preemption = -1; - MODULE_PARM_DESC(enable_preemption, "Enable preemption (A7xx only) (1=on , 0=disable, -1=auto (default))"); - module_param(enable_preemption, int, 0600); - -+bool disable_acd; -+MODULE_PARM_DESC(disable_acd, "Forcefully disable GPU ACD"); -+module_param_unsafe(disable_acd, bool, 0400); -+ - extern const struct adreno_gpulist a2xx_gpulist; - extern const struct adreno_gpulist a3xx_gpulist; - extern const struct adreno_gpulist a4xx_gpulist; --- -2.48.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 5/7] dt-bindings: opp: Add v2-qcom-adreno vendor - bindings -From: Akhil P Oommen -Date: Sat, 03 May 2025 12:33:36 +0530 -Message-Id: <20250503-gpu-acd-v6-5-ab1b52866c64@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Add a new schema which extends opp-v2 to support a new vendor specific -property required for Adreno GPUs found in Qualcomm's SoCs. The new -property called "qcom,opp-acd-level" carries a u32 value recommended -for each opp needs to be shared to GMU during runtime. - -Also, update MAINTAINERS file include the new opp-v2-qcom-adreno.yaml. - -Cc: Rob Clark -Tested-by: Maya Matuszczyk -Tested-by: Anthony Ruhier -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Akhil P Oommen ---- - .../bindings/opp/opp-v2-qcom-adreno.yaml | 96 ++++++++++++++++++++++ - MAINTAINERS | 1 + - 2 files changed, 97 insertions(+) - -diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml -new file mode 100644 -index 0000000000000000000000000000000000000000..a27ba7b663d456f964628a91a661b51a684de1be ---- /dev/null -+++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml -@@ -0,0 +1,96 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/opp/opp-v2-qcom-adreno.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Qualcomm Adreno compatible OPP supply -+ -+description: -+ Adreno GPUs present in Qualcomm's Snapdragon chipsets uses an OPP specific -+ ACD related information tailored for the specific chipset. This binding -+ provides the information needed to describe such a hardware value. -+ -+maintainers: -+ - Rob Clark -+ -+allOf: -+ - $ref: opp-v2-base.yaml# -+ -+properties: -+ compatible: -+ contains: -+ const: operating-points-v2-adreno -+ -+patternProperties: -+ '^opp-[0-9]+$': -+ type: object -+ additionalProperties: false -+ -+ properties: -+ opp-hz: true -+ -+ opp-level: true -+ -+ opp-peak-kBps: true -+ -+ opp-supported-hw: true -+ -+ qcom,opp-acd-level: -+ description: | -+ A positive value representing the ACD (Adaptive Clock Distribution, -+ a fancy name for clk throttling during voltage droop) level associated -+ with this OPP node. This value is shared to a co-processor inside GPU -+ (called Graphics Management Unit a.k.a GMU) during wake up. It may not -+ be present for some OPPs and GMU will disable ACD while transitioning -+ to that OPP. This value encodes a voltage threshold, delay cycles & -+ calibration margins which are identified by characterization of the -+ SoC. So, it doesn't have any unit. This data is passed to GMU firmware -+ via 'HFI_H2F_MSG_ACD' packet. -+ $ref: /schemas/types.yaml#/definitions/uint32 -+ -+ required: -+ - opp-hz -+ - opp-level -+ -+required: -+ - compatible -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ -+ gpu_opp_table: opp-table { -+ compatible = "operating-points-v2-adreno", "operating-points-v2"; -+ -+ opp-687000000 { -+ opp-hz = /bits/ 64 <687000000>; -+ opp-level = ; -+ opp-peak-kBps = <8171875>; -+ qcom,opp-acd-level = <0x882e5ffd>; -+ }; -+ -+ opp-550000000 { -+ opp-hz = /bits/ 64 <550000000>; -+ opp-level = ; -+ opp-peak-kBps = <6074219>; -+ qcom,opp-acd-level = <0xc0285ffd>; -+ }; -+ -+ opp-390000000 { -+ opp-hz = /bits/ 64 <390000000>; -+ opp-level = ; -+ opp-peak-kBps = <3000000>; -+ qcom,opp-acd-level = <0xc0285ffd>; -+ }; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-level = ; -+ opp-peak-kBps = <2136719>; -+ /* Intentionally left out qcom,opp-acd-level property here */ -+ }; -+ -+ }; -diff --git a/MAINTAINERS b/MAINTAINERS -index c59316109e3f8feacf9628fd1065ed551c4250d5..2d055c8135d1e3dbbf29fe9a552ac0ee98a8a2a4 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -7512,6 +7512,7 @@ S: Maintained - B: https://gitlab.freedesktop.org/drm/msm/-/issues - T: git https://gitlab.freedesktop.org/drm/msm.git - F: Documentation/devicetree/bindings/display/msm/gpu.yaml -+F: Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml - F: drivers/gpu/drm/msm/adreno/ - F: drivers/gpu/drm/msm/msm_gpu.* - F: drivers/gpu/drm/msm/msm_gpu_devfreq.* --- -2.48.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 6/7] arm64: dts: qcom: x1e80100: Add ACD levels for GPU -From: Akhil P Oommen -Date: Sat, 03 May 2025 12:33:37 +0530 -Message-Id: <20250503-gpu-acd-v6-6-ab1b52866c64@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Update GPU node to include acd level values. - -Reviewed-by: Konrad Dybcio -Tested-by: Maya Matuszczyk -Tested-by: Anthony Ruhier -Signed-off-by: Akhil P Oommen ---- - arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++++++++++- - 1 file changed, 10 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi -index 4936fa5b98ff7a9a009e3106f4dba90131251971..a9c8cca1c6356393962cef856b3dbd9420733999 100644 ---- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi -+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi -@@ -3752,60 +3752,69 @@ zap-shader { - }; - - gpu_opp_table: opp-table { -- compatible = "operating-points-v2"; -+ compatible = "operating-points-v2-adreno", "operating-points-v2"; - - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-level = ; - opp-peak-kBps = <16500000>; -+ qcom,opp-acd-level = <0xa82a5ffd>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-level = ; - opp-peak-kBps = <14398438>; -+ qcom,opp-acd-level = <0xa82b5ffd>; - }; - - opp-925000000 { - opp-hz = /bits/ 64 <925000000>; - opp-level = ; - opp-peak-kBps = <14398438>; -+ qcom,opp-acd-level = <0xa82b5ffd>; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-level = ; - opp-peak-kBps = <12449219>; -+ qcom,opp-acd-level = <0xa82c5ffd>; - }; - - opp-744000000 { - opp-hz = /bits/ 64 <744000000>; - opp-level = ; - opp-peak-kBps = <10687500>; -+ qcom,opp-acd-level = <0x882e5ffd>; - }; - - opp-687000000 { - opp-hz = /bits/ 64 <687000000>; - opp-level = ; - opp-peak-kBps = <8171875>; -+ qcom,opp-acd-level = <0x882e5ffd>; - }; - - opp-550000000 { - opp-hz = /bits/ 64 <550000000>; - opp-level = ; - opp-peak-kBps = <6074219>; -+ qcom,opp-acd-level = <0xc0285ffd>; - }; - - opp-390000000 { - opp-hz = /bits/ 64 <390000000>; - opp-level = ; - opp-peak-kBps = <3000000>; -+ qcom,opp-acd-level = <0xc0285ffd>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-level = ; - opp-peak-kBps = <2136719>; -+ qcom,opp-acd-level = <0xc02b5ffd>; - }; - }; - }; --- -2.48.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v6 7/7] arm64: dts: qcom: x1e80100: Add OPPs up to Turbo L3 - for GPU -From: Akhil P Oommen -Date: Sat, 03 May 2025 12:33:38 +0530 -Message-Id: <20250503-gpu-acd-v6-7-ab1b52866c64@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Now that we have ACD support for GPU, add additional OPPs up to -Turbo L3 which are supported across all existing SKUs. - -Reviewed-by: Konrad Dybcio -Tested-by: Maya Matuszczyk -Tested-by: Anthony Ruhier -Signed-off-by: Akhil P Oommen ---- - arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 +++++++++++++++- - 1 file changed, 15 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi -index a9c8cca1c6356393962cef856b3dbd9420733999..8eddf0c9609871b8660587a22b008212a67604b3 100644 ---- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi -+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi -@@ -3754,10 +3754,24 @@ zap-shader { - gpu_opp_table: opp-table { - compatible = "operating-points-v2-adreno", "operating-points-v2"; - -+ opp-1250000000 { -+ opp-hz = /bits/ 64 <1250000000>; -+ opp-level = ; -+ opp-peak-kBps = <16500000>; -+ qcom,opp-acd-level = <0xa82a5ffd>; -+ }; -+ -+ opp-1175000000 { -+ opp-hz = /bits/ 64 <1175000000>; -+ opp-level = ; -+ opp-peak-kBps = <14398438>; -+ qcom,opp-acd-level = <0xa82a5ffd>; -+ }; -+ - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-level = ; -- opp-peak-kBps = <16500000>; -+ opp-peak-kBps = <14398438>; - qcom,opp-acd-level = <0xa82a5ffd>; - }; - --- -2.48.1 - diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0154-dts-qcom-sm8550-add-opp-acd-level.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0154-dts-qcom-sm8550-add-opp-acd-level.patch index 9962d0583f..bc65a3b522 100644 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0154-dts-qcom-sm8550-add-opp-acd-level.patch +++ b/projects/ROCKNIX/devices/SM8550/patches/linux/0154-dts-qcom-sm8550-add-opp-acd-level.patch @@ -1,17 +1,24 @@ -From 7fc99b626100ab4a156832d34b1cb03113301ef3 Mon Sep 17 00:00:00 2001 +From 337f73a668d262757f0c39fa73e78329f46c7361 Mon Sep 17 00:00:00 2001 From: Philippe Simons -Date: Wed, 18 Jun 2025 23:26:47 +0200 +Date: Sat, 2 Aug 2025 23:11:08 +0200 Subject: [PATCH] dts: qcom: sm8550: add opp-acd-level --- - arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) + arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi -index b418c9f62df7..4e61a233aac0 100644 +index 71a7e3b57ece..70f11d23d42b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi -@@ -2904,48 +2904,56 @@ opp-680000000 { +@@ -2462,54 +2462,62 @@ zap-shader { + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { +- compatible = "operating-points-v2"; ++ compatible = "operating-points-v2-adreno", "operating-points-v2"; + + opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; opp-peak-kBps = <16500000>; @@ -69,5 +76,5 @@ index b418c9f62df7..4e61a233aac0 100644 }; }; -- -2.49.0 +2.50.1 diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0155_drm-msm-a7xx-Call-CP_RESET_CONTEXT_STATE.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0155_drm-msm-a7xx-Call-CP_RESET_CONTEXT_STATE.patch deleted file mode 100644 index 7661a51b42..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0155_drm-msm-a7xx-Call-CP_RESET_CONTEXT_STATE.patch +++ /dev/null @@ -1,96 +0,0 @@ -From patchwork Tue May 20 22:28:05 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [1/2] drm/msm: Fix CP_RESET_CONTEXT_STATE bitfield names -From: Connor Abbott -X-Patchwork-Id: 654922 -Message-Id: <20250520-msm-reset-context-state-v1-1-b738c8b7d0b8@gmail.com> -To: Rob Clark , Sean Paul , - Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten -Cc: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, - Connor Abbott -Date: Tue, 20 May 2025 18:28:05 -0400 - -Based on kgsl. - -Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") -Signed-off-by: Connor Abbott ---- - drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml -index 55a35182858ccac3292849faaf12727257e053c7..2134731a86ba819215476d89c1e054328f901dd1 100644 ---- a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml -+++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml -@@ -2255,7 +2255,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - -- -+ -+ - - - - -From patchwork Tue May 20 22:28:06 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [2/2] drm/msm/a7xx: Call CP_RESET_CONTEXT_STATE -From: Connor Abbott -X-Patchwork-Id: 654924 -Message-Id: <20250520-msm-reset-context-state-v1-2-b738c8b7d0b8@gmail.com> -To: Rob Clark , Sean Paul , - Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten -Cc: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, - Connor Abbott -Date: Tue, 20 May 2025 18:28:06 -0400 - -Calling this packet is necessary when we switch contexts because there -are various pieces of state used by userspace to synchronize between BR -and BV that are persistent across submits and we need to make sure that -they are in a "safe" state when switching contexts. Otherwise a -userspace submission in one context could cause another context to -function incorrectly and hang, effectively a denial of service (although -without leaking data). This was missed during initial a7xx bringup. - -Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") -Signed-off-by: Connor Abbott ---- - drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -index 06465bc2d0b4b128cddfcfcaf1fe4252632b6777..f776e9ce43a7cdbb4ef769606ec851909b0c4cdd 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -@@ -130,6 +130,20 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, - OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); - OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); - OUT_RING(ring, submit->seqno - 1); -+ -+ OUT_PKT7(ring, CP_THREAD_CONTROL, 1); -+ OUT_RING(ring, CP_SET_THREAD_BOTH); -+ -+ /* Reset state used to synchronize BR and BV */ -+ OUT_PKT7(ring, CP_RESET_CONTEXT_STATE, 1); -+ OUT_RING(ring, -+ CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS | -+ CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE | -+ CP_RESET_CONTEXT_STATE_0_CLEAR_BV_BR_COUNTER | -+ CP_RESET_CONTEXT_STATE_0_RESET_GLOBAL_LOCAL_TS); -+ -+ OUT_PKT7(ring, CP_THREAD_CONTROL, 1); -+ OUT_RING(ring, CP_SET_THREAD_BR); - } - - if (!sysprof) { diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0156_iommu-arm-smmu-drm-msm-Fixes-for-stall-on-fault.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0156_iommu-arm-smmu-drm-msm-Fixes-for-stall-on-fault.patch deleted file mode 100644 index 85cbe1641c..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0156_iommu-arm-smmu-drm-msm-Fixes-for-stall-on-fault.patch +++ /dev/null @@ -1,954 +0,0 @@ -From patchwork Tue May 20 19:08:54 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v8,1/7] iommu/arm-smmu-qcom: Enable threaded IRQ for Adreno - SMMUv2/MMU500 -From: Connor Abbott -X-Patchwork-Id: 654886 -Message-Id: <20250520-msm-gpu-fault-fixes-next-v8-1-fce6ee218787@gmail.com> -To: Rob Clark , Will Deacon , - Robin Murphy , Joerg Roedel , - Sean Paul , Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten -Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, - Connor Abbott -Date: Tue, 20 May 2025 15:08:54 -0400 - -The recommended flow for stall-on-fault in SMMUv2 is the following: - -1. Resolve the fault. -2. Write to FSR to clear the fault bits. -3. Write RESUME to retry or fail the transaction. - -MMU500 is designed with this sequence in mind. For example, -experimentally we have seen on MMU500 that writing RESUME does not clear -FSR.SS unless the original fault is cleared in FSR, so 2 must come -before 3. FSR.SS is allowed to signal a fault (and does on MMU500) so -that if we try to do 2 -> 1 -> 3 (while exiting from the fault handler -after 2) we can get duplicate faults without hacks to disable -interrupts. - -However, resolving the fault typically requires lengthy operations that -can stall, like bringing in pages from disk. The only current user, -drm/msm, dumps GPU state before failing the transaction which indeed can -stall. Therefore, from now on we will require implementations that want -to use stall-on-fault to also enable threaded IRQs. Do that with the -Adreno MMU implementations. - -Signed-off-by: Connor Abbott ---- - drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -index 59d02687280e8d37b5e944619fcfe4ebd1bd6926..4d3b99babd3584ec971bef30cd533c35904fe7f5 100644 ---- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -@@ -585,6 +585,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = { - .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, - .write_sctlr = qcom_adreno_smmu_write_sctlr, - .tlb_sync = qcom_smmu_tlb_sync, -+ .context_fault_needs_threaded_irq = true, - }; - - static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = { -@@ -594,6 +595,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = { - .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, - .write_sctlr = qcom_adreno_smmu_write_sctlr, - .tlb_sync = qcom_smmu_tlb_sync, -+ .context_fault_needs_threaded_irq = true, - }; - - static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, - -From patchwork Tue May 20 19:08:55 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v8,2/7] iommu/arm-smmu: Move handing of RESUME to the context fault - handler -From: Connor Abbott -X-Patchwork-Id: 654887 -Message-Id: <20250520-msm-gpu-fault-fixes-next-v8-2-fce6ee218787@gmail.com> -To: Rob Clark , Will Deacon , - Robin Murphy , Joerg Roedel , - Sean Paul , Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten -Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, - Connor Abbott -Date: Tue, 20 May 2025 15:08:55 -0400 - -The upper layer fault handler is now expected to handle everything -required to retry the transaction or dump state related to it, since we -enable threaded IRQs. This means that we can take charge of writing -RESUME, making sure that we always write it after writing FSR as -recommended by the specification. - -The iommu handler should write -EAGAIN if a transaction needs to be -retried. This avoids tricky cross-tree changes in drm/msm, since it -never wants to retry the transaction and it already returns 0 from its -fault handler. Therefore it will continue to correctly terminate the -transaction without any changes required. - -devcoredumps from drm/msm will temporarily be broken until it is fixed -to collect devcoredumps inside its fault handler, but fixing that first -would actually be worse because MMU-500 ignores writes to RESUME unless -all fields of FSR (except SS of course) are clear and raises an -interrupt when only SS is asserted. Right now, things happen to work -most of the time if we collect a devcoredump, because RESUME is written -asynchronously in the fault worker after the fault handler clears FSR -and finishes, although there will be some spurious faults, but if this -is changed before this commit fixes the FSR/RESUME write order then SS -will never be cleared, the interrupt will never be cleared, and the -whole system will hang every time a fault happens. It will therefore -help bisectability if this commit goes first. - -I've changed the TBU path to also accept -EAGAIN and do the same thing, -while keeping the old -EBUSY behavior. Although the old path was broken -because you'd get a storm of interrupts due to returning IRQ_NONE that -would eventually result in the interrupt being disabled, and I think it -was dead code anyway, so it should eventually be deleted. Note that -drm/msm never uses TBU so this is untested. - -Signed-off-by: Connor Abbott ---- - drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 9 +++++++++ - drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 14 -------------- - drivers/iommu/arm/arm-smmu/arm-smmu.c | 6 ++++++ - 3 files changed, 15 insertions(+), 14 deletions(-) - -diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c -index d03b2239baad48680eb6c3201c85f924ec4a0e07..65e0ef6539fe70aabffa0c8fbe444c34c620d367 100644 ---- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c -+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c -@@ -406,6 +406,12 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev) - arm_smmu_print_context_fault_info(smmu, idx, &cfi); - - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr); -+ -+ if (cfi.fsr & ARM_SMMU_CB_FSR_SS) { -+ arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, -+ ret == -EAGAIN ? 0 : ARM_SMMU_RESUME_TERMINATE); -+ } -+ - return IRQ_HANDLED; - } - -@@ -416,6 +422,9 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev) - if (!tmp || tmp == -EBUSY) { - ret = IRQ_HANDLED; - resume = ARM_SMMU_RESUME_TERMINATE; -+ } else if (tmp == -EAGAIN) { -+ ret = IRQ_HANDLED; -+ resume = 0; - } else { - phys_addr_t phys_atos = qcom_smmu_verify_fault(smmu_domain, cfi.iova, cfi.fsr); - -diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -index 4d3b99babd3584ec971bef30cd533c35904fe7f5..c84730d33a30c013a37e603d10319fb83203eaa5 100644 ---- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -@@ -120,19 +120,6 @@ static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled) - qsmmu->stall_enabled &= ~BIT(cfg->cbndx); - } - --static void qcom_adreno_smmu_resume_translation(const void *cookie, bool terminate) --{ -- struct arm_smmu_domain *smmu_domain = (void *)cookie; -- struct arm_smmu_cfg *cfg = &smmu_domain->cfg; -- struct arm_smmu_device *smmu = smmu_domain->smmu; -- u32 reg = 0; -- -- if (terminate) -- reg |= ARM_SMMU_RESUME_TERMINATE; -- -- arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); --} -- - static void qcom_adreno_smmu_set_prr_bit(const void *cookie, bool set) - { - struct arm_smmu_domain *smmu_domain = (void *)cookie; -@@ -337,7 +324,6 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, - priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; - priv->get_fault_info = qcom_adreno_smmu_get_fault_info; - priv->set_stall = qcom_adreno_smmu_set_stall; -- priv->resume_translation = qcom_adreno_smmu_resume_translation; - priv->set_prr_bit = NULL; - priv->set_prr_addr = NULL; - -diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c -index 8f439c265a23f16bd11801a93dae12fd476ddfb2..8d95b14c7d5a4040bb8add56475e297beb16b162 100644 ---- a/drivers/iommu/arm/arm-smmu/arm-smmu.c -+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c -@@ -474,6 +474,12 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) - arm_smmu_print_context_fault_info(smmu, idx, &cfi); - - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr); -+ -+ if (cfi.fsr & ARM_SMMU_CB_FSR_SS) { -+ arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, -+ ret == -EAGAIN ? 0 : ARM_SMMU_RESUME_TERMINATE); -+ } -+ - return IRQ_HANDLED; - } - - -From patchwork Tue May 20 19:08:56 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v8,3/7] iommu/arm-smmu-qcom: Make set_stall work when the device is - on -From: Connor Abbott -X-Patchwork-Id: 654888 -Message-Id: <20250520-msm-gpu-fault-fixes-next-v8-3-fce6ee218787@gmail.com> -To: Rob Clark , Will Deacon , - Robin Murphy , Joerg Roedel , - Sean Paul , Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten -Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, - Connor Abbott -Date: Tue, 20 May 2025 15:08:56 -0400 - -Up until now we have only called the set_stall callback during -initialization when the device is off. But we will soon start calling it -to temporarily disable stall-on-fault when the device is on, so handle -that by checking if the device is on and writing SCTLR. - -Signed-off-by: Connor Abbott -Reviewed-by: Rob Clark ---- - drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 33 +++++++++++++++++++++++++++--- - include/linux/adreno-smmu-priv.h | 6 +++--- - 2 files changed, 33 insertions(+), 6 deletions(-) - -diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -index c84730d33a30c013a37e603d10319fb83203eaa5..f7430c131c21f40308df36fe25fe75d31558c817 100644 ---- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c -@@ -112,12 +112,39 @@ static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled) - { - struct arm_smmu_domain *smmu_domain = (void *)cookie; - struct arm_smmu_cfg *cfg = &smmu_domain->cfg; -- struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu); -+ struct arm_smmu_device *smmu = smmu_domain->smmu; -+ struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); -+ u32 mask = BIT(cfg->cbndx); -+ bool stall_changed = !!(qsmmu->stall_enabled & mask) != enabled; -+ unsigned long flags; - - if (enabled) -- qsmmu->stall_enabled |= BIT(cfg->cbndx); -+ qsmmu->stall_enabled |= mask; - else -- qsmmu->stall_enabled &= ~BIT(cfg->cbndx); -+ qsmmu->stall_enabled &= ~mask; -+ -+ /* -+ * If the device is on and we changed the setting, update the register. -+ * The spec pseudocode says that CFCFG is resampled after a fault, and -+ * we believe that no implementations cache it in the TLB, so it should -+ * be safe to change it without a TLB invalidation. -+ */ -+ if (stall_changed && pm_runtime_get_if_active(smmu->dev) > 0) { -+ spin_lock_irqsave(&smmu_domain->cb_lock, flags); -+ -+ u32 reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_SCTLR); -+ -+ if (enabled) -+ reg |= ARM_SMMU_SCTLR_CFCFG; -+ else -+ reg &= ~ARM_SMMU_SCTLR_CFCFG; -+ -+ arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_SCTLR, reg); -+ -+ spin_unlock_irqrestore(&smmu_domain->cb_lock, flags); -+ -+ pm_runtime_put_autosuspend(smmu->dev); -+ } - } - - static void qcom_adreno_smmu_set_prr_bit(const void *cookie, bool set) -diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h -index abec23c7744f49bea70f3352da9385304ed3702e..d83c9175828f792f1f43bcc8056102a43d822c96 100644 ---- a/include/linux/adreno-smmu-priv.h -+++ b/include/linux/adreno-smmu-priv.h -@@ -45,9 +45,9 @@ struct adreno_smmu_fault_info { - * TTBR0 translation is enabled with the specified cfg - * @get_fault_info: Called by the GPU fault handler to get information about - * the fault -- * @set_stall: Configure whether stall on fault (CFCFG) is enabled. Call -- * before set_ttbr0_cfg(). If stalling on fault is enabled, -- * the GPU driver must call resume_translation() -+ * @set_stall: Configure whether stall on fault (CFCFG) is enabled. If -+ * stalling on fault is enabled, the GPU driver must call -+ * resume_translation() - * @resume_translation: Resume translation after a fault - * - * @set_prr_bit: [optional] Configure the GPU's Partially Resident - -From patchwork Tue May 20 19:08:57 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v8,4/7] drm/msm: Don't use a worker to capture fault devcoredump -From: Connor Abbott -X-Patchwork-Id: 654889 -Message-Id: <20250520-msm-gpu-fault-fixes-next-v8-4-fce6ee218787@gmail.com> -To: Rob Clark , Will Deacon , - Robin Murphy , Joerg Roedel , - Sean Paul , Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten -Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, - Connor Abbott -Date: Tue, 20 May 2025 15:08:57 -0400 - -Now that we use a threaded IRQ, it should be safe to do this in the -fault handler. - -We can also remove fault_info from struct msm_gpu and just pass it -directly. - -Signed-off-by: Connor Abbott ---- - drivers/gpu/drm/msm/adreno/adreno_gpu.c | 22 ++++++++-------------- - drivers/gpu/drm/msm/msm_gpu.c | 20 +++++++++----------- - drivers/gpu/drm/msm/msm_gpu.h | 8 ++------ - 3 files changed, 19 insertions(+), 31 deletions(-) - -diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c -index 26db1f4b5fb90930bdbd2f17682bf47e35870936..4a6dc29ff7071940e440297f5fbbe4e2d06c3ffd 100644 ---- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c -+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c -@@ -257,14 +257,6 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, - const char *type = "UNKNOWN"; - bool do_devcoredump = info && !READ_ONCE(gpu->crashstate); - -- /* -- * If we aren't going to be resuming later from fault_worker, then do -- * it now. -- */ -- if (!do_devcoredump) { -- gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu); -- } -- - /* - * Print a default message if we couldn't get the data from the - * adreno-smmu-priv -@@ -291,16 +283,18 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, - scratch[0], scratch[1], scratch[2], scratch[3]); - - if (do_devcoredump) { -+ struct msm_gpu_fault_info fault_info = {}; -+ - /* Turn off the hangcheck timer to keep it from bothering us */ - timer_delete(&gpu->hangcheck_timer); - -- gpu->fault_info.ttbr0 = info->ttbr0; -- gpu->fault_info.iova = iova; -- gpu->fault_info.flags = flags; -- gpu->fault_info.type = type; -- gpu->fault_info.block = block; -+ fault_info.ttbr0 = info->ttbr0; -+ fault_info.iova = iova; -+ fault_info.flags = flags; -+ fault_info.type = type; -+ fault_info.block = block; - -- kthread_queue_work(gpu->worker, &gpu->fault_work); -+ msm_gpu_fault_crashstate_capture(gpu, &fault_info); - } - - return 0; -diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c -index c380d9d9f5af10b90ef733b05f5b0295c0445f38..457f019d507e954daeb609c313d37ee64fd492f9 100644 ---- a/drivers/gpu/drm/msm/msm_gpu.c -+++ b/drivers/gpu/drm/msm/msm_gpu.c -@@ -257,7 +257,8 @@ static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, - } - - static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, -- struct msm_gem_submit *submit, char *comm, char *cmd) -+ struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info, -+ char *comm, char *cmd) - { - struct msm_gpu_state *state; - -@@ -276,7 +277,8 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, - /* Fill in the additional crash state information */ - state->comm = kstrdup(comm, GFP_KERNEL); - state->cmd = kstrdup(cmd, GFP_KERNEL); -- state->fault_info = gpu->fault_info; -+ if (fault_info) -+ state->fault_info = *fault_info; - - if (submit) { - int i; -@@ -308,7 +310,8 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, - } - #else - static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, -- struct msm_gem_submit *submit, char *comm, char *cmd) -+ struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info, -+ char *comm, char *cmd) - { - } - #endif -@@ -405,7 +408,7 @@ static void recover_worker(struct kthread_work *work) - - /* Record the crash state */ - pm_runtime_get_sync(&gpu->pdev->dev); -- msm_gpu_crashstate_capture(gpu, submit, comm, cmd); -+ msm_gpu_crashstate_capture(gpu, submit, NULL, comm, cmd); - - kfree(cmd); - kfree(comm); -@@ -459,9 +462,8 @@ static void recover_worker(struct kthread_work *work) - msm_gpu_retire(gpu); - } - --static void fault_worker(struct kthread_work *work) -+void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info) - { -- struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work); - struct msm_gem_submit *submit; - struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); - char *comm = NULL, *cmd = NULL; -@@ -484,16 +486,13 @@ static void fault_worker(struct kthread_work *work) - - /* Record the crash state */ - pm_runtime_get_sync(&gpu->pdev->dev); -- msm_gpu_crashstate_capture(gpu, submit, comm, cmd); -+ msm_gpu_crashstate_capture(gpu, submit, fault_info, comm, cmd); - pm_runtime_put_sync(&gpu->pdev->dev); - - kfree(cmd); - kfree(comm); - - resume_smmu: -- memset(&gpu->fault_info, 0, sizeof(gpu->fault_info)); -- gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu); -- - mutex_unlock(&gpu->lock); - } - -@@ -882,7 +881,6 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, - init_waitqueue_head(&gpu->retire_event); - kthread_init_work(&gpu->retire_work, retire_worker); - kthread_init_work(&gpu->recover_work, recover_worker); -- kthread_init_work(&gpu->fault_work, fault_worker); - - priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD; - -diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h -index e25009150579c08f7b98d4461a75757d1093734a..bed0692f5adb30e50d0448640a329158d1ffe5e5 100644 ---- a/drivers/gpu/drm/msm/msm_gpu.h -+++ b/drivers/gpu/drm/msm/msm_gpu.h -@@ -253,12 +253,6 @@ struct msm_gpu { - #define DRM_MSM_HANGCHECK_PROGRESS_RETRIES 3 - struct timer_list hangcheck_timer; - -- /* Fault info for most recent iova fault: */ -- struct msm_gpu_fault_info fault_info; -- -- /* work for handling GPU ioval faults: */ -- struct kthread_work fault_work; -- - /* work for handling GPU recovery: */ - struct kthread_work recover_work; - -@@ -705,6 +699,8 @@ static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu) - mutex_unlock(&gpu->lock); - } - -+void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info); -+ - /* - * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can - * support expanded privileges - -From patchwork Tue May 20 19:08:58 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v8,5/7] drm/msm: Delete resume_translation() -From: Connor Abbott -X-Patchwork-Id: 654890 -Message-Id: <20250520-msm-gpu-fault-fixes-next-v8-5-fce6ee218787@gmail.com> -To: Rob Clark , Will Deacon , - Robin Murphy , Joerg Roedel , - Sean Paul , Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten -Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, - Connor Abbott -Date: Tue, 20 May 2025 15:08:58 -0400 - -Unused since the previous commit. - -Signed-off-by: Connor Abbott ---- - drivers/gpu/drm/msm/adreno/a2xx_gpummu.c | 5 ----- - drivers/gpu/drm/msm/msm_iommu.c | 13 ------------- - drivers/gpu/drm/msm/msm_mmu.h | 1 - - 3 files changed, 19 deletions(-) - -diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpummu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpummu.c -index 39641551eeb66d1441810c9691708ef448192578..4280f71e472a4130a62ba74e936870905ca260bb 100644 ---- a/drivers/gpu/drm/msm/adreno/a2xx_gpummu.c -+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpummu.c -@@ -71,10 +71,6 @@ static int a2xx_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len) - return 0; - } - --static void a2xx_gpummu_resume_translation(struct msm_mmu *mmu) --{ --} -- - static void a2xx_gpummu_destroy(struct msm_mmu *mmu) - { - struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu); -@@ -90,7 +86,6 @@ static const struct msm_mmu_funcs funcs = { - .map = a2xx_gpummu_map, - .unmap = a2xx_gpummu_unmap, - .destroy = a2xx_gpummu_destroy, -- .resume_translation = a2xx_gpummu_resume_translation, - }; - - struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu) -diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c -index fd73dcd3f30e75878364cb28dd26475c2ff80a85..aae885d048d0d2fd617d7b2a16833da25f5e84cc 100644 ---- a/drivers/gpu/drm/msm/msm_iommu.c -+++ b/drivers/gpu/drm/msm/msm_iommu.c -@@ -345,7 +345,6 @@ static int msm_gpu_fault_handler(struct iommu_domain *domain, struct device *dev - unsigned long iova, int flags, void *arg) - { - struct msm_iommu *iommu = arg; -- struct msm_mmu *mmu = &iommu->base; - struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev); - struct adreno_smmu_fault_info info, *ptr = NULL; - -@@ -359,9 +358,6 @@ static int msm_gpu_fault_handler(struct iommu_domain *domain, struct device *dev - - pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags); - -- if (mmu->funcs->resume_translation) -- mmu->funcs->resume_translation(mmu); -- - return 0; - } - -@@ -376,14 +372,6 @@ static int msm_disp_fault_handler(struct iommu_domain *domain, struct device *de - return -ENOSYS; - } - --static void msm_iommu_resume_translation(struct msm_mmu *mmu) --{ -- struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev); -- -- if (adreno_smmu->resume_translation) -- adreno_smmu->resume_translation(adreno_smmu->cookie, true); --} -- - static void msm_iommu_detach(struct msm_mmu *mmu) - { - struct msm_iommu *iommu = to_msm_iommu(mmu); -@@ -431,7 +419,6 @@ static const struct msm_mmu_funcs funcs = { - .map = msm_iommu_map, - .unmap = msm_iommu_unmap, - .destroy = msm_iommu_destroy, -- .resume_translation = msm_iommu_resume_translation, - }; - - struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks) -diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h -index daf91529e02b6c491d624e9de686173eeef86a9b..c3d17aae88b0a57b3c7d1df3351b39ec39bca60a 100644 ---- a/drivers/gpu/drm/msm/msm_mmu.h -+++ b/drivers/gpu/drm/msm/msm_mmu.h -@@ -15,7 +15,6 @@ struct msm_mmu_funcs { - size_t len, int prot); - int (*unmap)(struct msm_mmu *mmu, uint64_t iova, size_t len); - void (*destroy)(struct msm_mmu *mmu); -- void (*resume_translation)(struct msm_mmu *mmu); - }; - - enum msm_mmu_type { - -From patchwork Tue May 20 19:08:59 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v8,6/7] drm/msm: Temporarily disable stall-on-fault after a page - fault -From: Connor Abbott -X-Patchwork-Id: 654891 -Message-Id: <20250520-msm-gpu-fault-fixes-next-v8-6-fce6ee218787@gmail.com> -To: Rob Clark , Will Deacon , - Robin Murphy , Joerg Roedel , - Sean Paul , Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten -Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, - Connor Abbott -Date: Tue, 20 May 2025 15:08:59 -0400 - -When things go wrong, the GPU is capable of quickly generating millions -of faulting translation requests per second. When that happens, in the -stall-on-fault model each access will stall until it wins the race to -signal the fault and then the RESUME register is written. This slows -processing page faults to a crawl as the GPU can generate faults much -faster than the CPU can acknowledge them. It also means that all -available resources in the SMMU are saturated waiting for the stalled -transactions, so that other transactions such as transactions generated -by the GMU, which shares translation resources with the GPU, cannot -proceed. This causes a GMU watchdog timeout, which leads to a failed -reset because GX cannot collapse when there is a transaction pending and -a permanently hung GPU. - -On older platforms with qcom,smmu-v2, it seems that when one transaction -is stalled subsequent faulting transactions are terminated, which avoids -this problem, but the MMU-500 follows the spec here. - -To work around these problems, disable stall-on-fault as soon as we get a -page fault until a cooldown period after pagefaults stop. This allows -the GMU some guaranteed time to continue working. We only use -stall-on-fault to halt the GPU while we collect a devcoredump and we -always terminate the transaction afterward, so it's fine to miss some -subsequent page faults. We also keep it disabled so long as the current -devcoredump hasn't been deleted, because in that case we likely won't -capture another one if there's a fault. - -After this commit HFI messages still occasionally time out, because the -crashdump handler doesn't run fast enough to let the GMU resume, but the -driver seems to recover from it. This will probably go away after the -HFI timeout is increased. - -Signed-off-by: Connor Abbott -Reviewed-by: Rob Clark ---- - drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 ++ - drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++++ - drivers/gpu/drm/msm/adreno/adreno_gpu.c | 40 ++++++++++++++++++++++++++++++++- - drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 ++ - drivers/gpu/drm/msm/msm_debugfs.c | 32 ++++++++++++++++++++++++++ - drivers/gpu/drm/msm/msm_drv.c | 4 ++++ - drivers/gpu/drm/msm/msm_drv.h | 23 +++++++++++++++++++ - drivers/gpu/drm/msm/msm_iommu.c | 9 ++++++++ - drivers/gpu/drm/msm/msm_mmu.h | 1 + - 9 files changed, 116 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c -index 650e5bac225f372e819130b891f1d020b464f17f..60aef079623606bb1ae44ba59ac45e391595b0ba 100644 ---- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c -+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c -@@ -131,6 +131,8 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) - struct msm_ringbuffer *ring = submit->ring; - unsigned int i, ibs = 0; - -+ adreno_check_and_reenable_stall(adreno_gpu); -+ - if (IS_ENABLED(CONFIG_DRM_MSM_GPU_SUDO) && submit->in_rb) { - ring->cur_ctx_seqno = 0; - a5xx_submit_in_rb(gpu, submit); -diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -index 06465bc2d0b4b128cddfcfcaf1fe4252632b6777..afa4626d58f577d5d47f47b494b26953adcf230f 100644 ---- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -@@ -212,6 +212,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) - struct msm_ringbuffer *ring = submit->ring; - unsigned int i, ibs = 0; - -+ adreno_check_and_reenable_stall(adreno_gpu); -+ - a6xx_set_pagetable(a6xx_gpu, ring, submit); - - get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), -@@ -335,6 +337,8 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) - struct msm_ringbuffer *ring = submit->ring; - unsigned int i, ibs = 0; - -+ adreno_check_and_reenable_stall(adreno_gpu); -+ - /* - * Toggle concurrent binning for pagetable switch and set the thread to - * BR since only it can execute the pagetable switch packets. -diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c -index 4a6dc29ff7071940e440297f5fbbe4e2d06c3ffd..0f8211641c318f1b619e1a72bb77f064fb78397b 100644 ---- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c -+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c -@@ -246,16 +246,54 @@ u64 adreno_private_address_space_size(struct msm_gpu *gpu) - return SZ_4G; - } - -+void adreno_check_and_reenable_stall(struct adreno_gpu *adreno_gpu) -+{ -+ struct msm_gpu *gpu = &adreno_gpu->base; -+ struct msm_drm_private *priv = gpu->dev->dev_private; -+ unsigned long flags; -+ -+ /* -+ * Wait until the cooldown period has passed and we would actually -+ * collect a crashdump to re-enable stall-on-fault. -+ */ -+ spin_lock_irqsave(&priv->fault_stall_lock, flags); -+ if (!priv->stall_enabled && -+ ktime_after(ktime_get(), priv->stall_reenable_time) && -+ !READ_ONCE(gpu->crashstate)) { -+ priv->stall_enabled = true; -+ -+ gpu->aspace->mmu->funcs->set_stall(gpu->aspace->mmu, true); -+ } -+ spin_unlock_irqrestore(&priv->fault_stall_lock, flags); -+} -+ - #define ARM_SMMU_FSR_TF BIT(1) - #define ARM_SMMU_FSR_PF BIT(3) - #define ARM_SMMU_FSR_EF BIT(4) -+#define ARM_SMMU_FSR_SS BIT(30) - - int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, - struct adreno_smmu_fault_info *info, const char *block, - u32 scratch[4]) - { -+ struct msm_drm_private *priv = gpu->dev->dev_private; - const char *type = "UNKNOWN"; -- bool do_devcoredump = info && !READ_ONCE(gpu->crashstate); -+ bool do_devcoredump = info && (info->fsr & ARM_SMMU_FSR_SS) && -+ !READ_ONCE(gpu->crashstate); -+ unsigned long irq_flags; -+ -+ /* -+ * In case there is a subsequent storm of pagefaults, disable -+ * stall-on-fault for at least half a second. -+ */ -+ spin_lock_irqsave(&priv->fault_stall_lock, irq_flags); -+ if (priv->stall_enabled) { -+ priv->stall_enabled = false; -+ -+ gpu->aspace->mmu->funcs->set_stall(gpu->aspace->mmu, false); -+ } -+ priv->stall_reenable_time = ktime_add_ms(ktime_get(), 500); -+ spin_unlock_irqrestore(&priv->fault_stall_lock, irq_flags); - - /* - * Print a default message if we couldn't get the data from the -diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h -index 92caba3584da0400b44a903e465814af165d40a3..6116f03e3d39bb208c7fa34f203931c563e029f9 100644 ---- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h -+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h -@@ -634,6 +634,8 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, - struct adreno_smmu_fault_info *info, const char *block, - u32 scratch[4]); - -+void adreno_check_and_reenable_stall(struct adreno_gpu *gpu); -+ - int adreno_read_speedbin(struct device *dev, u32 *speedbin); - - /* -diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_debugfs.c -index 7ab607252d183f78b99c3a8b878c949ed5f99fec..6af72162cda4c8d4bc8dd4c6473cbc29817bb3c6 100644 ---- a/drivers/gpu/drm/msm/msm_debugfs.c -+++ b/drivers/gpu/drm/msm/msm_debugfs.c -@@ -208,6 +208,35 @@ DEFINE_DEBUGFS_ATTRIBUTE(shrink_fops, - shrink_get, shrink_set, - "0x%08llx\n"); - -+/* -+ * Return the number of microseconds to wait until stall-on-fault is -+ * re-enabled. If 0 then it is already enabled or will be re-enabled on the -+ * next submit (unless there's a leftover devcoredump). This is useful for -+ * kernel tests that intentionally produce a fault and check the devcoredump to -+ * wait until the cooldown period is over. -+ */ -+ -+static int -+stall_reenable_time_get(void *data, u64 *val) -+{ -+ struct msm_drm_private *priv = data; -+ unsigned long irq_flags; -+ -+ spin_lock_irqsave(&priv->fault_stall_lock, irq_flags); -+ -+ if (priv->stall_enabled) -+ *val = 0; -+ else -+ *val = max(ktime_us_delta(priv->stall_reenable_time, ktime_get()), 0); -+ -+ spin_unlock_irqrestore(&priv->fault_stall_lock, irq_flags); -+ -+ return 0; -+} -+ -+DEFINE_DEBUGFS_ATTRIBUTE(stall_reenable_time_fops, -+ stall_reenable_time_get, NULL, -+ "%lld\n"); - - static int msm_gem_show(struct seq_file *m, void *arg) - { -@@ -319,6 +348,9 @@ static void msm_debugfs_gpu_init(struct drm_minor *minor) - debugfs_create_bool("disable_err_irq", 0600, minor->debugfs_root, - &priv->disable_err_irq); - -+ debugfs_create_file("stall_reenable_time_us", 0400, minor->debugfs_root, -+ priv, &stall_reenable_time_fops); -+ - gpu_devfreq = debugfs_create_dir("devfreq", minor->debugfs_root); - - debugfs_create_bool("idle_clamp",0600, gpu_devfreq, -diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c -index c3588dc9e53764a27efda1901b094724cec8928a..04a4bde2d33b03ae8fb06b2134ee1910debd774a 100644 ---- a/drivers/gpu/drm/msm/msm_drv.c -+++ b/drivers/gpu/drm/msm/msm_drv.c -@@ -245,6 +245,10 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv) - drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock); - drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock); - -+ /* Initialize stall-on-fault */ -+ spin_lock_init(&priv->fault_stall_lock); -+ priv->stall_enabled = true; -+ - /* Teach lockdep about lock ordering wrt. shrinker: */ - fs_reclaim_acquire(GFP_KERNEL); - might_lock(&priv->lru.lock); -diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h -index a65077855201746c37ee742364b61116565f3794..c8afb1ea6040b1ac94ac95a785e6fc366c8dbfd1 100644 ---- a/drivers/gpu/drm/msm/msm_drv.h -+++ b/drivers/gpu/drm/msm/msm_drv.h -@@ -222,6 +222,29 @@ struct msm_drm_private { - * the sw hangcheck mechanism. - */ - bool disable_err_irq; -+ -+ /** -+ * @fault_stall_lock: -+ * -+ * Serialize changes to stall-on-fault state. -+ */ -+ spinlock_t fault_stall_lock; -+ -+ /** -+ * @fault_stall_reenable_time: -+ * -+ * If stall_enabled is false, when to reenable stall-on-fault. -+ * Protected by @fault_stall_lock. -+ */ -+ ktime_t stall_reenable_time; -+ -+ /** -+ * @stall_enabled: -+ * -+ * Whether stall-on-fault is currently enabled. Protected by -+ * @fault_stall_lock. -+ */ -+ bool stall_enabled; - }; - - const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier); -diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c -index aae885d048d0d2fd617d7b2a16833da25f5e84cc..739ce2c283a4613e74df4542ca3b68f180aa8335 100644 ---- a/drivers/gpu/drm/msm/msm_iommu.c -+++ b/drivers/gpu/drm/msm/msm_iommu.c -@@ -372,6 +372,14 @@ static int msm_disp_fault_handler(struct iommu_domain *domain, struct device *de - return -ENOSYS; - } - -+static void msm_iommu_set_stall(struct msm_mmu *mmu, bool enable) -+{ -+ struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev); -+ -+ if (adreno_smmu->set_stall) -+ adreno_smmu->set_stall(adreno_smmu->cookie, enable); -+} -+ - static void msm_iommu_detach(struct msm_mmu *mmu) - { - struct msm_iommu *iommu = to_msm_iommu(mmu); -@@ -419,6 +427,7 @@ static const struct msm_mmu_funcs funcs = { - .map = msm_iommu_map, - .unmap = msm_iommu_unmap, - .destroy = msm_iommu_destroy, -+ .set_stall = msm_iommu_set_stall, - }; - - struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks) -diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h -index c3d17aae88b0a57b3c7d1df3351b39ec39bca60a..0c694907140d00bae86eb20411aed45650367e74 100644 ---- a/drivers/gpu/drm/msm/msm_mmu.h -+++ b/drivers/gpu/drm/msm/msm_mmu.h -@@ -15,6 +15,7 @@ struct msm_mmu_funcs { - size_t len, int prot); - int (*unmap)(struct msm_mmu *mmu, uint64_t iova, size_t len); - void (*destroy)(struct msm_mmu *mmu); -+ void (*set_stall)(struct msm_mmu *mmu, bool enable); - }; - - enum msm_mmu_type { - -From patchwork Tue May 20 19:09:00 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v8,7/7] iommu/smmu-arm-qcom: Delete resume_translation() -From: Connor Abbott -X-Patchwork-Id: 654892 -Message-Id: <20250520-msm-gpu-fault-fixes-next-v8-7-fce6ee218787@gmail.com> -To: Rob Clark , Will Deacon , - Robin Murphy , Joerg Roedel , - Sean Paul , Konrad Dybcio , - Abhinav Kumar , - Dmitry Baryshkov , - Marijn Suijten -Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, - Connor Abbott -Date: Tue, 20 May 2025 15:09:00 -0400 - -Unused since "drm/msm: Delete resume_translation()". - -Signed-off-by: Connor Abbott ---- - include/linux/adreno-smmu-priv.h | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - -diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h -index d83c9175828f792f1f43bcc8056102a43d822c96..4106b6b372117119bbebe67896de18fc6286fb44 100644 ---- a/include/linux/adreno-smmu-priv.h -+++ b/include/linux/adreno-smmu-priv.h -@@ -46,9 +46,8 @@ struct adreno_smmu_fault_info { - * @get_fault_info: Called by the GPU fault handler to get information about - * the fault - * @set_stall: Configure whether stall on fault (CFCFG) is enabled. If -- * stalling on fault is enabled, the GPU driver must call -- * resume_translation() -- * @resume_translation: Resume translation after a fault -+ * stalling on fault is enabled, the GPU driver should return -+ * -EAGAIN from the fault handler if retrying is required. - * - * @set_prr_bit: [optional] Configure the GPU's Partially Resident - * Region (PRR) bit in the ACTLR register. -@@ -71,7 +70,6 @@ struct adreno_smmu_priv { - int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); - void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); - void (*set_stall)(const void *cookie, bool enabled); -- void (*resume_translation)(const void *cookie, bool terminate); - void (*set_prr_bit)(const void *cookie, bool set); - void (*set_prr_addr)(const void *cookie, phys_addr_t page_addr); - }; diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0157_drm-msm-Fix-a-couple-submit-leaks.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0157_drm-msm-Fix-a-couple-submit-leaks.patch deleted file mode 100644 index 9a53807203..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0157_drm-msm-Fix-a-couple-submit-leaks.patch +++ /dev/null @@ -1,113 +0,0 @@ -From patchwork Wed May 14 16:33:32 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [1/2] drm/msm: Fix a fence leak in submit error path -From: Rob Clark -X-Patchwork-Id: 653584 -Message-Id: <20250514163334.23544-2-robdclark@gmail.com> -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, - Rob Clark , Rob Clark , - Abhinav Kumar , - Dmitry Baryshkov , Sean Paul , - Marijn Suijten , - David Airlie , Simona Vetter , - linux-kernel@vger.kernel.org (open list) -Date: Wed, 14 May 2025 09:33:32 -0700 - -From: Rob Clark - -In error paths, we could unref the submit without calling -drm_sched_entity_push_job(), so msm_job_free() will never get -called. Since drm_sched_job_cleanup() will NULL out the -s_fence, we can use that to detect this case. - -Signed-off-by: Rob Clark ---- - drivers/gpu/drm/msm/msm_gem_submit.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c -index 3e9aa2cc38ef..b2aeaecaa39b 100644 ---- a/drivers/gpu/drm/msm/msm_gem_submit.c -+++ b/drivers/gpu/drm/msm/msm_gem_submit.c -@@ -85,6 +85,15 @@ void __msm_gem_submit_destroy(struct kref *kref) - container_of(kref, struct msm_gem_submit, ref); - unsigned i; - -+ /* -+ * In error paths, we could unref the submit without calling -+ * drm_sched_entity_push_job(), so msm_job_free() will never -+ * get called. Since drm_sched_job_cleanup() will NULL out -+ * s_fence, we can use that to detect this case. -+ */ -+ if (submit->base.s_fence) -+ drm_sched_job_cleanup(&submit->base); -+ - if (submit->fence_id) { - spin_lock(&submit->queue->idr_lock); - idr_remove(&submit->queue->fence_idr, submit->fence_id); - -From patchwork Wed May 14 16:33:33 2025 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [2/2] drm/msm: Fix another leak in the submit error path -From: Rob Clark -X-Patchwork-Id: 653583 -Message-Id: <20250514163334.23544-3-robdclark@gmail.com> -To: dri-devel@lists.freedesktop.org -Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, - Rob Clark , Rob Clark , - Abhinav Kumar , - Dmitry Baryshkov , Sean Paul , - Marijn Suijten , - David Airlie , Simona Vetter , - linux-kernel@vger.kernel.org (open list) -Date: Wed, 14 May 2025 09:33:33 -0700 - -From: Rob Clark - -put_unused_fd() doesn't free the installed file, if we've already done -fd_install(). So we need to also free the sync_file. - -Signed-off-by: Rob Clark ---- - drivers/gpu/drm/msm/msm_gem_submit.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c -index b2aeaecaa39b..d4f71bb54e84 100644 ---- a/drivers/gpu/drm/msm/msm_gem_submit.c -+++ b/drivers/gpu/drm/msm/msm_gem_submit.c -@@ -658,6 +658,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, - struct msm_ringbuffer *ring; - struct msm_submit_post_dep *post_deps = NULL; - struct drm_syncobj **syncobjs_to_reset = NULL; -+ struct sync_file *sync_file = NULL; - int out_fence_fd = -1; - unsigned i; - int ret; -@@ -867,7 +868,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, - } - - if (ret == 0 && args->flags & MSM_SUBMIT_FENCE_FD_OUT) { -- struct sync_file *sync_file = sync_file_create(submit->user_fence); -+ sync_file = sync_file_create(submit->user_fence); - if (!sync_file) { - ret = -ENOMEM; - } else { -@@ -901,8 +902,11 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, - out_unlock: - mutex_unlock(&queue->lock); - out_post_unlock: -- if (ret && (out_fence_fd >= 0)) -+ if (ret && (out_fence_fd >= 0)) { - put_unused_fd(out_fence_fd); -+ if (sync_file) -+ fput(sync_file->file); -+ } - - if (!IS_ERR_OR_NULL(submit)) { - msm_gem_submit_put(submit); diff --git a/projects/ROCKNIX/packages/linux/package.mk b/projects/ROCKNIX/packages/linux/package.mk index 50ac422f35..72e176652b 100644 --- a/projects/ROCKNIX/packages/linux/package.mk +++ b/projects/ROCKNIX/packages/linux/package.mk @@ -31,10 +31,10 @@ case ${DEVICE} in ;; *) case ${DEVICE} in - H700|SM8550) + H700) PKG_VERSION="6.15.2" ;; - SM8250) + SM8250|SM8550) PKG_VERSION="6.16" ;; *)