From 075d23681dc433ec7b0828c167dbdd56e462d703 Mon Sep 17 00:00:00 2001 From: Philippe Simons Date: Mon, 29 Sep 2025 21:39:34 +0200 Subject: [PATCH] sm8550/linux: bump to 6.17 --- ...-sm8550-Fix-disp_cc_mdss_mdp_clk_src.patch | 30 + ...aw88166--AYN-Odin2-Specific-modifica.patch | 10 +- ...m-msm-Expose-DRIVER_SYNCOBJ_TIMELINE.patch | 25 - ...m-msm-remove-DRIVER_SYNCOBJ_TIMELINE.patch | 24 + ...h_multiple_power_domains_in_cc_probe.patch | 2061 ----------------- ...m64--dts--qcom--Add-AYN-Odin2-Common.patch | 6 +- ...-dts--qcom--Add-AYANEO-Pocket-Common.patch | 6 +- ...latory_hints_during_mac_registration.patch | 252 -- ...g_for_regulatory_update_during_inter.patch | 95 - projects/ROCKNIX/packages/linux/package.mk | 4 +- 10 files changed, 62 insertions(+), 2451 deletions(-) create mode 100644 projects/ROCKNIX/devices/SM8550/patches/linux/0002-qcom-dispcc-sm8550-Fix-disp_cc_mdss_mdp_clk_src.patch delete mode 100644 projects/ROCKNIX/devices/SM8550/patches/linux/0070-Revert-drm-msm-Expose-DRIVER_SYNCOBJ_TIMELINE.patch create mode 100644 projects/ROCKNIX/devices/SM8550/patches/linux/0070-drm-msm-remove-DRIVER_SYNCOBJ_TIMELINE.patch delete mode 100644 projects/ROCKNIX/devices/SM8550/patches/linux/0121_v5_20250530_quic_jkona_clk_qcom_add_support_to_attach_multiple_power_domains_in_cc_probe.patch delete mode 100644 projects/ROCKNIX/devices/SM8550/patches/linux/0601-v2_20250617_aditya_kumar_singh_wifi_ath12k_handle_regulatory_hints_during_mac_registration.patch delete mode 100644 projects/ROCKNIX/devices/SM8550/patches/linux/0602-20250626_aditya_kumar_singh_wifi_ath12k_fix_timeout_while_waiting_for_regulatory_update_during_inter.patch diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0002-qcom-dispcc-sm8550-Fix-disp_cc_mdss_mdp_clk_src.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0002-qcom-dispcc-sm8550-Fix-disp_cc_mdss_mdp_clk_src.patch new file mode 100644 index 0000000000..5d3fd30141 --- /dev/null +++ b/projects/ROCKNIX/devices/SM8550/patches/linux/0002-qcom-dispcc-sm8550-Fix-disp_cc_mdss_mdp_clk_src.patch @@ -0,0 +1,30 @@ +From 2974d421bb6e5ab6994cd8923180a9c1da7ad035 Mon Sep 17 00:00:00 2001 +From: Philippe Simons +Date: Wed, 8 Oct 2025 21:06:15 +0200 +Subject: [PATCH] qcom: dispcc-sm8550: Fix disp_cc_mdss_mdp_clk_src + +Set CLK_OPS_PARENT_ENABLE to ensure the parent gets prepared and enabled +when switching to it, fixing an "rcg didn't update its configuration" +warning. + +Signed-off-by: Philippe Simons +--- + drivers/clk/qcom/dispcc-sm8550.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c +index f27140c649f5..5f75e1ccf38f 100644 +--- a/drivers/clk/qcom/dispcc-sm8550.c ++++ b/drivers/clk/qcom/dispcc-sm8550.c +@@ -622,7 +622,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { + .name = "disp_cc_mdss_mdp_clk_src", + .parent_data = disp_cc_parent_data_8, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), +- .flags = CLK_SET_RATE_PARENT, ++ .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_shared_ops, + }, + }; +-- +2.51.0 + diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0047_ASoC--codecs--aw88166--AYN-Odin2-Specific-modifica.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0047_ASoC--codecs--aw88166--AYN-Odin2-Specific-modifica.patch index d70d478b80..4ac53ab1a0 100644 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0047_ASoC--codecs--aw88166--AYN-Odin2-Specific-modifica.patch +++ b/projects/ROCKNIX/devices/SM8550/patches/linux/0047_ASoC--codecs--aw88166--AYN-Odin2-Specific-modifica.patch @@ -71,7 +71,7 @@ index 9f52d838e262..e2636bde62fc 100644 return -EINVAL; } -@@ -1372,286 +1392,97 @@ static int aw88166_stop(struct aw_device *aw_dev) +@@ -1372,284 +1392,97 @@ static int aw88166_stop(struct aw_device *aw_dev) return 0; } @@ -193,7 +193,7 @@ index 9f52d838e262..e2636bde62fc 100644 { - struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); - struct aw88166 *aw88166 = snd_soc_component_get_drvdata(codec); -- char *prof_name, *name; +- char *prof_name; - int count, ret; - - uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; @@ -210,17 +210,15 @@ index 9f52d838e262..e2636bde62fc 100644 - if (uinfo->value.enumerated.item >= count) - uinfo->value.enumerated.item = count - 1; - -- name = uinfo->value.enumerated.name; - count = uinfo->value.enumerated.item; - - ret = aw88166_dev_get_prof_name(aw88166->aw_pa, count, &prof_name); - if (ret) { -- strscpy(uinfo->value.enumerated.name, "null", -- strlen("null") + 1); +- strscpy(uinfo->value.enumerated.name, "null"); - return 0; - } - -- strscpy(name, prof_name, sizeof(uinfo->value.enumerated.name)); +- strscpy(uinfo->value.enumerated.name, prof_name); + dev_dbg(dai->dev, "fmt=0x%x", fmt); return 0; diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0070-Revert-drm-msm-Expose-DRIVER_SYNCOBJ_TIMELINE.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0070-Revert-drm-msm-Expose-DRIVER_SYNCOBJ_TIMELINE.patch deleted file mode 100644 index 728fea9d5c..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0070-Revert-drm-msm-Expose-DRIVER_SYNCOBJ_TIMELINE.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 1c0e9e729c3deff54553ea72f128aceee42ae98a Mon Sep 17 00:00:00 2001 -From: Philippe Simons -Date: Sat, 7 Jun 2025 14:08:02 +0200 -Subject: [PATCH] Revert "drm/msm: Expose DRIVER_SYNCOBJ_TIMELINE" - -This reverts commit 977e4ef27591a41cab8ff43cf390d32936d4b7f5. ---- - drivers/gpu/drm/msm/msm_drv.c | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c -index c3588dc9e537..ff7a7a9f7b0d 100644 ---- a/drivers/gpu/drm/msm/msm_drv.c -+++ b/drivers/gpu/drm/msm/msm_drv.c -@@ -894,7 +894,6 @@ static const struct drm_driver msm_driver = { - DRIVER_RENDER | - DRIVER_ATOMIC | - DRIVER_MODESET | -- DRIVER_SYNCOBJ_TIMELINE | - DRIVER_SYNCOBJ, - .open = msm_open, - .postclose = msm_postclose, --- -2.49.0 - diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0070-drm-msm-remove-DRIVER_SYNCOBJ_TIMELINE.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0070-drm-msm-remove-DRIVER_SYNCOBJ_TIMELINE.patch new file mode 100644 index 0000000000..d498ad1158 --- /dev/null +++ b/projects/ROCKNIX/devices/SM8550/patches/linux/0070-drm-msm-remove-DRIVER_SYNCOBJ_TIMELINE.patch @@ -0,0 +1,24 @@ +From 32910f8a66978507a49ddb14abd28c7718d881aa Mon Sep 17 00:00:00 2001 +From: Philippe Simons +Date: Mon, 29 Sep 2025 20:10:53 +0200 +Subject: [PATCH] drm:msm remove DRIVER_SYNCOBJ_TIMELINE + +--- + drivers/gpu/drm/msm/msm_drv.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c +index 9dcc7a596a11..98ca2feece5b 100644 +--- a/drivers/gpu/drm/msm/msm_drv.c ++++ b/drivers/gpu/drm/msm/msm_drv.c +@@ -821,7 +821,6 @@ static const struct file_operations fops = { + DRIVER_GEM_GPUVA | \ + DRIVER_RENDER | \ + DRIVER_SYNCOBJ | \ +- DRIVER_SYNCOBJ_TIMELINE | \ + 0 ) + + #define DRIVER_FEATURES_KMS ( \ +-- +2.51.0 + diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0121_v5_20250530_quic_jkona_clk_qcom_add_support_to_attach_multiple_power_domains_in_cc_probe.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0121_v5_20250530_quic_jkona_clk_qcom_add_support_to_attach_multiple_power_domains_in_cc_probe.patch deleted file mode 100644 index 67d9e54df4..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0121_v5_20250530_quic_jkona_clk_qcom_add_support_to_attach_multiple_power_domains_in_cc_probe.patch +++ /dev/null @@ -1,2061 +0,0 @@ -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 1/18] dt-bindings: clock: qcom,sm8450-videocc: Add MXC - power domain -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:46 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -To configure the video PLLs and enable the video GDSCs on SM8450, -SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along -with MMCX. Therefore, update the videocc bindings to include -the MXC power domain on these platforms. - -Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") -Signed-off-by: Jagadeesh Kona -Reviewed-by: Bryan O'Donoghue -Acked-by: Rob Herring (Arm) ---- - .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 18 ++++++++++++------ - 1 file changed, 12 insertions(+), 6 deletions(-) - -diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml -index 62714fa54db82491a7a108f7f18a253d737f8d61..0d99178332cb99d3f02f50605e19b9b26e3ec807 100644 ---- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml -+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml -@@ -32,14 +32,18 @@ properties: - - description: Video AHB clock from GCC - - power-domains: -- maxItems: 1 - description: -- MMCX power domain. -+ Power domains required for the clock controller to operate -+ items: -+ - description: MMCX power domain -+ - description: MXC power domain - - required-opps: -- maxItems: 1 - description: -- A phandle to an OPP node describing required MMCX performance point. -+ OPP nodes that describe required performance points on power domains -+ items: -+ - description: MMCX performance point -+ - description: MXC performance point - - required: - - compatible -@@ -72,8 +76,10 @@ examples: - reg = <0x0aaf0000 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_VIDEO_AHB_CLK>; -- power-domains = <&rpmhpd RPMHPD_MMCX>; -- required-opps = <&rpmhpd_opp_low_svs>; -+ power-domains = <&rpmhpd RPMHPD_MMCX>, -+ <&rpmhpd RPMHPD_MXC>; -+ required-opps = <&rpmhpd_opp_low_svs>, -+ <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 2/18] dt-bindings: clock: qcom,sm8450-camcc: Allow to - specify two power domains -From: Vladimir Zapolskiy -Date: Fri, 30 May 2025 18:50:47 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-2-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -To configure the camera PLLs and enable the camera GDSCs on SM8450, SM8475, -SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. -Therefore, update the camcc bindings to include the MXC power domain on -these platforms. - -Fixes: 9cbc64745fc6 ("dt-bindings: clock: qcom: Add SM8550 camera clock controller") -Signed-off-by: Vladimir Zapolskiy -Reviewed-by: Krzysztof Kozlowski -Reviewed-by: Bryan O'Donoghue -Signed-off-by: Jagadeesh Kona ---- - .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 18 ++++++++++++------ - 1 file changed, 12 insertions(+), 6 deletions(-) - -diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml -index 9e79f8fec437b9aecb5103092f6ff2ad1cd42626..3fded6aa712fc1920c4c4a923545901ba804c42f 100644 ---- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml -+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml -@@ -37,14 +37,18 @@ properties: - - description: Sleep clock source - - power-domains: -- maxItems: 1 - description: -- A phandle and PM domain specifier for the MMCX power domain. -+ Power domains required for the clock controller to operate -+ items: -+ - description: MMCX power domain -+ - description: MXC power domain - - required-opps: -- maxItems: 1 - description: -- A phandle to an OPP node describing required MMCX performance point. -+ OPP nodes that describe required performance points on power domains -+ items: -+ - description: MMCX performance point -+ - description: MXC performance point - - reg: - maxItems: 1 -@@ -82,8 +86,10 @@ examples: - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; -- power-domains = <&rpmhpd RPMHPD_MMCX>; -- required-opps = <&rpmhpd_opp_low_svs>; -+ power-domains = <&rpmhpd RPMHPD_MMCX>, -+ <&rpmhpd RPMHPD_MXC>; -+ required-opps = <&rpmhpd_opp_low_svs>, -+ <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 3/18] dt-bindings: clock: qcom,sm8450-camcc: Move - sc8280xp camcc to sa8775p camcc -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:48 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-3-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -SC8280XP camcc only requires the MMCX power domain, unlike SM8450 camcc -which now supports both MMCX and MXC power domains. Hence move SC8280XP -camcc from SM8450 to SA8775P camcc, to have single power domain support. - -SA8775P camcc doesn't support required-opps property currently but SC8280XP -camcc need that property, so add required-opps based on SC8280XP camcc -conditional check in SA8775P camcc bindings. - -Reviewed-by: Bryan O'Donoghue -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Jagadeesh Kona -Reviewed-by: Krzysztof Kozlowski ---- - .../devicetree/bindings/clock/qcom,sa8775p-camcc.yaml | 15 +++++++++++++++ - .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 2 -- - 2 files changed, 15 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml -index 81623f59d11d73839e5c551411a52427e2f28415..f42ccb6627a387ee0d0238ebd1fcd1cdf64c5676 100644 ---- a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml -+++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml -@@ -17,12 +17,14 @@ description: | - See also: - include/dt-bindings/clock/qcom,qcs8300-camcc.h - include/dt-bindings/clock/qcom,sa8775p-camcc.h -+ include/dt-bindings/clock/qcom,sc8280xp-camcc.h - - properties: - compatible: - enum: - - qcom,qcs8300-camcc - - qcom,sa8775p-camcc -+ - qcom,sc8280xp-camcc - - clocks: - items: -@@ -35,6 +37,11 @@ properties: - maxItems: 1 - description: MMCX power domain - -+ required-opps: -+ description: -+ OPP node describing required MMCX performance point. -+ maxItems: 1 -+ - required: - - compatible - - clocks -@@ -43,6 +50,14 @@ required: - - allOf: - - $ref: qcom,gcc.yaml# -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: qcom,sc8280xp-camcc -+ then: -+ required: -+ - required-opps - - unevaluatedProperties: false - -diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml -index 3fded6aa712fc1920c4c4a923545901ba804c42f..c1e06f39431e68a3cd2f6c2dba84be2a3c143bb1 100644 ---- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml -+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml -@@ -15,7 +15,6 @@ description: | - domains on SM8450. - - See also: -- include/dt-bindings/clock/qcom,sc8280xp-camcc.h - include/dt-bindings/clock/qcom,sm8450-camcc.h - include/dt-bindings/clock/qcom,sm8550-camcc.h - include/dt-bindings/clock/qcom,sm8650-camcc.h -@@ -23,7 +22,6 @@ description: | - properties: - compatible: - enum: -- - qcom,sc8280xp-camcc - - qcom,sm8450-camcc - - qcom,sm8475-camcc - - qcom,sm8550-camcc --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 4/18] clk: qcom: clk-alpha-pll: Add support for common - PLL configuration function -From: Taniya Das -Date: Fri, 30 May 2025 18:50:49 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-4-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -To properly configure the PLLs on recent chipsets, it often requires more -than one power domain to be kept ON. The support to enable multiple power -domains is being added in qcom_cc_really_probe() and PLLs should be -configured post all the required power domains are enabled. - -Hence integrate PLL configuration into clk_alpha_pll structure and add -support for qcom_clk_alpha_pll_configure() function which can be called -from qcom_cc_really_probe() to configure the clock controller PLLs after -all required power domains are enabled. - -Signed-off-by: Taniya Das -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Jagadeesh Kona ---- - drivers/clk/qcom/clk-alpha-pll.c | 57 ++++++++++++++++++++++++++++++++++++++++ - drivers/clk/qcom/clk-alpha-pll.h | 3 +++ - 2 files changed, 60 insertions(+) - -diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c -index cec0afea8e446010f0d4140d4ef63121706dde47..d8e1cd1263317814da2d0414600988de4b87c56f 100644 ---- a/drivers/clk/qcom/clk-alpha-pll.c -+++ b/drivers/clk/qcom/clk-alpha-pll.c -@@ -63,6 +63,8 @@ - #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) - #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) - -+#define GET_PLL_TYPE(pll) (((pll)->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS) -+ - const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { - [CLK_ALPHA_PLL_TYPE_DEFAULT] = { - [PLL_OFF_L_VAL] = 0x04, -@@ -2960,3 +2962,58 @@ const struct clk_ops clk_alpha_pll_regera_ops = { - .set_rate = clk_zonda_pll_set_rate, - }; - EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops); -+ -+void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap) -+{ -+ const struct clk_init_data *init = pll->clkr.hw.init; -+ -+ switch (GET_PLL_TYPE(pll)) { -+ case CLK_ALPHA_PLL_TYPE_LUCID_OLE: -+ clk_lucid_ole_pll_configure(pll, regmap, pll->config); -+ break; -+ case CLK_ALPHA_PLL_TYPE_LUCID_EVO: -+ clk_lucid_evo_pll_configure(pll, regmap, pll->config); -+ break; -+ case CLK_ALPHA_PLL_TYPE_TAYCAN_ELU: -+ clk_taycan_elu_pll_configure(pll, regmap, pll->config); -+ break; -+ case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO: -+ clk_rivian_evo_pll_configure(pll, regmap, pll->config); -+ break; -+ case CLK_ALPHA_PLL_TYPE_TRION: -+ clk_trion_pll_configure(pll, regmap, pll->config); -+ break; -+ case CLK_ALPHA_PLL_TYPE_HUAYRA_2290: -+ clk_huayra_2290_pll_configure(pll, regmap, pll->config); -+ break; -+ case CLK_ALPHA_PLL_TYPE_FABIA: -+ clk_fabia_pll_configure(pll, regmap, pll->config); -+ break; -+ case CLK_ALPHA_PLL_TYPE_AGERA: -+ clk_agera_pll_configure(pll, regmap, pll->config); -+ break; -+ case CLK_ALPHA_PLL_TYPE_PONGO_ELU: -+ clk_pongo_elu_pll_configure(pll, regmap, pll->config); -+ break; -+ case CLK_ALPHA_PLL_TYPE_ZONDA: -+ case CLK_ALPHA_PLL_TYPE_ZONDA_OLE: -+ clk_zonda_pll_configure(pll, regmap, pll->config); -+ break; -+ case CLK_ALPHA_PLL_TYPE_STROMER: -+ case CLK_ALPHA_PLL_TYPE_STROMER_PLUS: -+ clk_stromer_pll_configure(pll, regmap, pll->config); -+ break; -+ case CLK_ALPHA_PLL_TYPE_DEFAULT: -+ case CLK_ALPHA_PLL_TYPE_DEFAULT_EVO: -+ case CLK_ALPHA_PLL_TYPE_HUAYRA: -+ case CLK_ALPHA_PLL_TYPE_HUAYRA_APSS: -+ case CLK_ALPHA_PLL_TYPE_BRAMMO: -+ case CLK_ALPHA_PLL_TYPE_BRAMMO_EVO: -+ clk_alpha_pll_configure(pll, regmap, pll->config); -+ break; -+ default: -+ WARN(1, "%s: invalid pll type\n", init->name); -+ break; -+ } -+} -+EXPORT_SYMBOL_GPL(qcom_clk_alpha_pll_configure); -diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h -index 79aca8525262211ae5295245427d4540abf1e09a..7f35aaa7a35d88411beb11fd2be5d5dd5bfbe066 100644 ---- a/drivers/clk/qcom/clk-alpha-pll.h -+++ b/drivers/clk/qcom/clk-alpha-pll.h -@@ -81,6 +81,7 @@ struct pll_vco { - * struct clk_alpha_pll - phase locked loop (PLL) - * @offset: base address of registers - * @regs: alpha pll register map (see @clk_alpha_pll_regs) -+ * @config: array of pll settings - * @vco_table: array of VCO settings - * @num_vco: number of VCO settings in @vco_table - * @flags: bitmask to indicate features supported by the hardware -@@ -90,6 +91,7 @@ struct clk_alpha_pll { - u32 offset; - const u8 *regs; - -+ const struct alpha_pll_config *config; - const struct pll_vco *vco_table; - size_t num_vco; - #define SUPPORTS_OFFLINE_REQ BIT(0) -@@ -237,5 +239,6 @@ void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, - const struct alpha_pll_config *config); - void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, - const struct alpha_pll_config *config); -+void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap); - - #endif --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 5/18] clk: qcom: common: Handle runtime power management - in qcom_cc_really_probe -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:50 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-5-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Add support for runtime power management in qcom_cc_really_probe() to -commonize it across all the clock controllers. The runtime power management -is not required for all clock controllers, hence handle the rpm based on -use_rpm flag in clock controller descriptor. - -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Bryan O'Donoghue -Signed-off-by: Jagadeesh Kona ---- - drivers/clk/qcom/common.c | 37 ++++++++++++++++++++++++++++--------- - drivers/clk/qcom/common.h | 1 + - 2 files changed, 29 insertions(+), 9 deletions(-) - -diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c -index 9e3380fd718198c9fe63d7361615a91c3ecb3d60..9cbf1c5296dad3ee5477a2f5a445488707663b9d 100644 ---- a/drivers/clk/qcom/common.c -+++ b/drivers/clk/qcom/common.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -304,6 +305,16 @@ int qcom_cc_really_probe(struct device *dev, - if (ret < 0 && ret != -EEXIST) - return ret; - -+ if (desc->use_rpm) { -+ ret = devm_pm_runtime_enable(dev); -+ if (ret) -+ return ret; -+ -+ ret = pm_runtime_resume_and_get(dev); -+ if (ret) -+ return ret; -+ } -+ - reset = &cc->reset; - reset->rcdev.of_node = dev->of_node; - reset->rcdev.ops = &qcom_reset_ops; -@@ -314,23 +325,25 @@ int qcom_cc_really_probe(struct device *dev, - - ret = devm_reset_controller_register(dev, &reset->rcdev); - if (ret) -- return ret; -+ goto put_rpm; - - if (desc->gdscs && desc->num_gdscs) { - scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); -- if (!scd) -- return -ENOMEM; -+ if (!scd) { -+ ret = -ENOMEM; -+ goto put_rpm; -+ } - scd->dev = dev; - scd->scs = desc->gdscs; - scd->num = desc->num_gdscs; - scd->pd_list = cc->pd_list; - ret = gdsc_register(scd, &reset->rcdev, regmap); - if (ret) -- return ret; -+ goto put_rpm; - ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister, - scd); - if (ret) -- return ret; -+ goto put_rpm; - } - - cc->rclks = rclks; -@@ -341,7 +354,7 @@ int qcom_cc_really_probe(struct device *dev, - for (i = 0; i < num_clk_hws; i++) { - ret = devm_clk_hw_register(dev, clk_hws[i]); - if (ret) -- return ret; -+ goto put_rpm; - } - - for (i = 0; i < num_clks; i++) { -@@ -350,14 +363,20 @@ int qcom_cc_really_probe(struct device *dev, - - ret = devm_clk_register_regmap(dev, rclks[i]); - if (ret) -- return ret; -+ goto put_rpm; - } - - ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc); - if (ret) -- return ret; -+ goto put_rpm; -+ -+ ret = qcom_cc_icc_register(dev, desc); -+ -+put_rpm: -+ if (desc->use_rpm) -+ pm_runtime_put(dev); - -- return qcom_cc_icc_register(dev, desc); -+ return ret; - } - EXPORT_SYMBOL_GPL(qcom_cc_really_probe); - -diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h -index 7ace5d7f5836aa81431153ba92d8f14f2ffe8147..9c10bc8c197cd7dfa25ccd245763ad6acb081523 100644 ---- a/drivers/clk/qcom/common.h -+++ b/drivers/clk/qcom/common.h -@@ -38,6 +38,7 @@ struct qcom_cc_desc { - const struct qcom_icc_hws_data *icc_hws; - size_t num_icc_hws; - unsigned int icc_first_node_id; -+ bool use_rpm; - }; - - /** --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 6/18] clk: qcom: common: Add support to configure clk - regs in qcom_cc_really_probe -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:51 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-6-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Add support to configure PLLS and clk registers in qcom_cc_really_probe(). -This ensures all required power domains are enabled and kept ON by runtime -PM code in qcom_cc_really_probe() before configuring the PLLS or clock -registers. - -Add support for qcom_cc_driver_data struct to maintain the clock -controllers PLLs and CBCRs data, and a pointer of it can be stored in -clock descriptor structure. If any clock controller driver requires to -program some additional misc register settings, it can register the -clk_regs_configure() callback in the driver data. - -Reviewed-by: Bryan O'Donoghue -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Jagadeesh Kona -Reviewed-by: Konrad Dybcio ---- - drivers/clk/qcom/common.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ - drivers/clk/qcom/common.h | 9 +++++++++ - 2 files changed, 53 insertions(+) - -diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c -index 9cbf1c5296dad3ee5477a2f5a445488707663b9d..b3838d885db25f183979576e5c685c07dc6a7049 100644 ---- a/drivers/clk/qcom/common.c -+++ b/drivers/clk/qcom/common.c -@@ -14,6 +14,8 @@ - #include - - #include "common.h" -+#include "clk-alpha-pll.h" -+#include "clk-branch.h" - #include "clk-rcg.h" - #include "clk-regmap.h" - #include "reset.h" -@@ -285,6 +287,40 @@ static int qcom_cc_icc_register(struct device *dev, - desc->num_icc_hws, icd); - } - -+static int qcom_cc_clk_pll_configure(const struct qcom_cc_driver_data *data, -+ struct regmap *regmap) -+{ -+ const struct clk_init_data *init; -+ struct clk_alpha_pll *pll; -+ int i; -+ -+ for (i = 0; i < data->num_alpha_plls; i++) { -+ pll = data->alpha_plls[i]; -+ init = pll->clkr.hw.init; -+ -+ if (!pll->config || !pll->regs) { -+ pr_err("%s: missing pll config or regs\n", init->name); -+ return -EINVAL; -+ } -+ -+ qcom_clk_alpha_pll_configure(pll, regmap); -+ } -+ -+ return 0; -+} -+ -+static void qcom_cc_clk_regs_configure(struct device *dev, const struct qcom_cc_driver_data *data, -+ struct regmap *regmap) -+{ -+ int i; -+ -+ for (i = 0; i < data->num_clk_cbcrs; i++) -+ qcom_branch_set_clk_en(regmap, data->clk_cbcrs[i]); -+ -+ if (data->clk_regs_configure) -+ data->clk_regs_configure(dev, regmap); -+} -+ - int qcom_cc_really_probe(struct device *dev, - const struct qcom_cc_desc *desc, struct regmap *regmap) - { -@@ -315,6 +351,14 @@ int qcom_cc_really_probe(struct device *dev, - return ret; - } - -+ if (desc->driver_data) { -+ ret = qcom_cc_clk_pll_configure(desc->driver_data, regmap); -+ if (ret) -+ goto put_rpm; -+ -+ qcom_cc_clk_regs_configure(dev, desc->driver_data, regmap); -+ } -+ - reset = &cc->reset; - reset->rcdev.of_node = dev->of_node; - reset->rcdev.ops = &qcom_reset_ops; -diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h -index 9c10bc8c197cd7dfa25ccd245763ad6acb081523..0f4b2d40c65cf94de694226f63ca30f4181d0ce5 100644 ---- a/drivers/clk/qcom/common.h -+++ b/drivers/clk/qcom/common.h -@@ -25,6 +25,14 @@ struct qcom_icc_hws_data { - int clk_id; - }; - -+struct qcom_cc_driver_data { -+ struct clk_alpha_pll **alpha_plls; -+ size_t num_alpha_plls; -+ u32 *clk_cbcrs; -+ size_t num_clk_cbcrs; -+ void (*clk_regs_configure)(struct device *dev, struct regmap *regmap); -+}; -+ - struct qcom_cc_desc { - const struct regmap_config *config; - struct clk_regmap **clks; -@@ -39,6 +47,7 @@ struct qcom_cc_desc { - size_t num_icc_hws; - unsigned int icc_first_node_id; - bool use_rpm; -+ struct qcom_cc_driver_data *driver_data; - }; - - /** --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 7/18] clk: qcom: videocc-sm8450: Move PLL & clk - configuration to really probe -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:52 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-7-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Video PLLs on SM8450/SM8475 require both MMCX and MXC rails to be kept ON -to configure the PLLs properly. Hence move runtime power management, PLL -configuration and enable critical clocks to qcom_cc_really_probe() which -ensures all required power domains are in enabled state before configuring -the PLLs or enabling the clocks. - -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Konrad Dybcio -Signed-off-by: Jagadeesh Kona ---- - drivers/clk/qcom/videocc-sm8450.c | 58 +++++++++++++++++---------------------- - 1 file changed, 25 insertions(+), 33 deletions(-) - -diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c -index 2e11dcffb6646d47b298c27ef68635a465dd728e..d53182f001262324d8f54b0c6a5e73541eb32190 100644 ---- a/drivers/clk/qcom/videocc-sm8450.c -+++ b/drivers/clk/qcom/videocc-sm8450.c -@@ -7,7 +7,6 @@ - #include - #include - #include --#include - #include - - #include -@@ -63,6 +62,7 @@ static const struct alpha_pll_config sm8475_video_cc_pll0_config = { - - static struct clk_alpha_pll video_cc_pll0 = { - .offset = 0x0, -+ .config = &video_cc_pll0_config, - .vco_table = lucid_evo_vco, - .num_vco = ARRAY_SIZE(lucid_evo_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], -@@ -106,6 +106,7 @@ static const struct alpha_pll_config sm8475_video_cc_pll1_config = { - - static struct clk_alpha_pll video_cc_pll1 = { - .offset = 0x1000, -+ .config = &video_cc_pll1_config, - .vco_table = lucid_evo_vco, - .num_vco = ARRAY_SIZE(lucid_evo_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], -@@ -407,6 +408,17 @@ static const struct qcom_reset_map video_cc_sm8450_resets[] = { - [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x808c, .bit = 2, .udelay = 1000 }, - }; - -+static struct clk_alpha_pll *video_cc_sm8450_plls[] = { -+ &video_cc_pll0, -+ &video_cc_pll1, -+}; -+ -+static u32 video_cc_sm8450_critical_cbcrs[] = { -+ 0x80e4, /* VIDEO_CC_AHB_CLK */ -+ 0x8114, /* VIDEO_CC_XO_CLK */ -+ 0x8130, /* VIDEO_CC_SLEEP_CLK */ -+}; -+ - static const struct regmap_config video_cc_sm8450_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, -@@ -415,6 +427,13 @@ static const struct regmap_config video_cc_sm8450_regmap_config = { - .fast_io = true, - }; - -+static struct qcom_cc_driver_data video_cc_sm8450_driver_data = { -+ .alpha_plls = video_cc_sm8450_plls, -+ .num_alpha_plls = ARRAY_SIZE(video_cc_sm8450_plls), -+ .clk_cbcrs = video_cc_sm8450_critical_cbcrs, -+ .num_clk_cbcrs = ARRAY_SIZE(video_cc_sm8450_critical_cbcrs), -+}; -+ - static const struct qcom_cc_desc video_cc_sm8450_desc = { - .config = &video_cc_sm8450_regmap_config, - .clks = video_cc_sm8450_clocks, -@@ -423,6 +442,8 @@ static const struct qcom_cc_desc video_cc_sm8450_desc = { - .num_resets = ARRAY_SIZE(video_cc_sm8450_resets), - .gdscs = video_cc_sm8450_gdscs, - .num_gdscs = ARRAY_SIZE(video_cc_sm8450_gdscs), -+ .use_rpm = true, -+ .driver_data = &video_cc_sm8450_driver_data, - }; - - static const struct of_device_id video_cc_sm8450_match_table[] = { -@@ -434,23 +455,6 @@ MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table); - - static int video_cc_sm8450_probe(struct platform_device *pdev) - { -- struct regmap *regmap; -- int ret; -- -- ret = devm_pm_runtime_enable(&pdev->dev); -- if (ret) -- return ret; -- -- ret = pm_runtime_resume_and_get(&pdev->dev); -- if (ret) -- return ret; -- -- regmap = qcom_cc_map(pdev, &video_cc_sm8450_desc); -- if (IS_ERR(regmap)) { -- pm_runtime_put(&pdev->dev); -- return PTR_ERR(regmap); -- } -- - if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) { - /* Update VideoCC PLL0 */ - video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; -@@ -458,23 +462,11 @@ static int video_cc_sm8450_probe(struct platform_device *pdev) - /* Update VideoCC PLL1 */ - video_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; - -- clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &sm8475_video_cc_pll0_config); -- clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &sm8475_video_cc_pll1_config); -- } else { -- clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); -- clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); -+ video_cc_pll0.config = &sm8475_video_cc_pll0_config; -+ video_cc_pll1.config = &sm8475_video_cc_pll1_config; - } - -- /* Keep some clocks always-on */ -- qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */ -- qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */ -- qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */ -- -- ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8450_desc, regmap); -- -- pm_runtime_put(&pdev->dev); -- -- return ret; -+ return qcom_cc_probe(pdev, &video_cc_sm8450_desc); - } - - static struct platform_driver video_cc_sm8450_driver = { --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 8/18] clk: qcom: videocc-sm8550: Move PLL & clk - configuration to really probe -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:53 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-8-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Video PLLs on SM8550/SM8650 require both MMCX and MXC rails to be kept ON -to configure the PLLs properly. Hence move runtime power management, PLL -configuration and enable critical clocks to qcom_cc_really_probe() which -ensures all required power domains are in enabled state before configuring -the PLLs or enabling the clocks. - -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Jagadeesh Kona -Reviewed-by: Bryan O'Donoghue -Reviewed-by: Konrad Dybcio ---- - drivers/clk/qcom/videocc-sm8550.c | 66 +++++++++++++++++++-------------------- - 1 file changed, 33 insertions(+), 33 deletions(-) - -diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c -index fcfe0cade6d0a95e749aabbc2af1174e5a70f0db..3e5891b43ee404edc6c99bbf8f2583cb44df9e37 100644 ---- a/drivers/clk/qcom/videocc-sm8550.c -+++ b/drivers/clk/qcom/videocc-sm8550.c -@@ -7,7 +7,6 @@ - #include - #include - #include --#include - #include - - #include -@@ -51,6 +50,7 @@ static struct alpha_pll_config video_cc_pll0_config = { - - static struct clk_alpha_pll video_cc_pll0 = { - .offset = 0x0, -+ .config = &video_cc_pll0_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -82,6 +82,7 @@ static struct alpha_pll_config video_cc_pll1_config = { - - static struct clk_alpha_pll video_cc_pll1 = { - .offset = 0x1000, -+ .config = &video_cc_pll1_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -511,6 +512,23 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = { - [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 }, - }; - -+static struct clk_alpha_pll *video_cc_sm8550_plls[] = { -+ &video_cc_pll0, -+ &video_cc_pll1, -+}; -+ -+static u32 video_cc_sm8550_critical_cbcrs[] = { -+ 0x80f4, /* VIDEO_CC_AHB_CLK */ -+ 0x8124, /* VIDEO_CC_XO_CLK */ -+ 0x8140, /* VIDEO_CC_SLEEP_CLK */ -+}; -+ -+static u32 video_cc_sm8650_critical_cbcrs[] = { -+ 0x80f4, /* VIDEO_CC_AHB_CLK */ -+ 0x8124, /* VIDEO_CC_XO_CLK */ -+ 0x8150, /* VIDEO_CC_SLEEP_CLK */ -+}; -+ - static const struct regmap_config video_cc_sm8550_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, -@@ -519,6 +537,13 @@ static const struct regmap_config video_cc_sm8550_regmap_config = { - .fast_io = true, - }; - -+static struct qcom_cc_driver_data video_cc_sm8550_driver_data = { -+ .alpha_plls = video_cc_sm8550_plls, -+ .num_alpha_plls = ARRAY_SIZE(video_cc_sm8550_plls), -+ .clk_cbcrs = video_cc_sm8550_critical_cbcrs, -+ .num_clk_cbcrs = ARRAY_SIZE(video_cc_sm8550_critical_cbcrs), -+}; -+ - static const struct qcom_cc_desc video_cc_sm8550_desc = { - .config = &video_cc_sm8550_regmap_config, - .clks = video_cc_sm8550_clocks, -@@ -527,6 +552,8 @@ static const struct qcom_cc_desc video_cc_sm8550_desc = { - .num_resets = ARRAY_SIZE(video_cc_sm8550_resets), - .gdscs = video_cc_sm8550_gdscs, - .num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs), -+ .use_rpm = true, -+ .driver_data = &video_cc_sm8550_driver_data, - }; - - static const struct of_device_id video_cc_sm8550_match_table[] = { -@@ -538,26 +565,7 @@ MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table); - - static int video_cc_sm8550_probe(struct platform_device *pdev) - { -- struct regmap *regmap; -- int ret; -- u32 sleep_clk_offset = 0x8140; -- -- ret = devm_pm_runtime_enable(&pdev->dev); -- if (ret) -- return ret; -- -- ret = pm_runtime_resume_and_get(&pdev->dev); -- if (ret) -- return ret; -- -- regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc); -- if (IS_ERR(regmap)) { -- pm_runtime_put(&pdev->dev); -- return PTR_ERR(regmap); -- } -- - if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) { -- sleep_clk_offset = 0x8150; - video_cc_pll0_config.l = 0x1e; - video_cc_pll0_config.alpha = 0xa000; - video_cc_pll1_config.l = 0x2b; -@@ -569,21 +577,13 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) - video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr; - video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr; - video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr; -- } -- -- clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); -- clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); - -- /* Keep some clocks always-on */ -- qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */ -- qcom_branch_set_clk_en(regmap, sleep_clk_offset); /* VIDEO_CC_SLEEP_CLK */ -- qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */ -- -- ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8550_desc, regmap); -- -- pm_runtime_put(&pdev->dev); -+ video_cc_sm8550_driver_data.clk_cbcrs = video_cc_sm8650_critical_cbcrs; -+ video_cc_sm8550_driver_data.num_clk_cbcrs = -+ ARRAY_SIZE(video_cc_sm8650_critical_cbcrs); -+ } - -- return ret; -+ return qcom_cc_probe(pdev, &video_cc_sm8550_desc); - } - - static struct platform_driver video_cc_sm8550_driver = { --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 9/18] clk: qcom: camcc-sm8450: Move PLL & clk - configuration to really probe -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:54 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-9-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Camera PLLs on SM8450/SM8475 require both MMCX and MXC rails to be -kept ON to configure the PLLs properly. Hence move runtime power -management, PLL configuration and enable critical clocks to -qcom_cc_really_probe() which ensures all required power domains are in -enabled state before configuring the PLLs or enabling the clocks. - -This change also removes the modelling for cam_cc_gdsc_clk and keeps it -always ON from probe since using CLK_IS_CRITICAL will prevent the clock -controller associated power domains from collapsing due to clock framework -invoking clk_pm_runtime_get() during prepare. - -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Konrad Dybcio -Signed-off-by: Jagadeesh Kona -Reviewed-by: Bryan O'Donoghue ---- - drivers/clk/qcom/camcc-sm8450.c | 89 ++++++++++++++++++++--------------------- - 1 file changed, 44 insertions(+), 45 deletions(-) - -diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c -index 08982737e4901c0703e19f8dd2d302e24748210c..4dd8be8cc9881c890d2e7c3a12f12816a9ab47dc 100644 ---- a/drivers/clk/qcom/camcc-sm8450.c -+++ b/drivers/clk/qcom/camcc-sm8450.c -@@ -86,6 +86,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll0_config = { - - static struct clk_alpha_pll cam_cc_pll0 = { - .offset = 0x0, -+ .config = &cam_cc_pll0_config, - .vco_table = lucid_evo_vco, - .num_vco = ARRAY_SIZE(lucid_evo_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], -@@ -191,6 +192,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll1_config = { - - static struct clk_alpha_pll cam_cc_pll1 = { - .offset = 0x1000, -+ .config = &cam_cc_pll1_config, - .vco_table = lucid_evo_vco, - .num_vco = ARRAY_SIZE(lucid_evo_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], -@@ -257,6 +259,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll2_config = { - - static struct clk_alpha_pll cam_cc_pll2 = { - .offset = 0x2000, -+ .config = &cam_cc_pll2_config, - .vco_table = rivian_evo_vco, - .num_vco = ARRAY_SIZE(rivian_evo_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], -@@ -296,6 +299,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll3_config = { - - static struct clk_alpha_pll cam_cc_pll3 = { - .offset = 0x3000, -+ .config = &cam_cc_pll3_config, - .vco_table = lucid_evo_vco, - .num_vco = ARRAY_SIZE(lucid_evo_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], -@@ -368,6 +372,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll4_config = { - - static struct clk_alpha_pll cam_cc_pll4 = { - .offset = 0x4000, -+ .config = &cam_cc_pll4_config, - .vco_table = lucid_evo_vco, - .num_vco = ARRAY_SIZE(lucid_evo_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], -@@ -440,6 +445,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll5_config = { - - static struct clk_alpha_pll cam_cc_pll5 = { - .offset = 0x5000, -+ .config = &cam_cc_pll5_config, - .vco_table = lucid_evo_vco, - .num_vco = ARRAY_SIZE(lucid_evo_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], -@@ -512,6 +518,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll6_config = { - - static struct clk_alpha_pll cam_cc_pll6 = { - .offset = 0x6000, -+ .config = &cam_cc_pll6_config, - .vco_table = lucid_evo_vco, - .num_vco = ARRAY_SIZE(lucid_evo_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], -@@ -584,6 +591,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll7_config = { - - static struct clk_alpha_pll cam_cc_pll7 = { - .offset = 0x7000, -+ .config = &cam_cc_pll7_config, - .vco_table = lucid_evo_vco, - .num_vco = ARRAY_SIZE(lucid_evo_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], -@@ -656,6 +664,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll8_config = { - - static struct clk_alpha_pll cam_cc_pll8 = { - .offset = 0x8000, -+ .config = &cam_cc_pll8_config, - .vco_table = lucid_evo_vco, - .num_vco = ARRAY_SIZE(lucid_evo_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], -@@ -1476,24 +1485,6 @@ static struct clk_rcg2 cam_cc_xo_clk_src = { - }, - }; - --static struct clk_branch cam_cc_gdsc_clk = { -- .halt_reg = 0x1320c, -- .halt_check = BRANCH_HALT, -- .clkr = { -- .enable_reg = 0x1320c, -- .enable_mask = BIT(0), -- .hw.init = &(const struct clk_init_data) { -- .name = "cam_cc_gdsc_clk", -- .parent_hws = (const struct clk_hw*[]) { -- &cam_cc_xo_clk_src.clkr.hw, -- }, -- .num_parents = 1, -- .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, -- .ops = &clk_branch2_ops, -- }, -- }, --}; -- - static struct clk_branch cam_cc_bps_ahb_clk = { - .halt_reg = 0x1004c, - .halt_check = BRANCH_HALT, -@@ -2819,7 +2810,6 @@ static struct clk_regmap *cam_cc_sm8450_clocks[] = { - [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, - [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, - [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, -- [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr, - [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, - [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, - [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, -@@ -2913,6 +2903,22 @@ static const struct qcom_reset_map cam_cc_sm8450_resets[] = { - [CAM_CC_SFE_1_BCR] = { 0x13094 }, - }; - -+static struct clk_alpha_pll *cam_cc_sm8450_plls[] = { -+ &cam_cc_pll0, -+ &cam_cc_pll1, -+ &cam_cc_pll2, -+ &cam_cc_pll3, -+ &cam_cc_pll4, -+ &cam_cc_pll5, -+ &cam_cc_pll6, -+ &cam_cc_pll7, -+ &cam_cc_pll8, -+}; -+ -+static u32 cam_cc_sm8450_critical_cbcrs[] = { -+ 0x1320c, /* CAM_CC_GDSC_CLK */ -+}; -+ - static const struct regmap_config cam_cc_sm8450_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, -@@ -3021,6 +3027,13 @@ static struct gdsc *cam_cc_sm8450_gdscs[] = { - [TITAN_TOP_GDSC] = &titan_top_gdsc, - }; - -+static struct qcom_cc_driver_data cam_cc_sm8450_driver_data = { -+ .alpha_plls = cam_cc_sm8450_plls, -+ .num_alpha_plls = ARRAY_SIZE(cam_cc_sm8450_plls), -+ .clk_cbcrs = cam_cc_sm8450_critical_cbcrs, -+ .num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8450_critical_cbcrs), -+}; -+ - static const struct qcom_cc_desc cam_cc_sm8450_desc = { - .config = &cam_cc_sm8450_regmap_config, - .clks = cam_cc_sm8450_clocks, -@@ -3029,6 +3042,8 @@ static const struct qcom_cc_desc cam_cc_sm8450_desc = { - .num_resets = ARRAY_SIZE(cam_cc_sm8450_resets), - .gdscs = cam_cc_sm8450_gdscs, - .num_gdscs = ARRAY_SIZE(cam_cc_sm8450_gdscs), -+ .use_rpm = true, -+ .driver_data = &cam_cc_sm8450_driver_data, - }; - - static const struct of_device_id cam_cc_sm8450_match_table[] = { -@@ -3040,12 +3055,6 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table); - - static int cam_cc_sm8450_probe(struct platform_device *pdev) - { -- struct regmap *regmap; -- -- regmap = qcom_cc_map(pdev, &cam_cc_sm8450_desc); -- if (IS_ERR(regmap)) -- return PTR_ERR(regmap); -- - if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) { - /* Update CAMCC PLL0 */ - cam_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; -@@ -3092,28 +3101,18 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev) - cam_cc_pll8_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; - cam_cc_pll8_out_even.clkr.hw.init = &sm8475_cam_cc_pll8_out_even_init; - -- clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &sm8475_cam_cc_pll0_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &sm8475_cam_cc_pll1_config); -- clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &sm8475_cam_cc_pll2_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &sm8475_cam_cc_pll3_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &sm8475_cam_cc_pll4_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &sm8475_cam_cc_pll5_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &sm8475_cam_cc_pll6_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &sm8475_cam_cc_pll7_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &sm8475_cam_cc_pll8_config); -- } else { -- clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); -- clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); -- clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); -- clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); -- clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); -- clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); -- clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); -- clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); -- clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); -+ cam_cc_pll0.config = &sm8475_cam_cc_pll0_config; -+ cam_cc_pll1.config = &sm8475_cam_cc_pll1_config; -+ cam_cc_pll2.config = &sm8475_cam_cc_pll2_config; -+ cam_cc_pll3.config = &sm8475_cam_cc_pll3_config; -+ cam_cc_pll4.config = &sm8475_cam_cc_pll4_config; -+ cam_cc_pll5.config = &sm8475_cam_cc_pll5_config; -+ cam_cc_pll6.config = &sm8475_cam_cc_pll6_config; -+ cam_cc_pll7.config = &sm8475_cam_cc_pll7_config; -+ cam_cc_pll8.config = &sm8475_cam_cc_pll8_config; - } - -- return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap); -+ return qcom_cc_probe(pdev, &cam_cc_sm8450_desc); - } - - static struct platform_driver cam_cc_sm8450_driver = { --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 10/18] clk: qcom: camcc-sm8550: Move PLL & clk - configuration to really probe -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:55 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-10-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Camera PLLs on SM8550 require both MMCX and MXC rails to be kept ON to -configure the PLLs properly. Hence move runtime power management, PLL -configuration and enabling critical clocks to qcom_cc_really_probe() which -ensures all required power domains are in enabled state before configuring -the PLLs or enabling the clocks. - -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Konrad Dybcio -Signed-off-by: Jagadeesh Kona -Reviewed-by: Bryan O'Donoghue ---- - drivers/clk/qcom/camcc-sm8550.c | 85 +++++++++++++++++++++-------------------- - 1 file changed, 44 insertions(+), 41 deletions(-) - -diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c -index 871155783c798fd9245d735642272eae2a2d3465..63aed9e4c362d523093409f74ef4e57f292ddf90 100644 ---- a/drivers/clk/qcom/camcc-sm8550.c -+++ b/drivers/clk/qcom/camcc-sm8550.c -@@ -7,7 +7,6 @@ - #include - #include - #include --#include - #include - - #include -@@ -74,6 +73,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = { - - static struct clk_alpha_pll cam_cc_pll0 = { - .offset = 0x0, -+ .config = &cam_cc_pll0_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -151,6 +151,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = { - - static struct clk_alpha_pll cam_cc_pll1 = { - .offset = 0x1000, -+ .config = &cam_cc_pll1_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -201,6 +202,7 @@ static const struct alpha_pll_config cam_cc_pll2_config = { - - static struct clk_alpha_pll cam_cc_pll2 = { - .offset = 0x2000, -+ .config = &cam_cc_pll2_config, - .vco_table = rivian_ole_vco, - .num_vco = ARRAY_SIZE(rivian_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], -@@ -232,6 +234,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = { - - static struct clk_alpha_pll cam_cc_pll3 = { - .offset = 0x3000, -+ .config = &cam_cc_pll3_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -286,6 +289,7 @@ static const struct alpha_pll_config cam_cc_pll4_config = { - - static struct clk_alpha_pll cam_cc_pll4 = { - .offset = 0x4000, -+ .config = &cam_cc_pll4_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -340,6 +344,7 @@ static const struct alpha_pll_config cam_cc_pll5_config = { - - static struct clk_alpha_pll cam_cc_pll5 = { - .offset = 0x5000, -+ .config = &cam_cc_pll5_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -394,6 +399,7 @@ static const struct alpha_pll_config cam_cc_pll6_config = { - - static struct clk_alpha_pll cam_cc_pll6 = { - .offset = 0x6000, -+ .config = &cam_cc_pll6_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -448,6 +454,7 @@ static const struct alpha_pll_config cam_cc_pll7_config = { - - static struct clk_alpha_pll cam_cc_pll7 = { - .offset = 0x7000, -+ .config = &cam_cc_pll7_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -502,6 +509,7 @@ static const struct alpha_pll_config cam_cc_pll8_config = { - - static struct clk_alpha_pll cam_cc_pll8 = { - .offset = 0x8000, -+ .config = &cam_cc_pll8_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -556,6 +564,7 @@ static const struct alpha_pll_config cam_cc_pll9_config = { - - static struct clk_alpha_pll cam_cc_pll9 = { - .offset = 0x9000, -+ .config = &cam_cc_pll9_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -610,6 +619,7 @@ static const struct alpha_pll_config cam_cc_pll10_config = { - - static struct clk_alpha_pll cam_cc_pll10 = { - .offset = 0xa000, -+ .config = &cam_cc_pll10_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -664,6 +674,7 @@ static const struct alpha_pll_config cam_cc_pll11_config = { - - static struct clk_alpha_pll cam_cc_pll11 = { - .offset = 0xb000, -+ .config = &cam_cc_pll11_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -718,6 +729,7 @@ static const struct alpha_pll_config cam_cc_pll12_config = { - - static struct clk_alpha_pll cam_cc_pll12 = { - .offset = 0xc000, -+ .config = &cam_cc_pll12_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -3479,6 +3491,27 @@ static const struct qcom_reset_map cam_cc_sm8550_resets[] = { - [CAM_CC_SFE_1_BCR] = { 0x133dc }, - }; - -+static struct clk_alpha_pll *cam_cc_sm8550_plls[] = { -+ &cam_cc_pll0, -+ &cam_cc_pll1, -+ &cam_cc_pll2, -+ &cam_cc_pll3, -+ &cam_cc_pll4, -+ &cam_cc_pll5, -+ &cam_cc_pll6, -+ &cam_cc_pll7, -+ &cam_cc_pll8, -+ &cam_cc_pll9, -+ &cam_cc_pll10, -+ &cam_cc_pll11, -+ &cam_cc_pll12, -+}; -+ -+static u32 cam_cc_sm8550_critical_cbcrs[] = { -+ 0x1419c, /* CAM_CC_GDSC_CLK */ -+ 0x142cc, /* CAM_CC_SLEEP_CLK */ -+}; -+ - static const struct regmap_config cam_cc_sm8550_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, -@@ -3487,6 +3520,13 @@ static const struct regmap_config cam_cc_sm8550_regmap_config = { - .fast_io = true, - }; - -+static struct qcom_cc_driver_data cam_cc_sm8550_driver_data = { -+ .alpha_plls = cam_cc_sm8550_plls, -+ .num_alpha_plls = ARRAY_SIZE(cam_cc_sm8550_plls), -+ .clk_cbcrs = cam_cc_sm8550_critical_cbcrs, -+ .num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8550_critical_cbcrs), -+}; -+ - static const struct qcom_cc_desc cam_cc_sm8550_desc = { - .config = &cam_cc_sm8550_regmap_config, - .clks = cam_cc_sm8550_clocks, -@@ -3495,6 +3535,8 @@ static const struct qcom_cc_desc cam_cc_sm8550_desc = { - .num_resets = ARRAY_SIZE(cam_cc_sm8550_resets), - .gdscs = cam_cc_sm8550_gdscs, - .num_gdscs = ARRAY_SIZE(cam_cc_sm8550_gdscs), -+ .use_rpm = true, -+ .driver_data = &cam_cc_sm8550_driver_data, - }; - - static const struct of_device_id cam_cc_sm8550_match_table[] = { -@@ -3505,46 +3547,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8550_match_table); - - static int cam_cc_sm8550_probe(struct platform_device *pdev) - { -- struct regmap *regmap; -- int ret; -- -- ret = devm_pm_runtime_enable(&pdev->dev); -- if (ret) -- return ret; -- -- ret = pm_runtime_resume_and_get(&pdev->dev); -- if (ret) -- return ret; -- -- regmap = qcom_cc_map(pdev, &cam_cc_sm8550_desc); -- if (IS_ERR(regmap)) { -- pm_runtime_put(&pdev->dev); -- return PTR_ERR(regmap); -- } -- -- clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); -- clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config); -- -- /* Keep some clocks always-on */ -- qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */ -- qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */ -- -- ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8550_desc, regmap); -- -- pm_runtime_put(&pdev->dev); -- -- return ret; -+ return qcom_cc_probe(pdev, &cam_cc_sm8550_desc); - } - - static struct platform_driver cam_cc_sm8550_driver = { --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 11/18] clk: qcom: camcc-sm8650: Move PLL & clk - configuration to really probe -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:56 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-11-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Camera PLLs on SM8650 require both MMCX and MXC rails to be kept ON -to configure the PLLs properly. Hence move runtime power management, -PLL configuration and enabling critical clocks to qcom_cc_really_probe() -which ensures all required power domains are in enabled state before -configuring the PLLs or enabling the clocks. - -Reviewed-by: Konrad Dybcio -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Jagadeesh Kona -Reviewed-by: Bryan O'Donoghue ---- - drivers/clk/qcom/camcc-sm8650.c | 83 +++++++++++++++++++++-------------------- - 1 file changed, 42 insertions(+), 41 deletions(-) - -diff --git a/drivers/clk/qcom/camcc-sm8650.c b/drivers/clk/qcom/camcc-sm8650.c -index 0ccd6de8ba78a3493f8f853a4330d2676b5743d4..8b388904f56fc3b3f77a43a09f735ace24b9fcf7 100644 ---- a/drivers/clk/qcom/camcc-sm8650.c -+++ b/drivers/clk/qcom/camcc-sm8650.c -@@ -7,7 +7,6 @@ - #include - #include - #include --#include - #include - - #include -@@ -72,6 +71,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = { - - static struct clk_alpha_pll cam_cc_pll0 = { - .offset = 0x0, -+ .config = &cam_cc_pll0_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -149,6 +149,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = { - - static struct clk_alpha_pll cam_cc_pll1 = { - .offset = 0x1000, -+ .config = &cam_cc_pll1_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -199,6 +200,7 @@ static const struct alpha_pll_config cam_cc_pll2_config = { - - static struct clk_alpha_pll cam_cc_pll2 = { - .offset = 0x2000, -+ .config = &cam_cc_pll2_config, - .vco_table = rivian_ole_vco, - .num_vco = ARRAY_SIZE(rivian_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], -@@ -230,6 +232,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = { - - static struct clk_alpha_pll cam_cc_pll3 = { - .offset = 0x3000, -+ .config = &cam_cc_pll3_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -284,6 +287,7 @@ static const struct alpha_pll_config cam_cc_pll4_config = { - - static struct clk_alpha_pll cam_cc_pll4 = { - .offset = 0x4000, -+ .config = &cam_cc_pll4_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -338,6 +342,7 @@ static const struct alpha_pll_config cam_cc_pll5_config = { - - static struct clk_alpha_pll cam_cc_pll5 = { - .offset = 0x5000, -+ .config = &cam_cc_pll5_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -392,6 +397,7 @@ static const struct alpha_pll_config cam_cc_pll6_config = { - - static struct clk_alpha_pll cam_cc_pll6 = { - .offset = 0x6000, -+ .config = &cam_cc_pll6_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -446,6 +452,7 @@ static const struct alpha_pll_config cam_cc_pll7_config = { - - static struct clk_alpha_pll cam_cc_pll7 = { - .offset = 0x7000, -+ .config = &cam_cc_pll7_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -500,6 +507,7 @@ static const struct alpha_pll_config cam_cc_pll8_config = { - - static struct clk_alpha_pll cam_cc_pll8 = { - .offset = 0x8000, -+ .config = &cam_cc_pll8_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -554,6 +562,7 @@ static const struct alpha_pll_config cam_cc_pll9_config = { - - static struct clk_alpha_pll cam_cc_pll9 = { - .offset = 0x9000, -+ .config = &cam_cc_pll9_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -631,6 +640,7 @@ static const struct alpha_pll_config cam_cc_pll10_config = { - - static struct clk_alpha_pll cam_cc_pll10 = { - .offset = 0xa000, -+ .config = &cam_cc_pll10_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -3509,6 +3519,27 @@ static const struct qcom_reset_map cam_cc_sm8650_resets[] = { - [CAM_CC_SFE_2_BCR] = { 0x130f4 }, - }; - -+static struct clk_alpha_pll *cam_cc_sm8650_plls[] = { -+ &cam_cc_pll0, -+ &cam_cc_pll1, -+ &cam_cc_pll2, -+ &cam_cc_pll3, -+ &cam_cc_pll4, -+ &cam_cc_pll5, -+ &cam_cc_pll6, -+ &cam_cc_pll7, -+ &cam_cc_pll8, -+ &cam_cc_pll9, -+ &cam_cc_pll10, -+}; -+ -+static u32 cam_cc_sm8650_critical_cbcrs[] = { -+ 0x132ec, /* CAM_CC_GDSC_CLK */ -+ 0x13308, /* CAM_CC_SLEEP_CLK */ -+ 0x13314, /* CAM_CC_DRV_XO_CLK */ -+ 0x13318, /* CAM_CC_DRV_AHB_CLK */ -+}; -+ - static const struct regmap_config cam_cc_sm8650_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, -@@ -3517,6 +3548,13 @@ static const struct regmap_config cam_cc_sm8650_regmap_config = { - .fast_io = true, - }; - -+static struct qcom_cc_driver_data cam_cc_sm8650_driver_data = { -+ .alpha_plls = cam_cc_sm8650_plls, -+ .num_alpha_plls = ARRAY_SIZE(cam_cc_sm8650_plls), -+ .clk_cbcrs = cam_cc_sm8650_critical_cbcrs, -+ .num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8650_critical_cbcrs), -+}; -+ - static const struct qcom_cc_desc cam_cc_sm8650_desc = { - .config = &cam_cc_sm8650_regmap_config, - .clks = cam_cc_sm8650_clocks, -@@ -3525,6 +3563,8 @@ static const struct qcom_cc_desc cam_cc_sm8650_desc = { - .num_resets = ARRAY_SIZE(cam_cc_sm8650_resets), - .gdscs = cam_cc_sm8650_gdscs, - .num_gdscs = ARRAY_SIZE(cam_cc_sm8650_gdscs), -+ .use_rpm = true, -+ .driver_data = &cam_cc_sm8650_driver_data, - }; - - static const struct of_device_id cam_cc_sm8650_match_table[] = { -@@ -3535,46 +3575,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8650_match_table); - - static int cam_cc_sm8650_probe(struct platform_device *pdev) - { -- struct regmap *regmap; -- int ret; -- -- ret = devm_pm_runtime_enable(&pdev->dev); -- if (ret) -- return ret; -- -- ret = pm_runtime_resume_and_get(&pdev->dev); -- if (ret) -- return ret; -- -- regmap = qcom_cc_map(pdev, &cam_cc_sm8650_desc); -- if (IS_ERR(regmap)) { -- pm_runtime_put(&pdev->dev); -- return PTR_ERR(regmap); -- } -- -- clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); -- clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config); -- -- /* Keep clocks always enabled */ -- qcom_branch_set_clk_en(regmap, 0x13318); /* CAM_CC_DRV_AHB_CLK */ -- qcom_branch_set_clk_en(regmap, 0x13314); /* CAM_CC_DRV_XO_CLK */ -- qcom_branch_set_clk_en(regmap, 0x132ec); /* CAM_CC_GDSC_CLK */ -- qcom_branch_set_clk_en(regmap, 0x13308); /* CAM_CC_SLEEP_CLK */ -- -- ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8650_desc, regmap); -- -- pm_runtime_put(&pdev->dev); -- -- return ret; -+ return qcom_cc_probe(pdev, &cam_cc_sm8650_desc); - } - - static struct platform_driver cam_cc_sm8650_driver = { --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 12/18] clk: qcom: camcc-x1e80100: Move PLL & clk - configuration to really probe -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:57 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-12-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Camera PLLs on X1E80100 require both MMCX and MXC rails to be kept ON -to configure the PLLs properly. Hence move runtime power management, -PLL configuration and enabling critical clocks to qcom_cc_really_probe() -which ensures all required power domains are in enabled state before -configuring the PLLs or enabling the clocks. - -Reviewed-by: Bryan O'Donoghue -Tested-by: Bryan O'Donoghue # Dell Inspiron -Reviewed-by: Konrad Dybcio -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Jagadeesh Kona ---- - drivers/clk/qcom/camcc-x1e80100.c | 67 +++++++++++++++++++-------------------- - 1 file changed, 32 insertions(+), 35 deletions(-) - -diff --git a/drivers/clk/qcom/camcc-x1e80100.c b/drivers/clk/qcom/camcc-x1e80100.c -index b73524ae64b1b2b1ee94ceca88b5f3b46143f20b..cbcc1c9fcb341e51272f5595f574f9cb7ef2b52e 100644 ---- a/drivers/clk/qcom/camcc-x1e80100.c -+++ b/drivers/clk/qcom/camcc-x1e80100.c -@@ -7,7 +7,6 @@ - #include - #include - #include --#include - #include - - #include -@@ -67,6 +66,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = { - - static struct clk_alpha_pll cam_cc_pll0 = { - .offset = 0x0, -+ .config = &cam_cc_pll0_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -144,6 +144,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = { - - static struct clk_alpha_pll cam_cc_pll1 = { - .offset = 0x1000, -+ .config = &cam_cc_pll1_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -194,6 +195,7 @@ static const struct alpha_pll_config cam_cc_pll2_config = { - - static struct clk_alpha_pll cam_cc_pll2 = { - .offset = 0x2000, -+ .config = &cam_cc_pll2_config, - .vco_table = rivian_ole_vco, - .num_vco = ARRAY_SIZE(rivian_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], -@@ -225,6 +227,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = { - - static struct clk_alpha_pll cam_cc_pll3 = { - .offset = 0x3000, -+ .config = &cam_cc_pll3_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -279,6 +282,7 @@ static const struct alpha_pll_config cam_cc_pll4_config = { - - static struct clk_alpha_pll cam_cc_pll4 = { - .offset = 0x4000, -+ .config = &cam_cc_pll4_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -333,6 +337,7 @@ static const struct alpha_pll_config cam_cc_pll6_config = { - - static struct clk_alpha_pll cam_cc_pll6 = { - .offset = 0x6000, -+ .config = &cam_cc_pll6_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -387,6 +392,7 @@ static const struct alpha_pll_config cam_cc_pll8_config = { - - static struct clk_alpha_pll cam_cc_pll8 = { - .offset = 0x8000, -+ .config = &cam_cc_pll8_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], -@@ -2418,6 +2424,21 @@ static const struct qcom_reset_map cam_cc_x1e80100_resets[] = { - [CAM_CC_SFE_0_BCR] = { 0x1327c }, - }; - -+static struct clk_alpha_pll *cam_cc_x1e80100_plls[] = { -+ &cam_cc_pll0, -+ &cam_cc_pll1, -+ &cam_cc_pll2, -+ &cam_cc_pll3, -+ &cam_cc_pll4, -+ &cam_cc_pll6, -+ &cam_cc_pll8, -+}; -+ -+static u32 cam_cc_x1e80100_critical_cbcrs[] = { -+ 0x13a9c, /* CAM_CC_GDSC_CLK */ -+ 0x13ab8, /* CAM_CC_SLEEP_CLK */ -+}; -+ - static const struct regmap_config cam_cc_x1e80100_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, -@@ -2426,6 +2447,13 @@ static const struct regmap_config cam_cc_x1e80100_regmap_config = { - .fast_io = true, - }; - -+static struct qcom_cc_driver_data cam_cc_x1e80100_driver_data = { -+ .alpha_plls = cam_cc_x1e80100_plls, -+ .num_alpha_plls = ARRAY_SIZE(cam_cc_x1e80100_plls), -+ .clk_cbcrs = cam_cc_x1e80100_critical_cbcrs, -+ .num_clk_cbcrs = ARRAY_SIZE(cam_cc_x1e80100_critical_cbcrs), -+}; -+ - static const struct qcom_cc_desc cam_cc_x1e80100_desc = { - .config = &cam_cc_x1e80100_regmap_config, - .clks = cam_cc_x1e80100_clocks, -@@ -2434,6 +2462,8 @@ static const struct qcom_cc_desc cam_cc_x1e80100_desc = { - .num_resets = ARRAY_SIZE(cam_cc_x1e80100_resets), - .gdscs = cam_cc_x1e80100_gdscs, - .num_gdscs = ARRAY_SIZE(cam_cc_x1e80100_gdscs), -+ .use_rpm = true, -+ .driver_data = &cam_cc_x1e80100_driver_data, - }; - - static const struct of_device_id cam_cc_x1e80100_match_table[] = { -@@ -2444,40 +2474,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_x1e80100_match_table); - - static int cam_cc_x1e80100_probe(struct platform_device *pdev) - { -- struct regmap *regmap; -- int ret; -- -- ret = devm_pm_runtime_enable(&pdev->dev); -- if (ret) -- return ret; -- -- ret = pm_runtime_resume_and_get(&pdev->dev); -- if (ret) -- return ret; -- -- regmap = qcom_cc_map(pdev, &cam_cc_x1e80100_desc); -- if (IS_ERR(regmap)) { -- pm_runtime_put(&pdev->dev); -- return PTR_ERR(regmap); -- } -- -- clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); -- clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); -- clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); -- -- /* Keep clocks always enabled */ -- qcom_branch_set_clk_en(regmap, 0x13a9c); /* CAM_CC_GDSC_CLK */ -- qcom_branch_set_clk_en(regmap, 0x13ab8); /* CAM_CC_SLEEP_CLK */ -- -- ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_x1e80100_desc, regmap); -- -- pm_runtime_put(&pdev->dev); -- -- return ret; -+ return qcom_cc_probe(pdev, &cam_cc_x1e80100_desc); - } - - static struct platform_driver cam_cc_x1e80100_driver = { --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 13/18] arm64: dts: qcom: sm8450: Additionally manage MXC - power domain in videocc -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:58 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-13-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Videocc requires both MMCX and MXC rails to be powered ON to configure -the video PLLs on SM8450 platform. Hence add MXC power domain to videocc -node on SM8450. - -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Bryan O'Donoghue -Reviewed-by: Konrad Dybcio -Signed-off-by: Jagadeesh Kona ---- - arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi -index 0b36f4cd4497ecffe0a15cd6102e9d9ac62a7425..36a67c679fbaed944d7590528b696635c306da5d 100644 ---- a/arch/arm64/boot/dts/qcom/sm8450.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi -@@ -3198,8 +3198,10 @@ videocc: clock-controller@aaf0000 { - reg = <0 0x0aaf0000 0 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_VIDEO_AHB_CLK>; -- power-domains = <&rpmhpd RPMHPD_MMCX>; -- required-opps = <&rpmhpd_opp_low_svs>; -+ power-domains = <&rpmhpd RPMHPD_MMCX>, -+ <&rpmhpd RPMHPD_MXC>; -+ required-opps = <&rpmhpd_opp_low_svs>, -+ <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 14/18] arm64: dts: qcom: sm8550: Additionally manage MXC - power domain in videocc -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:50:59 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-14-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Videocc requires both MMCX and MXC rails to be powered ON to configure -the video PLLs on SM8550 platform. Hence add MXC power domain to videocc -node on SM8550. - -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Bryan O'Donoghue -Reviewed-by: Konrad Dybcio -Signed-off-by: Jagadeesh Kona ---- - arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi -index f78d5292c5dd5ec88c8deb0ca6e5078511ac52b7..92017caedbbbea12eb2e43f2e9f5bcad0c0ee40c 100644 ---- a/arch/arm64/boot/dts/qcom/sm8550.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi -@@ -3225,8 +3225,10 @@ videocc: clock-controller@aaf0000 { - reg = <0 0x0aaf0000 0 0x10000>; - clocks = <&bi_tcxo_div2>, - <&gcc GCC_VIDEO_AHB_CLK>; -- power-domains = <&rpmhpd RPMHPD_MMCX>; -- required-opps = <&rpmhpd_opp_low_svs>; -+ power-domains = <&rpmhpd RPMHPD_MMCX>, -+ <&rpmhpd RPMHPD_MXC>; -+ required-opps = <&rpmhpd_opp_low_svs>, -+ <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 15/18] arm64: dts: qcom: sm8650: Additionally manage MXC - power domain in videocc -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:51:00 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-15-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Videocc requires both MMCX and MXC rails to be powered ON to configure -the video PLLs on SM8650 platform. Hence add MXC power domain to videocc -node on SM8650. - -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Bryan O'Donoghue -Reviewed-by: Konrad Dybcio -Signed-off-by: Jagadeesh Kona ---- - arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi -index 818db6ba3b3be99c187512ea4acf2004422f6a18..ad60596b71d25bb0198b26660dc41195a1210a23 100644 ---- a/arch/arm64/boot/dts/qcom/sm8650.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi -@@ -4959,7 +4959,8 @@ videocc: clock-controller@aaf0000 { - reg = <0 0x0aaf0000 0 0x10000>; - clocks = <&bi_tcxo_div2>, - <&gcc GCC_VIDEO_AHB_CLK>; -- power-domains = <&rpmhpd RPMHPD_MMCX>; -+ power-domains = <&rpmhpd RPMHPD_MMCX>, -+ <&rpmhpd RPMHPD_MXC>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 16/18] arm64: dts: qcom: sm8450: Additionally manage MXC - power domain in camcc -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:51:01 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-16-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Camcc requires both MMCX and MXC rails to be powered ON to configure -the camera PLLs on SM8450 platform. Hence add MXC power domain to -camcc node on SM8450. - -Reviewed-by: Konrad Dybcio -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Jagadeesh Kona -Reviewed-by: Bryan O'Donoghue ---- - arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi -index 36a67c679fbaed944d7590528b696635c306da5d..624190c07c59f3e6714f296f1b264d2a88135116 100644 ---- a/arch/arm64/boot/dts/qcom/sm8450.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi -@@ -3292,8 +3292,10 @@ camcc: clock-controller@ade0000 { - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; -- power-domains = <&rpmhpd RPMHPD_MMCX>; -- required-opps = <&rpmhpd_opp_low_svs>; -+ power-domains = <&rpmhpd RPMHPD_MMCX>, -+ <&rpmhpd RPMHPD_MXC>; -+ required-opps = <&rpmhpd_opp_low_svs>, -+ <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 17/18] arm64: dts: qcom: sm8550: Additionally manage MXC - power domain in camcc -From: Vladimir Zapolskiy -Date: Fri, 30 May 2025 18:51:02 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-17-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Camcc requires both MMCX and MXC rails to be powered ON to configure -the camera PLLs on SM8550 platform. Hence add MXC power domain to -camcc node on SM8550. While at it, update SM8550_MMCX macro to RPMHPD_MMCX -to align towards common macros. - -Fixes: e271b59e39a6f ("arm64: dts: qcom: sm8550: Add camera clock controller") -Signed-off-by: Vladimir Zapolskiy -Reviewed-by: Taniya Das -Reviewed-by: Konrad Dybcio -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Jagadeesh Kona -Reviewed-by: Bryan O'Donoghue ---- - arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi -index 92017caedbbbea12eb2e43f2e9f5bcad0c0ee40c..e9bb077aa9f0b8be28608d4a0345aae7df8cd167 100644 ---- a/arch/arm64/boot/dts/qcom/sm8550.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi -@@ -3333,8 +3333,10 @@ camcc: clock-controller@ade0000 { - <&bi_tcxo_div2>, - <&bi_tcxo_ao_div2>, - <&sleep_clk>; -- power-domains = <&rpmhpd SM8550_MMCX>; -- required-opps = <&rpmhpd_opp_low_svs>; -+ power-domains = <&rpmhpd RPMHPD_MMCX>, -+ <&rpmhpd RPMHPD_MXC>; -+ required-opps = <&rpmhpd_opp_low_svs>, -+ <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; --- -2.34.1 - -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v5 18/18] arm64: dts: qcom: sm8650: Additionally manage MXC - power domain in camcc -From: Jagadeesh Kona -Date: Fri, 30 May 2025 18:51:03 +0530 -Message-Id: <20250530-videocc-pll-multi-pd-voting-v5-18-02303b3a582d@quicinc.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -Camcc requires both MMCX and MXC rails to be powered ON to configure -the camera PLLs on SM8650 platform. Hence add MXC power domain to -camcc node on SM8650. - -Reviewed-by: Konrad Dybcio -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Jagadeesh Kona -Reviewed-by: Bryan O'Donoghue ---- - arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi -index ad60596b71d25bb0198b26660dc41195a1210a23..a2b3d97abc7f799810e20131d7231608c8757859 100644 ---- a/arch/arm64/boot/dts/qcom/sm8650.dtsi -+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi -@@ -5072,7 +5072,8 @@ camcc: clock-controller@ade0000 { - <&bi_tcxo_div2>, - <&bi_tcxo_ao_div2>, - <&sleep_clk>; -- power-domains = <&rpmhpd RPMHPD_MMCX>; -+ power-domains = <&rpmhpd RPMHPD_MMCX>, -+ <&rpmhpd RPMHPD_MXC>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; --- -2.34.1 - diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0200_arm64--dts--qcom--Add-AYN-Odin2-Common.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0200_arm64--dts--qcom--Add-AYN-Odin2-Common.patch index bf25056d5e..0cd13adf1c 100644 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0200_arm64--dts--qcom--Add-AYN-Odin2-Common.patch +++ b/projects/ROCKNIX/devices/SM8550/patches/linux/0200_arm64--dts--qcom--Add-AYN-Odin2-Common.patch @@ -3,7 +3,7 @@ new file mode 100644 index 000000000000..58d9ab342fe9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-common.dtsi -@@ -0,0 +1,1602 @@ +@@ -0,0 +1,1598 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Teguh Sobirin. @@ -30,10 +30,6 @@ index 000000000000..58d9ab342fe9 +/delete-node/ &cdsp_mem; +/delete-node/ &q6_cdsp_dtb_mem; + -+/delete-node/ &cci0; -+/delete-node/ &cci1; -+/delete-node/ &cci2; -+/delete-node/ &camcc; +/delete-node/ &remoteproc_mpss; +/delete-node/ &remoteproc_cdsp; + diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0210_arm64--dts--qcom--Add-AYANEO-Pocket-Common.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0210_arm64--dts--qcom--Add-AYANEO-Pocket-Common.patch index 758862f17b..f28895fab7 100644 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0210_arm64--dts--qcom--Add-AYANEO-Pocket-Common.patch +++ b/projects/ROCKNIX/devices/SM8550/patches/linux/0210_arm64--dts--qcom--Add-AYANEO-Pocket-Common.patch @@ -3,7 +3,7 @@ new file mode 100644 index 000000000000..58d9ab342fe9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocket-common.dtsi -@@ -0,0 +1,1486 @@ +@@ -0,0 +1,1482 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Teguh Sobirin. @@ -30,10 +30,6 @@ index 000000000000..58d9ab342fe9 +/delete-node/ &cdsp_mem; +/delete-node/ &q6_cdsp_dtb_mem; + -+/delete-node/ &cci0; -+/delete-node/ &cci1; -+/delete-node/ &cci2; -+/delete-node/ &camcc; +/delete-node/ &remoteproc_mpss; +/delete-node/ &remoteproc_cdsp; + diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0601-v2_20250617_aditya_kumar_singh_wifi_ath12k_handle_regulatory_hints_during_mac_registration.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0601-v2_20250617_aditya_kumar_singh_wifi_ath12k_handle_regulatory_hints_during_mac_registration.patch deleted file mode 100644 index 6c9609f531..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0601-v2_20250617_aditya_kumar_singh_wifi_ath12k_handle_regulatory_hints_during_mac_registration.patch +++ /dev/null @@ -1,252 +0,0 @@ -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH v2] wifi: ath12k: handle regulatory hints during mac - registration -From: Aditya Kumar Singh -Date: Tue, 17 Jun 2025 09:05:59 +0530 -Message-Id: <20250617-handle_user_regd_update_hints_during_insmod-v2-1-10a6a48efe81@oss.qualcomm.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -If a regulatory notification is there in the system while the hardware is -being registered, it attempts to set the new regulatory country. However, -ath12k currently boots with a default country derived from the BDF. If this -default country differs from the one provided in the notification, a race -condition can occur while updating the regulatory information back to -userspace. This potentially leads to driver having the incorrect regulatory -applied. - -For example, suppose the regulatory domain for France (FR) is already -applied, and then the driver is loaded with a BDF that has the United -States (US) country programmed. When the driver finishes loading, the -regulatory domain shown in phyX still reflects the US regulatory settings. -This is incorrect, as the driver had already received a notification for -FR during hardware registration, but failed to process it properly due to -the race condition. - -The race condition exists during driver initialization and hardware -registration: -- On driver load, the firmware sends BDF-based country regulatory rules, - which are stored in default_regd via ath12k_reg_handle_chan_list(). - -- During hardware registration, a regulatory notification is triggered - through: - ath12k_mac_hw_register() - -> ieee80211_register_hw() - -> wiphy_register() - -> wiphy_regulatory_register() - -> reg_call_notifier() - - This sends a country code to the firmware, which responds with updated - regulatory rules. - -- After registration, ath12k_mac_hw_register() calls ath12k_regd_update(), - which copies default_regd and passes it to the upper layers. - -The race occurs between the firmware's response and the execution of -ath12k_regd_update(). If the firmware's new rules are processed before the -update call, the correct values are used. Otherwise, outdated boot-time -country settings are exposed to userspace. - -To resolve this issue, introduce a completion mechanism within the hardware -group (ah). Trigger this completion whenever a regulatory change is -requested from the firmware. Then, in ath12k_regd_update(), wait for the -firmware to complete its regulatory processing before proceeding with the -update. - -This ensures that during driver load, the default country is processed -first. However, before ath12k_regd_update() is called, the new regulatory -notification will have already been received by the driver. As a result, it -will wait for the firmware's regulatory processing to complete, and only -the final, correct regulatory domain will be updated to userspace. - -Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.4.1-00199-QCAHKSWPL_SILICONZ-1 - -Signed-off-by: Aditya Kumar Singh -Reviewed-by: Vasanthakumar Thiagarajan ---- -Changes in v2: -- Fixed uninitialed variable usage warnings (detected by clang) ---- - drivers/net/wireless/ath/ath12k/core.c | 4 ++++ - drivers/net/wireless/ath/ath12k/core.h | 1 + - drivers/net/wireless/ath/ath12k/mac.c | 15 +++++++++++++++ - drivers/net/wireless/ath/ath12k/reg.c | 12 ++++++++++++ - drivers/net/wireless/ath/ath12k/reg.h | 2 ++ - drivers/net/wireless/ath/ath12k/wmi.c | 17 +++++++++++++++-- - 6 files changed, 49 insertions(+), 2 deletions(-) - -diff --git a/drivers/net/wireless/ath/ath12k/core.c b/drivers/net/wireless/ath/ath12k/core.c -index ebc0560d40e3419130e4caf01c9b91bd9affb3bd..9c18a706dc3ae3b8c5b95d8575e778c8a9c898ba 100644 ---- a/drivers/net/wireless/ath/ath12k/core.c -+++ b/drivers/net/wireless/ath/ath12k/core.c -@@ -1470,6 +1470,7 @@ static void ath12k_core_pre_reconfigure_recovery(struct ath12k_base *ab) - complete(&ar->vdev_setup_done); - complete(&ar->vdev_delete_done); - complete(&ar->bss_survey_done); -+ complete(&ar->regd_update_completed); - - wake_up(&ar->dp.tx_empty_waitq); - idr_for_each(&ar->txmgmt_idr, -@@ -1509,6 +1510,9 @@ static void ath12k_update_11d(struct work_struct *work) - ar = pdev->ar; - - memcpy(&ar->alpha2, &arg.alpha2, 2); -+ -+ reinit_completion(&ar->regd_update_completed); -+ - ret = ath12k_wmi_send_set_current_country_cmd(ar, &arg); - if (ret) - ath12k_warn(ar->ab, -diff --git a/drivers/net/wireless/ath/ath12k/core.h b/drivers/net/wireless/ath/ath12k/core.h -index 941db6e49d6eaeb03783f7714d433259d887820b..329f3e490a713b179413f73a4024448aedc363fd 100644 ---- a/drivers/net/wireless/ath/ath12k/core.h -+++ b/drivers/net/wireless/ath/ath12k/core.h -@@ -804,6 +804,7 @@ struct ath12k { - enum ath12k_11d_state state_11d; - u8 alpha2[REG_ALPHA2_LEN]; - bool regdom_set_by_user; -+ struct completion regd_update_completed; - - struct completion fw_stats_complete; - -diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c -index 88b59f3ff87af8b48cb3fafcd364fd9ced4ff197..ef2e8398cbe8723c020aff03da5db7fa7fb2245e 100644 ---- a/drivers/net/wireless/ath/ath12k/mac.c -+++ b/drivers/net/wireless/ath/ath12k/mac.c -@@ -10900,6 +10900,7 @@ ath12k_mac_op_reconfig_complete(struct ieee80211_hw *hw, - struct wmi_set_current_country_arg arg = {}; - - memcpy(&arg.alpha2, ar->alpha2, 2); -+ reinit_completion(&ar->regd_update_completed); - ath12k_wmi_send_set_current_country_cmd(ar, &arg); - } - -@@ -12116,6 +12117,16 @@ static int ath12k_mac_hw_register(struct ath12k_hw *ah) - goto err_cleanup_if_combs; - } - -+ /* Boot-time regulatory updates have already been processed. -+ * Mark them as complete now, because after registration, -+ * cfg80211 will notify us again if there are any pending hints. -+ * We need to wait for those hints to be processed, so it's -+ * important to mark the boot-time updates as complete before -+ * proceeding with registration. -+ */ -+ for_each_ar(ah, ar, i) -+ complete(&ar->regd_update_completed); -+ - ret = ieee80211_register_hw(hw); - if (ret) { - ath12k_err(ab, "ieee80211 registration failed: %d\n", ret); -@@ -12143,6 +12154,9 @@ static int ath12k_mac_hw_register(struct ath12k_hw *ah) - - memcpy(¤t_cc.alpha2, ab->new_alpha2, 2); - memcpy(&ar->alpha2, ab->new_alpha2, 2); -+ -+ reinit_completion(&ar->regd_update_completed); -+ - ret = ath12k_wmi_send_set_current_country_cmd(ar, ¤t_cc); - if (ret) - ath12k_warn(ar->ab, -@@ -12215,6 +12229,7 @@ static void ath12k_mac_setup(struct ath12k *ar) - init_completion(&ar->scan.on_channel); - init_completion(&ar->mlo_setup_done); - init_completion(&ar->completed_11d_scan); -+ init_completion(&ar->regd_update_completed); - - INIT_DELAYED_WORK(&ar->scan.timeout, ath12k_scan_timeout_work); - wiphy_work_init(&ar->scan.vdev_clean_wk, ath12k_scan_vdev_clean_work); -diff --git a/drivers/net/wireless/ath/ath12k/reg.c b/drivers/net/wireless/ath/ath12k/reg.c -index 2598b39d5d7ee9b24ad8ed5d6de1bc5bbc6554e0..079dcb6d83df4eb487fb0dbf4088fb8cacca8f6e 100644 ---- a/drivers/net/wireless/ath/ath12k/reg.c -+++ b/drivers/net/wireless/ath/ath12k/reg.c -@@ -102,6 +102,8 @@ ath12k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) - - /* Send the reg change request to all the radios */ - for_each_ar(ah, ar, i) { -+ reinit_completion(&ar->regd_update_completed); -+ - if (ar->ab->hw_params->current_cc_support) { - memcpy(¤t_arg.alpha2, request->alpha2, 2); - memcpy(&ar->alpha2, ¤t_arg.alpha2, 2); -@@ -272,9 +274,19 @@ int ath12k_regd_update(struct ath12k *ar, bool init) - struct ieee80211_regdomain *regd, *regd_copy = NULL; - int ret, regd_len, pdev_id; - struct ath12k_base *ab; -+ long time_left; - - ab = ar->ab; - -+ time_left = wait_for_completion_timeout(&ar->regd_update_completed, -+ ATH12K_REG_UPDATE_TIMEOUT_HZ); -+ if (time_left == 0) { -+ ath12k_warn(ab, "Timeout while waiting for regulatory update"); -+ /* Even though timeout has occurred, still continue since at least boot -+ * time data would be there to process -+ */ -+ } -+ - supported_bands = ar->pdev->cap.supported_bands; - reg_cap = &ab->hal_reg_cap[ar->pdev_idx]; - -diff --git a/drivers/net/wireless/ath/ath12k/reg.h b/drivers/net/wireless/ath/ath12k/reg.h -index 8af8e9ba462e90db3eb137885d0acd4b1cb2286e..fb508302c7f0f1fea2588ad4cf9d813da574d06b 100644 ---- a/drivers/net/wireless/ath/ath12k/reg.h -+++ b/drivers/net/wireless/ath/ath12k/reg.h -@@ -13,6 +13,8 @@ - struct ath12k_base; - struct ath12k; - -+#define ATH12K_REG_UPDATE_TIMEOUT_HZ (3 * HZ) -+ - #define ATH12K_2GHZ_MAX_FREQUENCY 2495 - #define ATH12K_5GHZ_MAX_FREQUENCY 5920 - -diff --git a/drivers/net/wireless/ath/ath12k/wmi.c b/drivers/net/wireless/ath/ath12k/wmi.c -index 60e2444fe08cefa39ae218d07eb9736d2a0c982b..db839fc835816c9a2d03d194547af506760f6c81 100644 ---- a/drivers/net/wireless/ath/ath12k/wmi.c -+++ b/drivers/net/wireless/ath/ath12k/wmi.c -@@ -6143,7 +6143,8 @@ static void ath12k_wmi_htc_tx_complete(struct ath12k_base *ab, - static int ath12k_reg_chan_list_event(struct ath12k_base *ab, struct sk_buff *skb) - { - struct ath12k_reg_info *reg_info; -- u8 pdev_idx; -+ struct ath12k *ar = NULL; -+ u8 pdev_idx = 255; - int ret; - - reg_info = kzalloc(sizeof(*reg_info), GFP_ATOMIC); -@@ -6198,7 +6199,7 @@ static int ath12k_reg_chan_list_event(struct ath12k_base *ab, struct sk_buff *sk - kfree(reg_info); - - if (ret == ATH12K_REG_STATUS_VALID) -- return ret; -+ goto out; - - fallback: - /* Fallback to older reg (by sending previous country setting -@@ -6212,6 +6213,18 @@ static int ath12k_reg_chan_list_event(struct ath12k_base *ab, struct sk_buff *sk - WARN_ON(1); - - out: -+ /* In some error cases, even a valid pdev_idx might not be available */ -+ if (pdev_idx != 255) -+ ar = ab->pdevs[pdev_idx].ar; -+ -+ /* During the boot-time update, 'ar' might not be allocated, -+ * so the completion cannot be marked at that point. -+ * This boot-time update is handled in ath12k_mac_hw_register() -+ * before registering the hardware. -+ */ -+ if (ar) -+ complete(&ar->regd_update_completed); -+ - return ret; - } - - ---- -base-commit: 7fb79ce2693c94f8f74bf62ad25a97e4b61721b8 -change-id: 20250522-handle_user_regd_update_hints_during_insmod-42c71ee7f386 - diff --git a/projects/ROCKNIX/devices/SM8550/patches/linux/0602-20250626_aditya_kumar_singh_wifi_ath12k_fix_timeout_while_waiting_for_regulatory_update_during_inter.patch b/projects/ROCKNIX/devices/SM8550/patches/linux/0602-20250626_aditya_kumar_singh_wifi_ath12k_fix_timeout_while_waiting_for_regulatory_update_during_inter.patch deleted file mode 100644 index f781cea108..0000000000 --- a/projects/ROCKNIX/devices/SM8550/patches/linux/0602-20250626_aditya_kumar_singh_wifi_ath12k_fix_timeout_while_waiting_for_regulatory_update_during_inter.patch +++ /dev/null @@ -1,95 +0,0 @@ -From git@z Thu Jan 1 00:00:00 1970 -Subject: [PATCH] wifi: ath12k: fix timeout while waiting for regulatory - update during interface creation -From: Aditya Kumar Singh -Date: Thu, 26 Jun 2025 10:49:56 +0530 -Message-Id: <20250626-fix_timeout_during_interface_creation-v1-1-90a7fdc222d4@oss.qualcomm.com> -MIME-Version: 1.0 -Content-Type: text/plain; charset="utf-8" -Content-Transfer-Encoding: 7bit - -During interface creation, following print is observed on the console - - - Timeout while waiting for regulatory update - -This occurs due to commit 906619a00967 ("wifi: ath12k: handle regulatory -hints during mac registration"), which introduced a completion mechanism to -synchronize the regulatory update process. The intent behind this change is -to coordinate the timing between when the firmware sends regulatory data to -the driver and when the driver processes that data. - -However, during interface addition, if the 6 GHz band is active, the driver -invokes ath12k_regd_update() to apply the appropriate 6 GHz power mode -regulatory settings. At this point, there is no interaction with the -firmware, so the completion object is not reinitialized. As a result, -wait_for_completion() eventually times out, leading to the observed error -log message. - -Hence to fix this, move all complete() on regd_update_completed to -complete_all(). - -The complete() function signals only once, causing any subsequent waits -without reinitialization to timeout. In this scenario, since waiting is -unnecessary, complete_all() can be used instead, ensuring that subsequent -calls to wait without reinitialization will simply bail out and not -actually wait. This approach is ideal because if the firmware is not -involved, there is no need to wait for the completion event. However, if -the firmware is involved, it is guaranteed that the completion will be -reinitialized, and thus, it would wait. - -Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.5-01651-QCAHKSWPL_SILICONZ-1 -Tested-by: Kang Yang -Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3 - -Fixes: 906619a00967 ("wifi: ath12k: handle regulatory hints during mac registration") -Signed-off-by: Aditya Kumar Singh ---- - drivers/net/wireless/ath/ath12k/core.c | 2 +- - drivers/net/wireless/ath/ath12k/mac.c | 2 +- - drivers/net/wireless/ath/ath12k/wmi.c | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/net/wireless/ath/ath12k/core.c b/drivers/net/wireless/ath/ath12k/core.c -index 83caba3104d6c0bca40dd1166de335aabc8b74e5..ffc19a6b948539dddf3f6f21f2799f1b661347f7 100644 ---- a/drivers/net/wireless/ath/ath12k/core.c -+++ b/drivers/net/wireless/ath/ath12k/core.c -@@ -1475,7 +1475,7 @@ static void ath12k_core_pre_reconfigure_recovery(struct ath12k_base *ab) - complete(&ar->vdev_setup_done); - complete(&ar->vdev_delete_done); - complete(&ar->bss_survey_done); -- complete(&ar->regd_update_completed); -+ complete_all(&ar->regd_update_completed); - - wake_up(&ar->dp.tx_empty_waitq); - idr_for_each(&ar->txmgmt_idr, -diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c -index 32519666632d1877eb48a31e94e5eb47f2b33880..d5f41f0fceee23710d2d775bb4d6f7451e15a55b 100644 ---- a/drivers/net/wireless/ath/ath12k/mac.c -+++ b/drivers/net/wireless/ath/ath12k/mac.c -@@ -12755,7 +12755,7 @@ static int ath12k_mac_hw_register(struct ath12k_hw *ah) - * proceeding with registration. - */ - for_each_ar(ah, ar, i) -- complete(&ar->regd_update_completed); -+ complete_all(&ar->regd_update_completed); - - ret = ieee80211_register_hw(hw); - if (ret) { -diff --git a/drivers/net/wireless/ath/ath12k/wmi.c b/drivers/net/wireless/ath/ath12k/wmi.c -index b38f22118d732aa182f9fd6dda376b0d41de65e2..2fb262d13a586bbf354a74be8e509df2b4905f30 100644 ---- a/drivers/net/wireless/ath/ath12k/wmi.c -+++ b/drivers/net/wireless/ath/ath12k/wmi.c -@@ -6764,7 +6764,7 @@ static int ath12k_reg_chan_list_event(struct ath12k_base *ab, struct sk_buff *sk - * before registering the hardware. - */ - if (ar) -- complete(&ar->regd_update_completed); -+ complete_all(&ar->regd_update_completed); - - return ret; - } - ---- -base-commit: aa555da8266715e52e5dd74360f3b4c866ddcb64 -change-id: 20250625-fix_timeout_during_interface_creation-ae428c7d3684 - diff --git a/projects/ROCKNIX/packages/linux/package.mk b/projects/ROCKNIX/packages/linux/package.mk index 76c17c4968..a6803c3cc3 100644 --- a/projects/ROCKNIX/packages/linux/package.mk +++ b/projects/ROCKNIX/packages/linux/package.mk @@ -31,10 +31,10 @@ case ${DEVICE} in ;; *) case ${DEVICE} in - SM8250) + SM8250|SM8550) PKG_VERSION="6.17" ;; - SM8550|H700) + H700) PKG_VERSION="6.16.9" ;; *)