Lennert Buytenhek 573a652fb0 ARM: Add Tauros2 L2 cache controller support ...

Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>

2009-11-27 15:43:21 -05:00

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include/mach

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addr-map.c

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common.c

ARM: Add Tauros2 L2 cache controller support

2009-11-27 15:43:21 -05:00

common.h

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dove-db-setup.c

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irq.c

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Kconfig

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Makefile

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Makefile.boot

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pcie.c

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