Tuomas Tynkkynen 89ac8567b9 clk: tegra30: Don't wait for PLL_U lock bit ...

The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

2013-08-28 19:08:09 -07:00

..

clk-audio-sync.c

…

clk-divider.c

…

clk-periph-gate.c

clk: tegra: Workaround for Tegra114 MSENC problem

2013-04-04 16:10:59 -06:00

clk-periph.c

clk: tegra: Add flags to tegra_clk_periph()

2013-04-04 16:10:56 -06:00

clk-pll-out.c

…

clk-pll.c

clk: tegra: Use override bits when needed

2013-06-11 18:00:32 -07:00

clk-super.c

clk: tegra: Implement locking for super clock

2013-02-12 10:29:12 -07:00

clk-tegra20.c

clk: add CLK_SET_RATE_NO_REPARENT flag

2013-08-19 12:27:17 -07:00

clk-tegra30.c

clk: tegra30: Don't wait for PLL_U lock bit

2013-08-28 19:08:09 -07:00

clk-tegra114.c

clk: add CLK_SET_RATE_NO_REPARENT flag

2013-08-19 12:27:17 -07:00

clk.c

clk: tegra: Use common of_clk_init function

2013-05-31 12:57:25 -07:00

clk.h

clk: tegra: T114: add DFLL DVCO reset control

2013-06-18 11:28:51 -07:00

Makefile

clk: tegra: Implement clocks for Tegra114

2013-04-04 17:17:12 -06:00