Markos Chandras 934c79231c MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions ...

MIPS R6 changed the 'cache' instruction opcode and reduced the
offset field to 8 bits. This means we now have to adjust the
base register every 256 bytes and as a result of which we can
no longer use the previous cache functions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

2015-02-17 15:37:20 +00:00

..

asm

MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions

2015-02-17 15:37:20 +00:00

uapi/asm

MIPS: mm: Add MIPS R6 instruction encodings

2015-02-16 14:02:50 +00:00