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Aneesh Kumar K.V
f6eedbba7a
We update the hash linux page table layout such that we can support 512TB. But we limit the TASK_SIZE to 128TB. We can switch to 128TB by default without conditional because that is the max virtual address supported by other architectures. We will later add a mechanism to on-demand increase the application's effective address range to 512TB. Having the page table layout changed to accommodate 512TB makes testing large memory configuration easier with less code changes to kernel Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
113 lines
3.0 KiB
C
113 lines
3.0 KiB
C
#ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
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#define _ASM_POWERPC_BOOK3S_64_HASH_4K_H
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/*
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* Entries per page directory level. The PTE level must use a 64b record
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* for each page table entry. The PMD and PGD level use a 32b record for
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* each entry by assuming that each entry is page aligned.
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*/
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#define H_PTE_INDEX_SIZE 9
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#define H_PMD_INDEX_SIZE 7
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#define H_PUD_INDEX_SIZE 9
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#define H_PGD_INDEX_SIZE 12
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#ifndef __ASSEMBLY__
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#define H_PTE_TABLE_SIZE (sizeof(pte_t) << H_PTE_INDEX_SIZE)
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#define H_PMD_TABLE_SIZE (sizeof(pmd_t) << H_PMD_INDEX_SIZE)
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#define H_PUD_TABLE_SIZE (sizeof(pud_t) << H_PUD_INDEX_SIZE)
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#define H_PGD_TABLE_SIZE (sizeof(pgd_t) << H_PGD_INDEX_SIZE)
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/* PTE flags to conserve for HPTE identification */
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#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \
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H_PAGE_F_SECOND | H_PAGE_F_GIX)
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/*
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* Not supported by 4k linux page size
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*/
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#define H_PAGE_4K_PFN 0x0
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#define H_PAGE_THP_HUGE 0x0
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#define H_PAGE_COMBO 0x0
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#define H_PTE_FRAG_NR 0
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#define H_PTE_FRAG_SIZE_SHIFT 0
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/*
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* On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()
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*/
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#define remap_4k_pfn(vma, addr, pfn, prot) \
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
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#ifdef CONFIG_HUGETLB_PAGE
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static inline int hash__hugepd_ok(hugepd_t hpd)
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{
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unsigned long hpdval = hpd_val(hpd);
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/*
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* if it is not a pte and have hugepd shift mask
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* set, then it is a hugepd directory pointer
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*/
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if (!(hpdval & _PAGE_PTE) &&
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((hpdval & HUGEPD_SHIFT_MASK) != 0))
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return true;
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return false;
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}
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#endif
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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static inline char *get_hpte_slot_array(pmd_t *pmdp)
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{
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BUG();
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return NULL;
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}
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static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)
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{
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BUG();
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return 0;
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}
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static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array,
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int index)
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{
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BUG();
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return 0;
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}
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static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array,
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unsigned int index, unsigned int hidx)
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{
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BUG();
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}
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static inline int hash__pmd_trans_huge(pmd_t pmd)
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{
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return 0;
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}
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static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
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{
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BUG();
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return 0;
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}
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static inline pmd_t hash__pmd_mkhuge(pmd_t pmd)
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{
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BUG();
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return pmd;
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}
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extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm,
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unsigned long addr, pmd_t *pmdp,
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unsigned long clr, unsigned long set);
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extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp);
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extern void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
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pgtable_t pgtable);
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extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
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extern void hash__pmdp_huge_split_prepare(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp);
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extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm,
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unsigned long addr, pmd_t *pmdp);
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extern int hash__has_transparent_hugepage(void);
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#endif
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_POWERPC_BOOK3S_64_HASH_4K_H */
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