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Ralph Sennhauser
6c7515c61f
As it turns out more than just Armada 370 and XP support using GPIO
lines as PWM lines. For example the Armada 38x family has the same
hardware support. As such "marvell,armada-370-xp-gpio" for the
compatible string is a misnomer.
Change the compatible string to "marvell,armada-370-gpio" before the
driver makes it out of the -rc stage. This also follows the practice of
using only the first device family supported as part of the name.
Also update the documentation and comments in the code accordingly.
Fixes: 757642f9a5 ("gpio: mvebu: Add limited PWM support")
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
86 lines
2.7 KiB
Plaintext
86 lines
2.7 KiB
Plaintext
* Marvell EBU GPIO controller
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Required properties:
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- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
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or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
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Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
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370. "marvell,mv78200-gpio" should be used for the Discovery
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MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
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SoCs (MV78230, MV78260, MV78460).
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- reg: Address and length of the register set for the device. Only one
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entry is expected, except for the "marvell,armadaxp-gpio" variant
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for which two entries are expected: one for the general registers,
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one for the per-cpu registers.
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- interrupts: The list of interrupts that are used for all the pins
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managed by this GPIO bank. There can be more than one interrupt
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(example: 1 interrupt per 8 pins on Armada XP, which means 4
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interrupts per bank of 32 GPIOs).
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. Should be two.
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The first cell is the GPIO number.
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The second cell is used to specify flags:
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bits[3:0] trigger type and level flags:
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1 = low-to-high edge triggered.
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2 = high-to-low edge triggered.
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4 = active high level-sensitive.
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8 = active low level-sensitive.
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- gpio-controller: marks the device node as a gpio controller
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- ngpios: number of GPIOs this controller has
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- #gpio-cells: Should be two. The first cell is the pin number. The
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second cell is reserved for flags, unused at the moment.
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Optional properties:
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In order to use the GPIO lines in PWM mode, some additional optional
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properties are required.
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- compatible: Must contain "marvell,armada-370-gpio"
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- reg: an additional register set is needed, for the GPIO Blink
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Counter on/off registers.
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- reg-names: Must contain an entry "pwm" corresponding to the
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additional register range needed for PWM operation.
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- #pwm-cells: Should be two. The first cell is the GPIO line number. The
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second cell is the period in nanoseconds.
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- clocks: Must be a phandle to the clock for the GPIO controller.
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Example:
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gpio0: gpio@d0018100 {
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compatible = "marvell,armadaxp-gpio";
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reg = <0xd0018100 0x40>,
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<0xd0018800 0x30>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <16>, <17>, <18>, <19>;
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};
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gpio1: gpio@18140 {
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compatible = "marvell,armada-370-gpio";
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reg = <0x18140 0x40>, <0x181c8 0x08>;
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reg-names = "gpio", "pwm";
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ngpios = <17>;
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gpio-controller;
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#gpio-cells = <2>;
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#pwm-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <87>, <88>, <89>;
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clocks = <&coreclk 0>;
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};
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