Daniel Vetter 50b44a449f drm/i915: clear DPLL reg when disabling i9xx dplls ...

Toghether with the hw state readout this should catch cases where we
don't properly updated the pll state (either in sw or hw). At least
for the shared dpll code the equivalent tricke helped a lot in
catching bugs.

Also rename the function prefix, it's not a generic piece of
infrastructure.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2013-07-12 18:54:02 +02:00

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drm

drm/i915: clear DPLL reg when disabling i9xx dplls

2013-07-12 18:54:02 +02:00

host1x

gpu: host1x: Rework CPU syncpoint increment

2013-06-22 12:43:55 +02:00

vga

…

Makefile

gpu: host1x: Add host1x driver

2013-04-22 12:32:40 +02:00