Daniel Vetter 3ad8a208ab drm/i915: Fix up cpt pixel multiplier enable sequence ...

Bspec for the "DPLL HDMI multiplier" field says:

"Restriction : The DPLL must be enabled and stable before setting these bits.
These bits must be programmed after DPLL_SEL is programmed."

There is apparently no restriction on programming the DPLL_SEL
register wrt the DPLL. So let's just move that up before we enable the
pch dpll.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2013-07-12 18:54:01 +02:00

..

drm

drm/i915: Fix up cpt pixel multiplier enable sequence

2013-07-12 18:54:01 +02:00

host1x

gpu: host1x: Rework CPU syncpoint increment

2013-06-22 12:43:55 +02:00

vga

…

Makefile

gpu: host1x: Add host1x driver

2013-04-22 12:32:40 +02:00