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Ben Skeggs
ebb945a94b
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
142 lines
4.7 KiB
C
142 lines
4.7 KiB
C
#ifndef __NOUVEAU_COMPAT_H__
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#define __NOUVEAU_COMPAT_H__
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int nvdrm_gart_init(struct drm_device *, u64 *, u64 *);
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u8 _nv_rd08(struct drm_device *, u32);
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void _nv_wr08(struct drm_device *, u32, u8);
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u32 _nv_rd32(struct drm_device *, u32);
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void _nv_wr32(struct drm_device *, u32, u32);
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u32 _nv_mask(struct drm_device *, u32, u32, u32);
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bool _nv_bios(struct drm_device *, u8 **, u32 *);
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struct dcb_gpio_func;
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void nouveau_gpio_reset(struct drm_device *);
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int nouveau_gpio_find(struct drm_device *, int, u8, u8, struct dcb_gpio_func *);
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bool nouveau_gpio_func_valid(struct drm_device *, u8 tag);
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int nouveau_gpio_func_set(struct drm_device *, u8 tag, int state);
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int nouveau_gpio_func_get(struct drm_device *, u8 tag);
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int nouveau_gpio_irq(struct drm_device *, int idx, u8 tag, u8 line, bool on);
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int nouveau_gpio_isr_add(struct drm_device *, int idx, u8 tag, u8 line,
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void (*)(void *, int state), void *data);
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void nouveau_gpio_isr_del(struct drm_device *, int idx, u8 tag, u8 line,
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void (*)(void *, int state), void *data);
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struct nouveau_i2c_port *nouveau_i2c_find(struct drm_device *, u8);
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bool nouveau_probe_i2c_addr(struct nouveau_i2c_port *, int addr);
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struct i2c_adapter *nouveau_i2c_adapter(struct nouveau_i2c_port *);
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int nouveau_i2c_identify(struct drm_device *dev, const char *what,
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struct i2c_board_info *info,
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bool (*match)(struct nouveau_i2c_port *,
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struct i2c_board_info *), int index);
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int auxch_rd(struct drm_device *, struct nouveau_i2c_port *, u32, u8 *, u8);
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int auxch_wr(struct drm_device *, struct nouveau_i2c_port *, u32, u8 *, u8);
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struct nvbios_pll;
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struct nouveau_pll_vals;
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u32 get_pll_register(struct drm_device *dev, u32 type);
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int get_pll_limits(struct drm_device *, u32, struct nvbios_pll *);
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int setPLL(struct drm_device *, u32 reg, u32 clk);
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int nouveau_calc_pll_mnp(struct drm_device *, struct nvbios_pll *,
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int, struct nouveau_pll_vals *);
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int nva3_calc_pll(struct drm_device *dev, struct nvbios_pll *info, u32 freq,
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int *N, int *fN, int *M, int *P);
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int nouveau_hw_setpll(struct drm_device *, u32, struct nouveau_pll_vals *);
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struct dcb_output;
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void nouveau_bios_run_init_table(struct drm_device *, u16, struct dcb_output *, int);
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void nouveau_bios_init_exec(struct drm_device *, u16);
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void nv_intr(struct drm_device *);
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bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
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uint32_t reg, uint32_t mask, uint32_t val);
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bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
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uint32_t reg, uint32_t mask, uint32_t val);
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bool nouveau_wait_cb(struct drm_device *, u64 timeout,
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bool (*cond)(void *), void *);
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u64 nv_timer_read(struct drm_device *);
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int nvfb_tile_nr(struct drm_device *);
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void nvfb_tile_init(struct drm_device *, int, u32, u32, u32, u32);
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void nvfb_tile_fini(struct drm_device *, int);
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void nvfb_tile_prog(struct drm_device *, int);
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struct nouveau_fb_tile *nvfb_tile(struct drm_device *, int);
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struct nouveau_mem;
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int nvfb_vram_get(struct drm_device *dev, u64 size, u32 align, u32 ncmin,
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u32 memtype, struct nouveau_mem **pmem);
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void nvfb_vram_put(struct drm_device *dev, struct nouveau_mem **pmem);
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bool nvfb_flags_valid(struct drm_device *dev, u32);
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u64 nvfb_vram_sys_base(struct drm_device *);
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u64 nvfb_vram_size(struct drm_device *);
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int nvfb_vram_type(struct drm_device *);
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int nvfb_vram_rank_B(struct drm_device *);
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void nv50_fb_vm_trap(struct drm_device *, int);
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struct nouveau_gpuobj *nvimem_ramro(struct drm_device *);
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struct nouveau_gpuobj *nvimem_ramfc(struct drm_device *);
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int _nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_gpuobj *par,
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int size, int align, u32 flags,
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struct nouveau_gpuobj **pboj);
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u32 nv_ri32(struct drm_device *, u32);
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void nv_wi32(struct drm_device *, u32, u32);
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u32 nvimem_reserved(struct drm_device *);
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void nvimem_flush(struct drm_device *);
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void _nv50_vm_flush_engine(struct drm_device *dev, int engine);
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int _nouveau_vm_new(struct drm_device *, u64 offset, u64 length,
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u64 mm_offset, struct nouveau_vm **);
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struct nouveau_vma;
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int nouveau_gpuobj_map_bar(struct nouveau_gpuobj *, u32, struct nouveau_vma *);
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int
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nvbar_map(struct drm_device *dev, struct nouveau_mem *mem, u32 flags,
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struct nouveau_vma *vma);
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void
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nvbar_unmap(struct drm_device *dev, struct nouveau_vma *vma);
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struct nouveau_vm *
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nv04vm_ref(struct drm_device *dev);
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struct nouveau_gpuobj *
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nv04vm_refdma(struct drm_device *dev);
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void
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nvvm_engref(struct nouveau_vm *, int, int);
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int
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nvvm_spg_shift(struct nouveau_vm *);
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int
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nvvm_lpg_shift(struct nouveau_vm *);
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u32
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nv50_display_active_crtcs(struct drm_device *dev);
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u64 nvgpuobj_addr(struct nouveau_object *object);
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struct drm_device *
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nouveau_drv(void *drm);
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struct nouveau_channel *
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nvdrm_channel(struct drm_device *dev);
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struct mutex *
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nvchan_mutex(struct nouveau_channel *chan);
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#endif
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