Dinh Nguyen 56713da3ee clk: socfpga: allow for multiple parents on Arria10 periph clocks ...

There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.

Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

2016-02-22 14:17:37 -08:00

..

clk-gate-a10.c

clk: socfpga: allow for multiple parents on Arria10 periph clocks

2016-02-22 14:17:37 -08:00

clk-gate.c

clk: socfpga: switch to GENMASK()

2015-07-28 11:59:16 -07:00

clk-periph-a10.c

clk: socfpga: allow for multiple parents on Arria10 periph clocks

2016-02-22 14:17:37 -08:00

clk-periph.c

clk: socfpga: Add a second parent option for the dbg_base_clk

2015-08-24 16:49:03 -07:00

clk-pll-a10.c

clk: socfpga: fix __init annotation

2016-02-08 14:13:31 -08:00

clk-pll.c

clk: socfpga: Remove clk.h and clkdev.h includes

2015-07-20 11:11:14 -07:00

clk.c

clk: socfpga: add a clock driver for the Arria 10 platform

2015-05-21 15:16:04 -07:00

clk.h

clk: socfpga: Add a second parent option for the dbg_base_clk

2015-08-24 16:49:03 -07:00

Makefile

clk: socfpga: add a clock driver for the Arria 10 platform

2015-05-21 15:16:04 -07:00