Soren Brinkmann 0beb2bd36f ARM: zynq: PM: Enable DDR clock stop ...

The DDR controller can detect idle periods and leverage low power
features clock stop. When new requests occur, the DDRC resumes
normal operation.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

2014-09-16 12:55:07 +02:00

..

common.c

ARM: zynq: PM: Enable DDR clock stop

2014-09-16 12:55:07 +02:00

common.h

ARM: zynq: PM: Enable DDR clock stop

2014-09-16 12:55:07 +02:00

headsmp.S

ARM: zynq: Enable big-endian

2014-05-20 16:17:13 +02:00

hotplug.c

arm: zynq: hotplug: Remove unreachable code

2013-08-20 07:32:13 +02:00

Kconfig

PM / OPP: Remove ARCH_HAS_OPP

2014-07-23 00:51:30 +02:00

Makefile

ARM: zynq: PM: Enable DDR clock stop

2014-09-16 12:55:07 +02:00

Makefile.boot

ARM: 7022/1: allow to detect conflicting zreladdrs

2011-10-17 09:12:40 +01:00

platsmp.c

ARM: zynq: PM: Enable A9 internal clock gating feature

2014-09-16 12:55:05 +02:00

pm.c

ARM: zynq: PM: Enable DDR clock stop

2014-09-16 12:55:07 +02:00

slcr.c

ARM: zynq: Add support for SOC_BUS

2014-05-20 16:13:48 +02:00