Pull ARM DT updates from Olof Johansson:
"Device tree contents continue to be the largest branches we submit.
This time around, some of the contents worth pointing out is:
New SoC platforms:
- Freescale i.MX 7Solo
- Broadcom BCM23550
- Cirrus Logic EP7209 and EP7211 (clps711x platforms)_
- Hisilicon HI3519
- Renesas R8A7792
Some of the other delta that is sticking out, line-count wise:
- Exynos moves of IP blocks under an SoC bus, which causes a large
delta due to indentation changes
- a new Tegra K1 board: Apalis
- a bunch of small updates to many Allwinner platforms; new hardware
support, some cleanup, etc"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits)
ARM: dts: sun8i: Add dts file for inet86dz board
ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet
ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts
ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04
ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply
ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi
ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts
ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts
ARM: dts: sun5i: reference-design-tablet: Remove mention of q8
ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc
ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi
ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts
ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi
ARM: dts: at91: Don't build unnecessary dtbs
ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions
ARM: dts: at91: at91sam9g25ek: fix isi endpoint node
ARM: dts: at91: move isi definition to at91sam9g25ek
ARM: dts: at91: fix i2c-gpio node name
ARM: dts: at91: vinco: fix regulator name
ARM: dts: at91: ariag25 : fix onewire node
...
Pull spi updates from Mark Brown:
"Quite a lot of cleanup and maintainence work going on this release in
various drivers, and also a fix for a nasty locking issue in the core:
- A fix for locking issues when external drivers explicitly locked
the bus with spi_bus_lock() - we were using the same lock to both
control access to the physical bus in multi-threaded I/O operations
and exclude multiple callers.
Confusion between these two caused us to have scenarios where we
were dropping locks. These are fixed by splitting into two
separate locks like should have been done originally, making
everything much clearer and correct.
- Support for DMA in spi_flash_read().
- Support for instantiating spidev on ACPI systems, including some
test devices used in Windows validation.
- Use of the core DMA mapping functionality in the McSPI driver.
- Start of support for ThunderX SPI controllers, involving a very big
set of changes to the Cavium driver.
- Support for Braswell, Exynos 5433, Kaby Lake, Merrifield, RK3036,
RK3228, RK3368 controllers"
* tag 'spi-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (64 commits)
spi: Split bus and I/O locking
spi: octeon: Split driver into Octeon specific and common parts
spi: octeon: Move include file from arch/mips to drivers/spi
spi: octeon: Put register offsets into a struct
spi: octeon: Store system clock freqency in struct octeon_spi
spi: octeon: Convert driver to use readq()/writeq() functions
spi: pic32-sqi: fixup wait_for_completion_timeout return handling
spi: pic32: fixup wait_for_completion_timeout return handling
spi: rockchip: limit transfers to (64K - 1) bytes
spi: xilinx: Return IRQ_NONE if no interrupts were detected
spi: xilinx: Handle errors from platform_get_irq()
spi: s3c64xx: restore removed comments
spi: s3c64xx: add Exynos5433 compatible for ioclk handling
spi: s3c64xx: use error code from clk_prepare_enable()
spi: s3c64xx: rename goto labels to meaningful names
spi: s3c64xx: document the clocks and the clock-name property
spi: s3c64xx: add exynos5433 spi compatible
spi: s3c64xx: fix reference leak to master in s3c64xx_spi_remove()
spi: spi-sh: Remove deprecated create_singlethread_workqueue
spi: spi-topcliff-pch: Remove deprecated create_singlethread_workqueue
...
* acpi-tables:
ACPI: Rename configfs.c to acpi_configfs.c to prevent link error
ACPI: add support for loading SSDTs via configfs
ACPI: add support for configfs
efi / ACPI: load SSTDs from EFI variables
spi / ACPI: add support for ACPI reconfigure notifications
i2c / ACPI: add support for ACPI reconfigure notifications
ACPI: add support for ACPI reconfiguration notifiers
ACPI / scan: fix enumeration (visited) flags for bus rescans
ACPI / documentation: add SSDT overlays documentation
ACPI: ARM64: support for ACPI_TABLE_UPGRADE
ACPI / tables: introduce ARCH_HAS_ACPI_TABLE_UPGRADE
ACPI / tables: move arch-specific symbol to asm/acpi.h
ACPI / tables: table upgrade: refactor function definitions
ACPI / tables: table upgrade: use cacheable map for tables
Conflicts:
arch/arm64/include/asm/acpi.h
The current SPI code attempts to use bus_lock_mutex for two purposes. One
is to implement spi_bus_lock() which grants exclusive access to the bus.
The other is to serialize access to the physical hardware. This duplicate
purpose causes confusion which leads to cases where access is not locked
when a caller holds the bus lock mutex. Fix this by splitting out the I/O
functionality into a new io_mutex.
This means taking both mutexes in the DMA path, replacing the existing
mutex with the new I/O one in the message pump (the mutex now always
being taken in the message pump) and taking the bus lock mutex in
spi_sync(), allowing __spi_sync() to have no mutex handling.
While we're at it hoist the mutex further up the message pump before we
power up the device so that all power up/down of the block is covered by
it and there are no races with in-line pumping of messages.
Reported-by: Rich Felker <dalias@libc.org>
Tested-by: Rich Felker <dalias@libc.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Instead of hard-coding the register offsets put them into a struct
and set them in the probe function.
Signed-off-by: Jan Glauber <jglauber@cavium.com>
Tested-by: Steven J. Hill <steven.hill@cavium.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Storing the system clock frequency in struct octeon_spi avoids
calling the MIPS specific octeon_get_io_clock_rate() for every transfer.
Signed-off-by: Jan Glauber <jglauber@cavium.com>
Tested-by: Steven J. Hill <steven.hill@cavium.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Remove all calls to cvmx_read_csr()/cvmx_write_csr() and use
the portable readq()/writeq() functions.
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Signed-off-by: Jan Glauber <jglauber@cavium.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
wait_for_completion_timeout returns unsigned long not int so the check for
<= 0 should be == 0 here, and the type unsigned long. The function return
is set to -ETIMEDOUT to reflect the actual problem.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
wait_for_completion_timeout returns unsigned long not int so the check for
<= 0 should be == 0 here.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
The Rockchip SPI controller's length register only supports 16-bits,
yielding a maximum length of 64KiB (the CTRLR1 register holds "length -
1"). Trying to transfer more than that (e.g., with a large SPI flash
read) will cause the driver to hang.
Now, it seems that while theoretically we should be able to program
CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to
cause the core to choke, so stick with a maximum of 64K - 1 bytes --
i.e., 0xffff.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Return IRQ_NONE from the interrupt handler if the handler is running, but
no interrupt was detected. This allows the system to recover in case of an
interrupt storm due to an invalid interrupt configuration or faulty
hardware.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The Xilinx SPI driver can operate without an IRQ, but not every error
returned by platform_get_irq() means that no IRQ was specified. It will
also return an error if the IRQ specification is invalid or the IRQ
provider is not yet available (EPROBE_DEFER).
So instead of ignoring all errors only ignore ENXIO, which means no IRQ was
specified, and propagate all other errors to device driver core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Patch a9e93e8 has erroneously removed some comments which are
important to understand why the bus frequency is multiplied by
two during the spi transfer.
Reword the previous comment to a more appropriate message.
Suggested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The new compatible is related to the Samsung Exynos5433 SoC. The
difference between the previous is that in the exynos5433 the SPI
controller is driven by three clocks instead of only one.
The new clock (ioclk) is controlling the input/output clock
whenever the controller is slave or master.
The presence of the clock line is detected from the compatibility
structure (exynos5433_spi_port_config) as a boolean value.
The probe function checks whether the ioclk is present and if so,
it acquires.
The runtime suspend and resume functions will handle the clock
enabling and disabling as well.
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Linus Torvalds
Rafael J. Wysocki
Mark Brown
Jan Glauber
Steven J. Hill
Nicholas Mc Guire
Brian Norris
Lars-Peter Clausen
Andi Shyti