Make single kernel can be used on RBTX4927/37/38. Also make
some SoC-specific code independent from board-specific code.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Split out PCIC dependent code and SoC dependent code from board dependent
code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code.
Also fix some build problems on CONFIG_PCI=n.
As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards
and PCI66 support is available for all TX49 boards.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Move arch/mips/{jmr3927,tx4927,tx4938} into arch/mips/txx9/ tree.
This will help more code sharing and maintainance.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Declare pci_probe_only, etc. in asm-mips/pci.h file. This will fix
some sparse warnings.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
SGI-IP28 is running in so called slow mode, when kernel is started
from the PROM. PROM calls must be done in slow mode otherwise the
PROM will issue an error. To get better memory performance we now
switch to normal mode, when the PROM is no longer needed.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The third operand to 'ins' must be a constant int, not a register.
[Ralf: The bug was actually intensional. Some versions used to throw an
error under certain circumstances for code like:
static inline void f(unsigned nr, unsigned *p)
{
unsigned short bit = nr & 5;
if (__builtin_constant_p(bit)) {
__asm__ __volatile__ (" foo %0, %1" : "=m" (*p) : "i" (bit));
} else {
/* Do something else. */
}
}
because gcc was not able to figure out that the "i" constraint was possibly
at the early stage when the constraint are getting verified. The solution
was using "ri" instead of "i". The "ri" would keep gcc happy but in the
end for code generation always the "i" constraint would be satisfied. The
problem afair originally appeared in the i386 io.h and also hit it's mips
equivalent. From there the workaround spread to many of the inline
assembler functions.]
Signed-off-by: David Daney <ddaney@avtrex.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Document a few more register bits provided by the MB ASIC used on R4000SC
(KN04) and R4400SC (KN05) CPU daughtercards with the DECstation.
Reverse-engineered and not documented anywhere else to the best of my
knowledge. Bit names appended to the last underscore the same as reported
by the firmware in register dumps.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Never terribly functional or popular, plagued by hard to fix bugs the time
to say goodbye has more than arrived.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch fixes the following sparse warning:
<<<<<<<<
arch/mips/kernel/early_printk.c:35:13: warning: symbol 'setup_early_printk'
was not declared. Should it be static?
<<<<<<<<
The fix is to define a prototype of the setup_early_printk() function and
to include the appropriate header into arch/mips/kernel/early_printk.c.
[Ralf: Sorted includes again]
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The isa_slot_offset variable and its __ISA_IO_base macro is not used
anywhere anymore. It does not look like a decent interface per today's
standards either. Remove both including all places of initialization.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The branch optimization fixes in 2.6.21 introduced a bug in
atomic_sub_if_positive that causes it to return even when the sc
instruction fails. The result is that e.g. down_trylock becomes unreliable
as the semaphore counter is not always decremented.
Original MUA-shredded patch from Morten Larsen <mlarsen@broadcom.com>.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
After the common MIPS CPU interrupt controller (for irq0-7) was introduced
the Lasat boards didn't get their interrupts right, so nothing worked. The
old routines need to be offset by the new 8 hardware interrupts common to
all MIPS CPU's.
Signed-off-by: Thomas Horsten <thomas@horsten.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
In the conversion done in the commits
95c4eb3ef4484ca85da5c98780d358cffd546b90
9d360ab4a7
[MIPS] Alchemy: Renumber interrupts so irq_cpu can work.
one reserved interrupt on au1500 was missed. this broke the au1000 ethernet
driver.
Signed-off-by: Bruno Randolf <br1@einfach.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Atsushi Nemoto
Ralf Baechle
Thomas Bogendoerfer
David Daney
Maciej W. Rozycki
Manuel Lauss
Dmitri Vorobiev
Chen, Huacai
Thomas Horsten
Chris Dearman
bruno randolf
Vegard Nossum