The mandatory barriers (mb, rmb, wmb) are used even on uniprocessor
systems for things like ordering Normal Non-cacheable memory accesses
with DMA transfer (via Device memory writes). The current implementation
uses dmb() for mb() and friends but this is not sufficient. The DMB only
ensures the relative ordering of the observability of accesses by other
processors or devices acting as masters. In case of DMA transfers
started by writes to device memory, the relative ordering is not ensured
because accesses to slave ports of a device are not considered
observable by the DMB definition.
A DSB is required for the data to reach the main memory (even if mapped
as Normal Non-cacheable) before the device receives the notification to
begin the transfer. Furthermore, some L2 cache controllers (like L2x0 or
PL310) buffer stores to Normal Non-cacheable memory and this would need
to be drained with the outer_sync() function call.
The patch also allows platforms to define their own mandatory barriers
implementation by selecting CONFIG_ARCH_HAS_BARRIERS and providing a
mach/barriers.h file.
Note that the SMP barriers are unchanged (being DMBs as before) since
they are only guaranteed to work with Normal Cacheable memory.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The L2x0 cache controllers need to explicitly drain their write buffer
even for Normal Noncacheable memory accesses.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch introduces the outer_cache_fns.sync function pointer together
with the OUTER_CACHE_SYNC config option that can be used to drain the
write buffer of the outer cache.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
To avoid #include collisions with subsequent patches in the series, this
patch moves the outer_cache definitions to a separate asm/outercache.h
file.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* 'sh/for-2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
sh: Silence unintialized variable warnings in dwarf unwinder.
sh: Tidy up a couple of section mismatches.
sh: Fix build after dynamic PMB rework
sh: Replace unsafe manipulation of MMUCR
sh: Flush ITLB too in PTEAEX's flush_tlb_page()
sh64: Remove long unused mid_sched macro
SH: remove superfluous warning from the serial driver
SH: fix SCIFA SCASCR register bit definitions
serial: sh-sci: fix SH-Mobile SH breakage
sh: Add watch-dog register address for SH7722/SH7723/SH7724
sh: ms7724: Add tiny-document for sound
sh: mach-ecovec24: Add i2c_put_adapter on sh_eth_init
Fix two bugs with the kernel image compression:
1) reset the bss section of the compressed vmlinux
2) clear the high half of the registers for 64 bit early enough
for the decompression step
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
commit 024914477e "memcg: move charges of anonymous
swap" revealed that the 1 byte and 2 byte cmpxchg is currently broken:
arch/s390/include/asm/system.h: Assembler messages:
arch/s390/include/asm/system.h:241: Error: junk at end of line: `(%r5)'
make[1]: *** [mm/page_cgroup.o] Error 1
make[1]: *** Waiting for unfinished jobs....
It turned out that commit 987bcdacb1 ([S390] use
inline assembly contraints available with gcc 3.3.3) broke the inline assembly.
The or operands are now in constraint 3 and 4 instead of 2 and 3.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
The intermediate lowcore for CONFIG_SMP is allocated using a call to
__alloc_bootmem() with a goal of 0. That however doesn't guarantee that
the allocated piece of memory is below 2GB.
Instead we should call __alloc_bootmem_low().
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
To save the registers for all CPUs a sigp "store status" is done that
stores the registers to address absolute zero. To access storage at
absolute zero, normally the address of the prefix register of the
accessing CPU has to be used. This does not work when large pages are
active (currently only under LPAR). In order to fix that problem,
instead of memcpy memcpy_real is used, which switches to real mode
where prefixing works.
Signed-off-by: Michael Holzheu <holzheu@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
"Input: add KEY_WPS_BUTTON definition" introduced
a generic keycode for WPS input events.
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Commit "Input: add KEY_WPS_BUTTON definition"
added a generic keycode for WPS button.
Let's use it, instead of "F1" mapping.
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
The parent rb_node needs to be initialized to shut up the compiler, even
though we're unlikely to ever hit this issue at run time.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
select_idle_routine() and register_sh_pmu() both needed their annotations
fixed up to silence section mismatch warnings.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
set_pmb_entry() is now only used by a function that is wrapped in #ifdef
CONFIG_PM, so wrap set_pmb_entry() in CONFIG_PM too.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Setting the TI in MMUCR causes all the TLB bits in MMUCR to be
cleared. Unfortunately, the TLB wired bits are also cleared when setting
the TI bit, causing any wired TLB entries to become unwired.
Use local_flush_tlb_all() which implements TLB flushing in a safer
manner by using the memory-mapped TLB registers. As each CPU has its own
PMB the modifications in pmb_init() only affect the local CPU, so only
flush the local CPU's TLB.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
flush_tlb_page() can be used to flush TLB entries that map executable
pages. Therefore, we need to ensure that the ITLB is also flushed in
local_flush_tlb_page().
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
interruptible_sleep_on() is referenced for use in the mid_sched macro
which is not used anywhere. Remove reference and macro as well as the
comment which appears to belong with them.
Signed-off-by: Andreas Bombe <aeb@debian.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Commit 3f6da39053
(perf: Rework and fix the arch CPU-hotplug hooks) broke suspend to
RAM on my HP nx6325 (and most likely on other AMD-based boxes too)
by allowing amd_pmu_cpu_offline() to be executed for CPUs that are
going offline as part of the suspend process. The problem is that
cpuhw->amd_nb may be NULL already, so the function should make sure
it's not NULL before accessing the object pointed to by it.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This fixes a warning when booting 2.6.34-rc2:
[ 26.619814] ------------[ cut here ]------------
[ 26.624604] WARNING: at fs/proc/generic.c:316 __xlate_proc_name+0xac/0xc0()
[ 26.631555] name 'on/off button'
[ 26.634753] Modules linked in:
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Cc: Sven Neumann <s.neumann@raumfeld.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Catalin Marinas
Linus Torvalds
Martin Schwidefsky
Christian Borntraeger
Heiko Carstens
Michael Holzheu
Christian Lamparter
Russell King
Paul Mundt
Matt Fleming
Andreas Bombe
Kuninori Morimoto
Rafael J. Wysocki
Daniel Mack
Huang Weiyi