Commit Graph

55 Commits

Author SHA1 Message Date
Ralf Baechle e001e52801 [MIPS] Replace use of stext with _stext.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31 21:35:28 +01:00
Fuxin Zhang 2a21c7300b [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10 17:33:02 +01:00
Ralf Baechle 617667ba72 [MIPS] Avoid dupliate D-cache flush on R400C / R4400 SC and MC variants.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30 01:14:48 +00:00
Atsushi Nemoto 0550d9d13e [MIPS] Remove redundant r4k_blast_icache() calls
r4k_flush_cache_all() and r4k_flush_cache_mm() case: these are noop if
the CPU did not have dc_aliases.  It would mean we do not need to care
about icache here.

r4k_flush_cache_range case: if r4k_flush_cache_mm() did not need to
care about icache, it would be same for this function.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30 01:14:48 +00:00
Atsushi Nemoto c59a0f15be [MIPS] Remove __flush_icache_page
__flash_icache_page is unused, so kill it.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-01 23:16:58 +01:00
Ralf Baechle a00f631018 [MIPS] c-r4k: Convert init functions from inline to __init.
With more recent compilers inline doesn't necessarily means a function
will always be inlined.  So leave that decission to the compiler and
make the function as __init.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27 13:37:44 +01:00
Atsushi Nemoto f6502791d7 [MIPS] Do not use drop_mmu_context to flusing other task's VIPT I-cache.
c-r4k.c and c-sb1.c use drop_mmu_context() to flush virtually tagged
I-caches, but this does not work for flushing other task's icache.  This
is for example triggered by copy_to_user_page() called from ptrace(2).
Use indexed flush for such cases.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27 13:37:37 +01:00
Ralf Baechle 585fa72493 [MIPS] Retire flush_icache_page from mm use.
On the 34K the redundant cache operations were causing excessive stalls
resulting in realtime code running on the second VPE missing its deadline.
For all other platforms this patch is just a significant performance
improvment as illustrated by below benchmark numbers.

Processor, Processes - times in microseconds - smaller is better
------------------------------------------------------------------------------
Host                 OS  Mhz null null      open slct sig  sig  fork exec sh
                             call  I/O stat clos TCP  inst hndl proc proc proc
--------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
25Kf      2.6.18-rc4     533 0.49 1.16 7.57 33.4 30.5 1.34 12.4 5497 17.K 54.K
25Kf      2.6.18-rc4-p   533 0.49 1.16 6.68 23.0 30.7 1.36 8.55 5030 16.K 48.K
4Kc       2.6.18-rc4      80 4.21 15.0 131. 289. 261. 16.5 258. 18.K 70.K 227K
4Kc       2.6.18-rc4-p    80 4.34 13.1 128. 285. 262. 18.2 258. 12.K 52.K 176K
34Kc      2.6.18-rc4      40 5.01 14.0 61.6 90.0 477. 17.9 94.7 29.K 108K 342K
34Kc      2.6.18-rc4-p    40 4.98 13.9 61.2 89.7 475. 17.6 93.7 8758 44.K 158K
BCM1480   2.6.18-rc4     700 0.28 0.60 3.68 5.92 16.0 0.78 5.08 931. 3163 15.K
BCM1480   2.6.18-rc4-p   700 0.28 0.61 3.65 5.85 16.0 0.79 5.20 395. 1464 8385
TX49-16K  2.6.18-rc3     197 0.73 2.41 19.0 37.8 82.9 2.94 17.5 4438 14.K 56.K
TX49-16K  2.6.18-rc3-p   197 0.73 2.40 19.9 36.3 82.9 2.94 23.4 2577 9103 38.K
TX49-32K  2.6.18-rc3     396 0.36 1.19 6.80 11.8 41.0 1.46 8.17 2738 8465 32.K
TX49-32K  2.6.18-rc3-p   396 0.36 1.19 6.82 10.2 41.0 1.46 8.18 1330 4638 18.K
    
Original patch by me with enhancements by Atsushi Nemoto.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
2006-09-27 13:37:34 +01:00
Ralf Baechle df586d59a4 [MIPS] c-r4k: Typo fix.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27 13:37:23 +01:00
Yoichi Yuasa 2874fe5533 [MIPS] vr41xx: Replace magic number for P4K bit with symbol.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:11 +01:00
Yoichi Yuasa 1058ecda9b [MIPS] vr41xx: Changed workaround to recommended method
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:11 +01:00
Yoichi Yuasa 4e8ab36182 [MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:06 +01:00
Ralf Baechle fc5d2d279f [MIPS] Use the proper technical term for naming some of the cache macros.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:04 +01:00
Jörn Engel 6ab3d5624e Remove obsolete #include <linux/config.h>
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-30 19:25:36 +02:00
Ralf Baechle 2e78ae3f48 [MIPS] 74K: Assume it will also have an AR bit in config7
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:54 +01:00
Ralf Baechle beab375a48 [MIPS] Treat CPUs with AR bit as physically indexed.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:54 +01:00
Chris Dearman 73f403527b [MIPS] Fix handling of 0 length I & D caches.
Don't ask.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:53 +01:00
Chris Dearman 9318c51acd [MIPS] MIPS32/MIPS64 secondary cache management
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:52 +01:00
Sergei Shtylyov 9370b35175 [MIPS] Save write-only Config.OD from being clobbered
Save the Config.OD bit from being clobbered by coherency_setup(). This
bit, when set, fixes various errata in the early steppings of Au1x00
SOCs.  Unfortunately, the bit was write-only on the most early of them.
In addition, also restore the bit after a wakeup from sleep.
    
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-06 00:15:13 +01:00
Kumba 44d921b246 [MIPS] Treat R14000 like R10000.
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:35 +01:00
Ralf Baechle 7f3f1d01a9 [MIPS] Fix deadlock on MP with cache aliases.
A proper fix would involve introducing the notion of shared caches but
at this stage of 2.6.17 that's going to be too intrusive and not needed
for current hardware; aside I think some discussion will be needed.

So for now on the affected SMP configurations which happen to suffer from
cache aliases we make use of the fact that a single cache will be shared
by all processors.  This solves the deadlock issue and will improve
performance by getting rid of the smp_call_function overhead.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:33 +01:00
Nigel Stephens 98a41de99a [MIPS] Add missing 34K processor IDs
The 34K is very much like a 24K on steroids.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:30 +01:00
Atsushi Nemoto 3c68da798a [MIPS] Use __ffs() instead of ffs() for waybit calculation.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:30 +02:00
Ralf Baechle 7e3bfc7cfc [MIPS] Handle IDE PIO cache aliases on SMP.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:29 +02:00
Atsushi Nemoto 67a3f6de93 [MIPS] Fix tx49_blast_icache32_page_indexed.
Fix the cache index value in tx49_blast_icache32_page_indexed().
This is a damage by de62893bc0 commit.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:21 +02:00