so the page will be flushed on unmap on ARCH which need it.
Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
Since commit 8dfd0374be ("MMC core: limit
minimum initialization frequency to 400kHz") MMC core checks for minimum
frequency, and that causes following messages flood when using eSDHC
controllers:
...
mmc0: Minimum clock frequency too high for identification mode
mmc0: Minimum clock frequency too high for identification mode
...
The warnings are legitimate, since if we'd use 133 MHz clocks for standard
SDHCI controllers, we'd not able to scale frequency down to 400 kHz.
But eSDHC controllers have a non-standard SD clock management, so we can
divide clock by 256 * 16, not just 256.
This patch introduces get_min_clock() callback for sdhci core and
implements it for sdhci-of driver, and thus fixes the issue.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Cc: Matt Fleming <matt@console-pimps.org>
Cc: Ian Molton <ian@mnementh.co.uk>
Cc: "Roberto A. Foglietta" <roberto.foglietta@gmail.com>
Cc: Pierre Ossman <drzeus@drzeus.cx>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Standard data flow for MMC/SD/SDIO cards requires that the mvsdio
controller be set for big endian operation. This is causing problems
with buffers which length is not a multiple of 4 bytes as the last
partial word doesn't get shifted all the way and stored properly in
memory. Let's compensate for this.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
CC: stable@kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Add a new spi_master.flags word listing constraints relevant to that
controller. Define the first constraint bit: a half duplex restriction.
Include that constraint in the OMAP1 MicroWire controller driver.
Have the mmc_spi host be the first customer of this flag. Its coding
relies heavily on full duplex transfers, so it must fail when the
underlying controller driver won't perform them.
(The spi_write_then_read routine could use it too: use the
temporarily-withdrawn full-duplex speedup unless this flag is set, in
which case the existing code applies. Similarly, any spi_master
implementing only SPI_3WIRE should set the flag.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
The SDHCI controller found in the VX855ES requires 10ms
delay between applying power and applying clock.
This issue has been discovered and documented by the OLPC XO1.5 team.
Signed-off-by: Harald Welte <HaraldWelte@viatech.com>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
This was missed in the DMA changes during the s3c24xx
updates in commit 8970ef47d5.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
This adds the via-sdmmc driver for the SD/MMC-controller of VIA,
which is found in a number of recent integrated VIA chipset
products.
Signed-off-by: Harald Welte <HaraldWelte@viatech.com>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
Some hosts (hardware configurations, or particular SD/MMC slots) may
not support 4-bit bus. For example, on MPC8569E-MDS boards we can
switch between serial (1-bit only) and nibble (4-bit) modes, thought
we have to disable more peripherals to work in 4-bit mode.
Along with some small core changes, this patch modifies sdhci-of
driver, so that now it looks for "sdhci,1-bit-only" property in the
device-tree, and if specified we enable a proper quirk.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
Add quirk to show the controller cannot do multi-block IO.
This is mainly for the Samsung SDHCI controller that currently
cannot manage to do multi-block PIO without timing out.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
Update the ADMA error reporting to not only show the
overall controller state but also to print the ADMA
descriptor list.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
Add support for the 'HSMMC' block(s) in the Samsung SoC
line. These are compatible with the SDHCI driver so add
the necessary setup and driver binding for the platform
devices.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc: (25 commits)
atmel-mci: add MCI2 register definitions
atmel-mci: Integrate AT91 specific definition in header file
tmio_mmc: allow compilation for ASIC3
mmc_block: do not DMA to stack
sdhci: Print ADMA status and pointer on debug
tmio_mmc: fix clock setup
tmio_mmc: map SD control registers after enabling the MFD cell
tmio_mmc: correct probe return value for num_resources != 3
tmio_mmc: don't use set_irq_type
tmio_mmc: add bus_shift support
MFD,mmc: tmio_mmc: make HCLK configurable
mmc_spi: don't use EINVAL for possible transmission errors
cb710: more cleanup for the DEBUG case.
sdhci: platform driver for SDHCI
mxcmmc: remove frequency workaround
cb710: handle DEBUG define in Makefile
cb710: add missing parenthesis
cb710: fix printk format string
mmc: Driver for CB710/720 memory card reader (MMC part)
pxamci: add regulator support.
...
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (417 commits)
MAINTAINERS: EB110ATX is not ebsa110
MAINTAINERS: update Eric Miao's email address and status
fb: add support of LCD display controller on pxa168/910 (base layer)
[ARM] 5552/1: ep93xx get_uart_rate(): use EP93XX_SYSCON_PWRCNT and EP93XX_SYSCON_PWRCN
[ARM] pxa/sharpsl_pm: zaurus needs generic pxa suspend/resume routines
[ARM] 5544/1: Trust PrimeCell resource sizes
[ARM] pxa/sharpsl_pm: cleanup of gpio-related code.
[ARM] pxa/sharpsl_pm: drop set_irq_type calls
[ARM] pxa/sharpsl_pm: merge pxa-specific code into generic one
[ARM] pxa/sharpsl_pm: merge the two sharpsl_pm.c since it's now pxa specific
[ARM] sa1100: remove unused collie_pm.c
[ARM] pxa: fix the conflicting non-static declarations of global_gpios[]
[ARM] 5550/1: Add default configure file for w90p910 platform
[ARM] 5549/1: Add clock api for w90p910 platform.
[ARM] 5548/1: Add gpio api for w90p910 platform
[ARM] 5551/1: Add multi-function pin api for w90p910 platform.
[ARM] Make ARM_VIC_NR depend on ARM_VIC
[ARM] 5546/1: ARM PL022 SSP/SPI driver v3
ARM: OMAP4: SMP: Update defconfig for OMAP4430
ARM: OMAP4: SMP: Enable SMP support for OMAP4430
...
New revision of Atmel MCI interface adds new features. This is a update of
register definition in header file. This new MCI IP is called MCI2.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
The MCI IP is shared among AVR32 and AT91 SOCs.
AT91 has specific bit definitions in the user interface of MCI SD/MMC IP.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
In the write recovery routine, the data to get from the card
is allocated from the stack. The DMA mapping documentation says
explicitly stack memory is not mappable by any of the DMA calls.
Change to using kmalloc() to allocate the memory for the result
from the card and then free it once we've finished with the
transaction.
[ Changed to GFP_KERNEL allocation - Pierre Ossman ]
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
If using ADMA, then we should print the ADMA error
and current pointer in sdhci_dumpregs() when any
debug is requested.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
This patch fixes the clock setup in tmio_mmc.
* Incorrect divider setting
* Cruft written to the clock registers (seemingly harmless but Not
Good (tm))
It also eliminates some unnecessary ifs and tidies the loop syntax.
Thanks to Philipp Zabel who discovered the divider issue, commenting
"Except for the SDCLK = HCLK (divider bypassed) case, the clock
setting resulted in double the requested frequency.
The smallest possible frequency (f_max/512) is configured with
a divider setting 0x80, not 0x40."
Signed-off-by: Ian Molton <ian@mnementh.co.uk>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
ASIC3 can disable the memory, so we need to wait for mfd_cell->enable
to enable the memory before we can map the SD control registers.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Acked-by: Ian Molton <ian@mnementh.co.uk>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
Sebastian Andrzej Siewior
Anton Vorontsov
Nicolas Pitre
Russell King
Matt Reimer
David Brownell
Pierre Ossman
Harald Welte
Ben Dooks
Linus Torvalds
Nicolas Ferre
Philipp Zabel
Ian Molton