The simple example provided in the comments for nand_id_has_period()
actually has a period of 3, not 2. Silly mistake...
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The {read,write}s{b,w,l} operations are not defined by all
architectures and are being removed from the asm-generic/io.h
interface.
This patch replaces the usage of these string functions in the mtd
gpio accessors with io{read,write}{8,16,32}_rep calls instead.
Signed-off-by: Matthew Leach <matthew@mattleach.net>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
If you create a block2mtd device that is larger than main memory,
and write to all of it, then lots of pages will be dirtied but
they will never be flushed out as nothing calls any variant of
balance_dirty_pages.
It would be nice to call set_page_dirty_balance(), but that isn't exported,
so just call balance_dirty_pages_ratelimited() directly.
Signed-off-by: NeilBrown <neilb@suse.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
It could happen (1 out of 100 times) that NAND did not start up
correctly after warm rebooting, so the kernel could not find the UBI or
DMA timed out due to a stalled BCH. When resetting BCH together with
GPMI, the issue could not be observed anymore (after 10000+ reboots). We
probably need the consistent state already before sending any command to
NAND, even when no ECC is needed. I chose to keep the extra reset for
BCH when changing the flash layout to be on the safe side.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Huang Shijie <b32955@freescale.com>
Cc: stable@vger.kernel.org
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This patch does two things related to reading the factory badblock table during
initialization: (1) fix error where a non-zero return code from
docg4_read_page() is assumed to be an error (it was later changed to be
max_bitflips; thanks to Brian Norris for bringing this to my attention a while
back), and (2) if there is an error reading the factory bbt, it tries reading
another (redundant) factory bbt table.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The controller on the docg4 has a "reliable" mode, where consecutive 2k pages
are used in parallel. The initial program loader (IPL) on my Treo 680 expects
the secondary program loader (SPL) to be written in this mode. This patch adds
support for writing data in reliable mode, by way of a module parameter.
Support for reading in this mode (as the IPL does) is not supported yet, but
alternate (even-numbered) 2k pages written in reliable mode can be read normally
(odd-numbered pages will contain junk and generate ecc errors).
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The cmdline is the easiest to change source of information. Thus
let it take precedence over 'RedBoot' and 'ofpart'. This makes the
mxc_nand driver to be in sync with all other NAND drivers that support
'cmdlinepart' partition parsing.
Also change 'const char *' to 'const char const *' as advised by checkpatch.pl
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
If nand_scan_ident() or nand_scan_tail() fails, the NAND chip may have
been deselected and the clock already disabled. Thus, check 'clk_act'
in the error path to decide whether the clock still needs to be
disabled.
This fixes a:
|WARNING: at drivers/clk/clk.c:472 __clk_disable+0x3c/0x78()
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
It's more user friendly to report debug information and statistics
through debugfs, than to use printing facilites.
This patch introduces a very minimal debugfs infrastructure
and moves eraseblock wear report to an entry located at:
/sys/kernel/debug/nandsim/wear_report
This means we can remove rptwear option and just let
the user get the wear report when we needs to.
Signed-off-by: Ezequiel Garcia <elezegarcia@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This patch solves a NULL pointer dereference, this may occur if the tuple
is not mappable (jumps to continue in the for-loop). Out of the loop
possible results are:
- info->list_size == 0 if no of the tuples is mappable
- info->list_size == 1
- info->list_size > 1
If no one of the supplied tuples is mappable (info->list_size == 0) and
info->cmtd will not be set. But it is used in mtd_device_parse_register, OOPS!
actually it should generate an error in this case!
Signed-off-by: Anton Prins <anton.prins@nl.bosch.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
If we set oobdelta to zero then we will either return -EINVAL or hit
a divide (modulus) by zero on the next line when we check
"(ooblen % oobdelta)". It's better to just return -EINVAL here instead.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This patch fix pmecc's read_page() to return maximum number of bitflips, 0 if uncorrectable.
In the commit: 3f91e94f7f ("mtd: nand: read_page() returns max_bitflips ()"),
The ecc.read_page() is changed to return the maximum number of bitflips.
And when meet uncorrectable bitflips it needs to return 0.
See the comment in nand.h:
* @read_page: function to read a page according to the ECC generator
* requirements; returns maximum number of bitflips corrected in
* any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
When working on a problem with some flash chips that lock up during
write-buffer operations, I think there may be a bug in the linux
handling of chips using cfi_cmdset_0002.c.
The datasheets I have found for a number of these chips all specify that
when aborting a write-buffer command, it is not enough to use the
standard reset. Rather a "write-to-buffer-reset command" is needed.
This command is quite similar for all chips, the main variance seem to
be if the final 0xF0 can go to any address or must go to addr_unlock1.
The bug is then in the recovery handling when timing out at the end of
do_write_buffer, where using the normal reset command is not sufficient.
Without this change, if the write-buffer command fails then any
following operations on the flash also fail.
Signed-off-by: Harald Nordgard-Hansen <hhansen@pvv.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
- NAND_CMD_READID want an address that it is not scaled on x16 device (it is always 0x20)
- NAND_CMD_PARAM want 8 bits data
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The driver call nand_scan_ident in 8 bit mode, then
readid or onfi detection are done (and detect bus width).
The driver should update its bus width before calling nand_scan_tail.
This work because readid and onfi are read work 8 byte mode.
Note that nand_scan_ident send command (NAND_CMD_RESET, NAND_CMD_READID, NAND_CMD_PARAM), address and read data
The ONFI specificication is not very clear for x16 device if high byte of address should be driven to 0,
but according to [1] it should be ok to not drive it during autodetection.
[1]
3.3.2. Target Initialization
[...]
The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus.
The host shall not issue commands that use a word data width on x16 devices until the host
determines the device supports a 16-bit data bus width in the parameter page.
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
nand_wait_ready timeout should not assume HZ=100.
Make it independent of HZ value by using msecs_to_jiffies.
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
There are two reasons to remove the "chip" parameter in nand_get_device():
[1] The nand_release_device() does not have the "chip" parameter.
[2] We can get the nand_chip by the mtd->priv field.
This patch removes the "chip" parameter in nand_get_device().
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The nand_get_device() does not select the chip, but nand_release_device()
does de-select the chip. It is really strange.
With the current code, nand_sync() will de-select the chip, even if the chip
has never been selected.
To make the balance of select/de-select chip, it's better to remove the
de-select chip code in nand_release_device() which makes the code more
clear.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Micron N25Q128 has two types of flash:
- One is for 1.8v supply voltage, prefixed with "n25q128a11" and the jedec
code is 0x20bb18.
- Another is for 3v supply voltage, prefixed with "n25q128a13" and the jedec
code is 0x20ba18.
So modify the original type info and add another type for Micron N25Q128.
Signed-off-by: Liming Wang <walimisdev@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Brian Norris
Matthew Leach
NeilBrown
Wolfram Sang
Mike Dunn
Lothar Waßmann
Ezequiel Garcia
Anton Prins
Dan Carpenter
Rafał Miłecki
Christian Herzig
Josh Wu
Harald Nordgard-Hansen
Matthieu CASTET
Huang Shijie
Liming Wang