The SDK7786 FPGA has secondary control over the PCIe clocks, specifically
relating to the slots and oscillator. This ties the FPGA clocks in to the
clock framework and balances the refcounting similar to how the primary
on-chip clocks are managed. While the on-chip clocks are per-port, the
FPGA clock enable/disable is global for the entire block.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
SDK7786 supports connecting either slot3 or 4 to the same PCIe port by
way of FPGA muxing. By default the vertical slot 3 on the baseboard is
enabled, so this adds in a command line option for forcibly enabling the
slot 4 edge connector.
If nothing has been specified on the command line, we fall back to
reading the resistor values for card presence to figure out where to
route the port to.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This copies the pci_config_lock idea from x86 over, allowing us to kill
off a couple of existing private locks. At the same time, these need to
be converted to raw spinlocks for -rt kernels, so we make that change at
the same time. This should make it easier for future parts to get the
locking right instead of inevitable ending up with lock type mismatches.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This gets each port handling its MSTP bit, as well as moving the PHY
clock management in to the clock framework.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Some of the existing code is flipping between __raw_xxx() and
pci_{read,write}_reg(). As the latter are just wrappers for the former,
flip over to using them consistently.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Presently we error out if a link is disabled and simply drop the port
registration outright. This follows the PPC changes and simply reports on
the link state on boot, leaving the port registered, in order to more
easily deal with hotplug on future parts.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
These settings are properly propagated by the hardware already, so
there's no need to bother with them manually.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The SH7786 PCIe is presently unable to enumerate itself in root complex
mode, and has no visibility through either type 0 or type 1 accesses,
despite having a mostly sensible extended config space for each port.
Attempts to generate type 0 or type 1 config cycles result in completer
aborts, so we're ultimately forced to use SuperHyway transactions
instead.
As each port has a single port <-> device mapping that resolves for any
PCI_SLOT definition, we simply hijack devfn 0 for the SuperHyway
transaction and bump up the devfn limit.
With enumeration of the root complex now possible, we also need to insert
an early fixup to hide the BARs from the kernel. With all of that done,
it's now possible to use the pcieport services with all of the PCIe
ports, which is the first step to power management support.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Previously these IDs were only used by one driver, so there was not much
need for having them generically defined. Now that this will no longer
hold true, move them over.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The spec suggests waiting up to 500ms for the PHY to settle before
testing link state, but practice shows that 100ms is sufficient (this is
the delay value we also use on the other SH-4A PCI controllers, too).
This makes device detection much more reliable, although in the future it
should be a bit faster to simply serialize with a TLP IRQ.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Now that the resource assignment issues are resolved, we can finally wire
up the small third memory window -- in the future we may reclaim this for
MSI.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
An IORESOURCE_IO was missing here, which meant that we weren't properly
establishing the I/O window for this particular slot. With this
corrected, cards with I/O BARs have them actually assigned and
accessible.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Certain memory windows are only available for 32-bit space, so skip over
these in 29-bit mode. This will severely restrict the amount of memory
that can be mapped, but since a boot loader bug makes booting in 29-bit
mode close to impossible anyways, everything is ok.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This bumps up the low address to match the physical memory windows for
SHway<->PCIe transfers. The previous implementation was banking on a 1:1
virt<->phys SHway mapping, which doesn't apply here.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
SH7786 PCIe has 1 slot per port, but no specific restriction on function.
Relax the devfn restriction and look to the slot number instead when
configured as a root complex.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This brings the clocking and register setting in line with the somewhat
factually ambiguous specification.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This enables support for type 1 config space accesses on the SH7786
PCI controller. At the same time, add in some extra sanity checks for
controller asserted errors.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
create_proc_read_entry() may fail, if so return -ENOMEM.
Signed-off-by: Kulikov Vasiliy <segooon@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Paul Mundt
Matt Fleming
Kulikov Vasiliy