Commit Graph

24822 Commits

Author SHA1 Message Date
Christian König cc1de6e800 drm/amdgpu: fix issue with overlapping userptrs
Otherwise we could try to evict overlapping userptr BOs in get_user_pages(),
leading to a possible circular locking dependency.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2016-02-10 14:07:52 -05:00
Nicolai Hähnle f6ff4f67cd drm/radeon: hold reference to fences in radeon_sa_bo_new
An arbitrary amount of time can pass between spin_unlock and
radeon_fence_wait_any, so we need to ensure that nobody frees the
fences from under us.

Based on the analogous fix for amdgpu.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
2016-02-10 14:07:44 -05:00
Nicolai Hähnle b19763d0d8 drm/amdgpu: remove unnecessary forward declaration
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
2016-02-10 14:07:38 -05:00
Nicolai Hähnle a8d81b3626 drm/amdgpu: hold reference to fences in amdgpu_sa_bo_new (v2)
An arbitrary amount of time can pass between spin_unlock and
fence_wait_any_timeout, so we need to ensure that nobody frees the
fences from under us.

A stress test (rapidly starting and killing hundreds of glxgears
instances) ran into a deadlock in fence_wait_any_timeout after
about an hour, and this race condition appears to be a plausible
cause.

v2: agd: rebase on upstream

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
2016-02-10 14:07:31 -05:00
Flora Cui ca19852884 drm/amdgpu: fix s4 resume
No need to re-init asic if it's already been initialized.
Skip IB tests since kernel processes are frozen in thaw.

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2016-02-10 14:07:13 -05:00
Alex Deucher db5cffcd2b drm/amdgpu/cz: plumb pg flags through to powerplay
Enable vce and uvd pg based on single set of pg flags.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:48 -05:00
Alex Deucher 52b52a8781 drm/amdgpu/tonga: plumb pg flags through to powerplay
Enable vce and uvd pg based on single set of pg flags.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:48 -05:00
Alex Deucher e3b04bc790 drma/dmgpu: move cg and pg flags into shared headers
So they can be used by powerplay.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:47 -05:00
Alex Deucher b118af7012 drm/amdgpu: remove unused cg defines
Leftover from radeon.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:47 -05:00
Alex Deucher 08d3340876 drm/amdgpu: add a cgs interface to fetch cg and pg flags
Needed to pass the cg and pg info to powerplay.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:46 -05:00
Alex Deucher f997e6f213 drm/amd/powerplay/tonga: disable vce pg
Not working reliably yet.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:46 -05:00
Alex Deucher 3d5afb41f8 drm/amd/powerplay/tonga: disable uvd pg
Not working reliably yet.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:45 -05:00
Alex Deucher 67a0a0fd11 drm/amd/powerplay/cz: disable vce pg
Not working reliably yet.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:45 -05:00
Alex Deucher d4fdc08e25 drm/amd/powerplay/cz: disable uvd pg
Not working reliably yet.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:44 -05:00
Alex Deucher 35e5912d08 drm/amdgpu: be consistent with uvd cg flags
Don't do anything if the uvd cg flags are not set.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:44 -05:00
Alex Deucher 0fd4af9e32 drm/amdgpu: clean up vce pg flags for cz/st
It was already disabled elsewhere, make it offical.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:43 -05:00
Alex Deucher 808a934fd4 drm/amdgpu: handle vce pg flags properly
Don't attempt to start/stop the vce block if pg is disabled.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:43 -05:00
Alex Deucher b6df77fc5c drm/amdgpu: handle uvd pg flags properly
Don't attempt to start/stop the uvd block if pg is disabled.

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:42 -05:00
Alex Deucher 50171ebecf drm/amdgpu/dpm/ci: switch over to the common pcie caps interface
We already query this at driver init, so use that info.  Also
handles virtualization cases.

Reviewed-by: monk liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:42 -05:00
Alex Deucher 76ecb2c75b drm/amdgpu/cik: don't mess with aspm if gpu is root bus
Pcie registers may not be available in a virtualized
environment.

Reviewed-by: monk liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:41 -05:00
Alex Deucher cd474ba0d6 drm/amdgpu: add pcie cap module parameters (v2)
Allows the user to force the supported pcie gen and lane
config on both the asic and the chipset.
Useful for debugging pcie problems and for virtualization
where we may not be able to query the pcie bridge caps.

Default to:
gen: chipset 1/2, asic 1/2/3
lanes: 1/2/4/8/16

v2: fix bare metal case

Reviewed-by: monk liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08 10:37:41 -05:00
Dave Airlie 6739b3d7bc Merge branch 'drm-fixes-mst' of git://people.freedesktop.org/~airlied/linux into drm-fixes
displayport multistream fixes from AMD.

* 'drm-fixes-mst' of git://people.freedesktop.org/~airlied/linux:
  drm/dp/mst: deallocate payload on port destruction
  drm/dp/mst: Reverse order of MST enable and clearing VC payload table.
  drm/dp/mst: move GUID storage from mgr, port to only mst branch
  drm/dp/mst: change MST detection scheme
  drm/dp/mst: Calculate MST PBN with 31.32 fixed point
  drm: Add drm_fixp_from_fraction and drm_fixp2int_ceil
  drm/mst: Add range check for max_payloads during init
  drm/mst: Don't ignore the MST PBN self-test result
  drm: fix missing reference counting decrease
2016-02-05 15:24:17 +10:00
Mykola Lysenko 91a25e4631 drm/dp/mst: deallocate payload on port destruction
This is needed to properly deallocate port payload
after downstream branch get unplugged.

In order to do this unplugged MST topology should
be preserved, to find first alive port on path to
unplugged MST topology, and send payload deallocation
request to branch device of found port.

For this mstb and port kref's are used in reversed
order to track when port and branch memory could be
freed.

Added additional functions to find appropriate mstb
as described above.

Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-02-05 15:23:49 +10:00
Andrey Grodzovsky c175cd16df drm/dp/mst: Reverse order of MST enable and clearing VC payload table.
On DELL U3014 if you clear the table before enabling MST it sometimes
hangs the receiver.

Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-02-05 15:23:49 +10:00
Hersen Wu 5e93b8208d drm/dp/mst: move GUID storage from mgr, port to only mst branch
Previous implementation does not handle case below: boot up one MST branch
to DP connector of ASIC. After boot up, hot plug 2nd MST branch to DP output
of 1st MST, GUID is not created for 2nd MST branch. When downstream port of
2nd MST branch send upstream request, it fails because 2nd MST branch GUID
is not available.

New Implementation: only create GUID for MST branch and save it within Branch.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-02-05 15:23:49 +10:00