Pull clk fix from Stephen Boyd:
"One fix for Samsung Exynos524x SoCs where recent IOMMU patches have
caused some of these clocks to turn off when they were always left on
before"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk/samsung: exynos542x: mark some clocks as critical
Some parent clocks of the Exynos542x clock blocks, which have separate
power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always
enabled to access any register related to power management unit or devices
connected to it. For the time being, until a proper solution based on
runtime PM is applied, mark those clocks as critical (instead of ignore
unused or even no flags) to prevent disabling them.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> [Exynos5800 Peach Pi Chromebook]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull clk fixes from Stephen Boyd:
"One fix for a broken driver on Renesas RZ/A1 SoCs with bootloaders
that don't turn all the clks on and another fix for stm32f4 SoCs where
we have multiple drivers attaching to the same DT node"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method
clk: renesas: mstp: Support 8-bit registers for r7s72100
Clock and reset controller use same compatible strings (same IP).
Since commit 989eafd0b6 ("clk: core: Avoid double initialization of
clocks") the OF core flags clock controllers registered with the
CLK_OF_DECLARE() macro as OF_POPULATED, so platform devices with the same
compatible string will not be registered.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The RZ/A1 is different than the other Renesas SOCs because the MSTP
registers are 8-bit instead of 32-bit and if you try writing values as
32-bit nothing happens...meaning this driver never worked for r7s72100.
Fixes: b6face404f ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull ARM updates from Russell King:
- an update for clkdev registration error detection to simplify users
- add cpu capacity parsing from DT
- support for larger cachelines found on UniPhier caches
- documentation for udelay constants
- properly tag assembly function declarations
- remove unnecessary indirection of asm/mach-types.h
- switch to syscall table based generation to simplify future additions
of system calls, along with correpsonding commit for pkey syscalls
- remove redundant sa1101 header file
- RONX protect modules when they're in the vmalloc region
* 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm:
ARM: mm: allow set_memory_*() to be used on the vmalloc region
ARM: mm: fix set_memory_*() bounds checks
ARM: 8631/1: clkdev: Detect errors in clk_hw_register_clkdev() for mass registration
ARM: 8629/1: vfp: properly tag assembly function declarations in C code
ARM: 8622/3: add sysfs cpu_capacity attribute
ARM: 8621/3: parse cpu capacity-dmips-mhz from DT
ARM: 8623/1: mm: add ARM_L1_CACHE_SHIFT_7 for UniPhier outer cache
ARM: Update mach-types
ARM: sa1100: remove SA-1101 header file
ARM: 8619/1: udelay: document the various constants
ARM: wire up new pkey syscalls
ARM: convert to generated system call tables
ARM: remove indirection of asm/mach-types.h
Pull ARM SoC platform updates from Arnd Bergmann:
"These are updates for platform specific code on 32-bit ARM machines,
essentially anything that can not (yet) be expressed using DT files.
Noteworthy changes include:
- Added support for the TI DRA71x family of SoCs in mach-omap2, this
is an new variant of the the DRA72x/DRA74x automotive infotainment
chips we already supported for a while.
- Added support for the ST STM32F746 SoC, the first Cortex-M7 based
microcontroller we support, related to the smaller STM32F4 family.
- Renesas adds support for r8a7743 and r8a7745 in mach-shmobile, see
http://elinux.org/RZ-G
- SMP is now supported on the OX820 platform
- A lot of code in mach-omap2 gets removed as a follow-up to removing
support for board files in the previous release
- Davinci has some new work to improve USB support
- For i.MX, the performance monitor now supports profiling the memory
controller using 'perf'"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (95 commits)
ARM: davinci: da830-evm: use gpio descriptor for mmc pins
ARM: davinci: da850-evm: use gpio descriptor for mmc pins
ARM: davinci: hawk: use gpio descriptor for mmc pins
ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6
ARM: davinci: da8xx: Fix ohci device name
ARM: oxnas: Add OX820 config and makefile entry
ARM: oxnas: Add OX820 SMP support
ARM: davinci: PM: fix build when da850 not compiled in
ARM: orion5x: remove legacy support of ls-chl
ARM: integrator: drop EBI access use syscon
ARM: BCM5301X: Add back handler ignoring external imprecise aborts
ARM: davinci: PM: support da8xx DT platforms
ARM: davinci: PM: cleanup: remove references to pdata
ARM: davinci: PM: rework init, remove platform device
ARM: Kconfig: Introduce MACH_STM32F746 flag
ARM: mach-stm32: Add a new SOC - STM32F746
ARM: shmobile: document SK-RZG1E board
ARM: shmobile: r8a7745: basic SoC support
ARM: imx: mach-imx6ul: add imx6ull support
ARM: zynq: Reserve correct amount of non-DMA RAM
...
Pull ARM SoC non-urgent fixes from Arnd Bergmann:
"As usual, we queue up a few fixes that don't seem urgent enough to go
in through -rc, or that just came a little too late given their size.
The zx fixes make the platform finally boot on real hardware, the
davinci and imx31 get the DT support working better for some of the
machines that are still normally used with classic board files. One
tegra fix is important for new bootloader versions, but the bug has
been around for a while without anyone noticing.
The other changes are mostly cosmetic"
* tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits)
arm64: tegra: Add missing Smaug revision
arm64: tegra: Add VDD_GPU regulator to Jetson TX1
arm64: dts: zte: clean up gic-v3 redistributor properties
arm64: dts: zx: Fix gic GICR property
bus: vexpress-config: fix device reference leak
soc: ti: qmss: fix the case when !SMP
ARM: lpc32xx: drop duplicate header device.h
ARM: ixp4xx: drop duplicate header gpio.h
ARM: socfpga: fix spelling mistake in error message
ARM: dts: imx6q-cm-fx6: fix fec pinctrl
ARM: dts: imx7d-pinfunc: fix UART pinmux defines
ARM: dts: imx6qp: correct LDB clock inputs
ARM: OMAP2+: pm-debug: Use seq_putc() in two functions
ARM: OMAP2+: Remove the omapdss_early_init_of() function
mfd: tps65217: Fix mismatched interrupt number
ARM: zx: Fix error handling
ARM: spear: Fix error handling
ARM: davinci: da850: Fix pwm name matching
ARM: clk: imx31: properly init clocks for machines with DT
clk: imx31: fix rewritten input argument of mx31_clocks_init()
...
Some driver is using this type of DT bindings for clock (more detail,
see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt).
sound_soc {
...
cpu {
clocks = <&xxx>;
...
};
codec {
clocks = <&xxx>;
...
};
};
Current driver in this case uses of_clk_get() for each node, but there
is no devm_of_clk_get() today.
OTOH, the problem of having devm_of_clk_get() is that it encourages the
use of of_clk_get() when clk_get() is more desirable.
Thus, this patch adds new devm_get_clk_from_chile() which explicitly
reads as get a clock from a child node of this device.
By this function, we can also use this type of DT bindings
sound_soc {
clocks = <&xxx>, <&xxx>;
clock-names = "cpu", "codec";
clock-ranges;
...
cpu {
...
};
codec {
...
};
};
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[sboyd@codeurora.org: Rename subject to clk + add API]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Free memory and memory mapping , if mmp2_clk_init is not successful.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
[sboyd@codeaurora.org: Put return at the right place]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
It is likely that instead of '1>64', 'q>64' was expected.
Moreover, according to datasheet,
http://www.ti.com/lit/ds/symlink/cdce925.pdf
SCAS847I - JULY 2007 - REVISED OCTOBER 2016
PLL settings limits are: 16 <= q <= 63
So change the upper limit check from 64 to 63.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The broadcom clk driver Kconfig file selects and depends on the
COMMON_CLK_IPROC config for different SoC specific drivers. Let's
simplify this by always selecting the COMMON_CLK_IPROC config,
turning it into a set of library code. We still want to retain
the SoC specific options, so we leave those in place. Since we're
here we also drop COMMON_CLK dependency because that's implicitly
handled by including this file in drivers/clk/Kconfig in the
right place and also make CLK_BCM_KONA default to y on the
architecture it exists for instead of plain default y.
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <ray.jui@broadcom.com>
Cc: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The VEC clock requires needs to be set at exactly 108MHz. Allow rate
change propagation on PLLH_AUX to match this requirement wihtout
impacting other IPs (PLLH is currently only used by the HDMI encoder,
which cannot be enabled when the VEC encoder is enabled).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Some peripheral clocks, like the VEC (Video EnCoder) clock need to be set
to a precise rate (in our case 108MHz). With the current implementation,
where peripheral clocks are not allowed to forward rate change requests
to their parents, it is impossible to match this requirement unless the
bootloader has configured things correctly, or a specific rate has been
assigned through the DT (with the assigned-clk-rates property).
Add a new field to struct bcm2835_clock_data to specify which parent
clocks accept rate change propagation, and support set rate propagation
in bcm2835_clock_determine_rate().
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
bcm2835_pll_divider_off() is resetting the divider field in the A2W reg
to zero when disabling the clock.
Make sure we preserve this value by reading the previous a2w_reg value
first and ORing the result with A2W_PLL_CHANNEL_DISABLE.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: <stable@vger.kernel.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The OMAP36xx DPLL5, driving EHCI USB, can be subject to a long-term
frequency drift. The frequency drift magnitude depends on the VCO update
rate, which is inversely proportional to the PLL divider. The kernel
DPLL configuration code results in a high value for the divider, leading
to a long term drift high enough to cause USB transmission errors. In
the worst case the USB PHY's ULPI interface can stop responding,
breaking USB operation completely. This manifests itself on the
Beagleboard xM by the LAN9514 reporting 'Cannot enable port 2. Maybe the
cable is bad?' in the kernel log.
Errata sprz319 advisory 2.1 documents PLL values that minimize the
drift. Use them automatically when DPLL5 is used for USB operation,
which we detect based on the requested clock rate. The clock framework
will still compute the PLL parameters and resulting rate as usual, but
the PLL M and N values will then be overridden. This can result in the
effective clock rate being slightly different than the rate cached by
the clock framework, but won't cause any adverse effect to USB
operation.
Signed-off-by: Richard Watts <rrw@kynesim.co.uk>
[Upported from v3.2 to v4.9]
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Linus Torvalds
Marek Szyprowski
Gabriel Fernandez
Chris Brandt
Boris Brezillon
Kuninori Morimoto
Arvind Yadav
Christophe JAILLET
Stephen Boyd
Tang Yuantian
Grygorii Strashko
Richard Watts
Pan Bian
Masahiro Yamada