35dc3f97a6
drm/i915: Give names to more ring registers
...
The logical render context population has a bunch of raw ring register
offsets. Use the names we have for them, and in cases where we we don't,
give them names.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-23-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
2015-11-18 14:35:36 +02:00
e597ef4045
drm/i915: Make the cmd parser 64bit regs explicit
...
Add defines for the upper halves of the registers used by the cmd
parser. Getting rid of the arithmetic with the register offset
will help in making registers type safe.
v2: s/_HI/_UDW/ (Chris)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
Link: http://patchwork.freedesktop.org/patch/msgid/1446839080-18732-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 14:35:20 +02:00
8697600b40
drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctl
...
Store the upper dword of the register offset in the whitelist as well.
This would allow it to read register where the two halves aren't sitting
right next to each other, and it'll make it easier to make register
access type safe.
While at it change the register offsets to u32 from u64. Our register
space isn't quite that big, yet :)
v2: Use ldw/udw as the suffixes, and add a note about
64bit wide split regs (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk >
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1446839021-18599-1-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
2015-11-18 14:35:16 +02:00
e6c4c76366
drm/i915: Parametrize MOCS registers
...
v2: Use for_each_ring() (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk >
Cc: Francisco Jerez <currojerez@riseup.net >
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1446725633-6419-1-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
2015-11-18 14:35:10 +02:00
6fa1c5f1a7
drm/i915: Parametrize L3 error registers
...
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-15-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
2015-11-18 14:35:06 +02:00
086f8e84a0
drm/i915: Prefix raw register defines with underscore
...
Most of our register defines follow the convention that if there's a
need for the raw register offset, that one has an underscore sa a
prefix. The define (possibly parametrized) without the underscore is
the one people should normally use, since it will take into account
all the parameters and other potential offsets that are needed.
Fix up the few stragglers that don't follow this convention.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-14-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
2015-11-18 14:35:02 +02:00
9f836f9016
drm/i915/gen9: Turn DC handling into a power well
...
Handle DC off as a power well where enabling the power well will prevent
the DMC to enter selected DC states (required around modesets and Aux
A). Disabling the power well will allow DC states again. For now the
highest DC state is DC6 for Skylake and DC5 for Broxton but will be
configurable for Skylake in a later patch.
v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
v3:
- Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
- Add PW2 dependency to DC_OFF (Imre)
v4: Put DC_OFF before PW2 in BXT power well array
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Reviewed-by: Imre Deak <imre.deak@intel.com >
[fixed line over 80 and parenthesis alignment checkpatch warns (imre)]
Link: http://patchwork.freedesktop.org/patch/msgid/1447687201-24759-1-git-send-email-patrik.jakobsson@linux.intel.com
2015-11-17 20:55:20 +02:00
cd02ac52eb
drm/i915: Explain usage of power well IDs vs bit groups
...
v2: Add explanation of the fixed power well bits (Imre)
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Reviewed-by: Imre Deak <imre.deak@intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1447682467-6237-2-git-send-email-patrik.jakobsson@linux.intel.com
2015-11-17 20:55:20 +02:00
13ae3a0d5b
drm/i915/gen9: simplify DC toggling code
...
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
[fix line over 80 chars checkpatch WARN in gen9_set_dc_state() (imre)]
Link: http://patchwork.freedesktop.org/patch/msgid/1446657859-9598-8-git-send-email-imre.deak@intel.com
2015-11-17 20:55:15 +02:00
56fcfd6333
drm/i915: fix the power well ID for always on wells
...
lookup_power_well() expects uniq power well IDs, but atm we have
uninitialized IDs which would clash with those power wells with a 0
ID. This wasn't a problem so far since nothing looked up such a power
well, but an upcoming patch will (Misc IO for SKL), so fix this up on
platforms where this matters.
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1446657859-9598-2-git-send-email-imre.deak@intel.com
2015-11-17 19:38:55 +02:00
443a389f43
drm/i915: Add dev_priv->psr_mmio_base
...
Drop the EDP_PSR_BASE() thing, and just stick the PSR register offset
under dev_priv, like we for DSI and GPIO for example.
TODO: could probably move a bunch of this kind of stuff into the device
info instead...
v2: Drop the spurious whitespace change (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1447266856-30249-7-git-send-email-ville.syrjala@linux.intel.com
2015-11-16 16:01:30 +02:00
da00bdcfb2
drm/i915: Remove the magic AUX_CTL is at DP + foo tricks
...
Currently we determine the location of the AUX registers in a confusing
way. First we assume the PCH registers are used always, but then we
override it for everything but HSW/BDW to use DP+0x10. Very confusing.
Let's just make it straightforward and simply add a few functions to
pick the right AUX_CTL based on the DP port.
To deal with VLV/CHV we'll include the display_mmio_offset into the
AUX register defines.
v2: Reorder patches (Chris)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk > (v1)
Link: http://patchwork.freedesktop.org/patch/msgid/1447266856-30249-5-git-send-email-ville.syrjala@linux.intel.com
2015-11-16 16:00:34 +02:00
750a951fd3
drm/i915: Parametrize AUX registers
...
v2: Keep some MISSING_CASE() stuff (Jani)
s/-1/-PIPE_B/ in the register macro
Fix typo in patch subject
v3: Use PORT_B registers for invalid ports in g4x_aux_ctl_reg() (Jani)
v4: Reorder patches (Chris)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: Jani Nikula <jani.nikula@intel.com > (v3)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk > (v3)
Link: http://patchwork.freedesktop.org/patch/msgid/1447266856-30249-4-git-send-email-ville.syrjala@linux.intel.com
2015-11-16 16:00:14 +02:00
b377e0df11
drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/
...
The DP link frequency is 162MHz, not 160MHz. Rename the ILK eDP PLL
defines to match.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1446146763-31821-11-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch >
2015-11-10 16:23:42 +02:00
6fb403de36
drm/i915: Add csr programming registers to dmc debugfs entry
...
We check these to determine firmware loading status. Include
them to help to debug causes of firmware loading fails.
v2: Move all CSR specific registers to i915_reg.h (Ville)
v3: Rebase
v4: Rebase (RPM ref)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com >
Reviewed-by: Imre Deak <imre.deak@intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1446220487-32691-1-git-send-email-mika.kuoppala@intel.com
Tested-by: Daniel Stone <daniels@collabora.com > # SKL
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
2015-11-09 19:16:19 +02:00
16e11b9946
drm/i915/bxt: Expose DC5 entry count
...
For bxt CSR firmware exposes a count of dc5 entries. Expose
it through debugs
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com >
Reviewed-by: Imre Deak <imre.deak@intel.com >
Tested-by: Daniel Stone <daniels@collabora.com > # SKL
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
2015-11-09 19:15:32 +02:00
8337206d3b
drm/i915/skl: Expose DC5/DC6 entry counts
...
The CSR firmware expose two counters, handy to check if we are indeed
entering DC5/DC6.
v2: Rebase
v3: Take RPM ref before reading (Imre)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com >
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com > (v1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com >
Reviewed-by: Imre Deak <imre.deak@intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1446220412-32574-1-git-send-email-mika.kuoppala@intel.com
Tested-by: Daniel Stone <daniels@collabora.com > # SKL
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
2015-11-09 19:15:16 +02:00
f1b391a551
drm/i915/skl: While sanitizing cdclock check the SWF18 as well
...
SWF18 is set if the display has been initialized by the pre-os. It also
gives what configuration is enabled on which pipe. In skl_sanitize_cdclk,
the DPLL sanity check can pass even if GOP/VBIOS is not loaded as BIOS
enables DPLL for integrated audio codec related programming.
So fisrt check if SWF18 is set and then follow through with other DPLL
and CDCLK verification. If not set then for sure we need to sanitize the
cdclock.
v2: Update the commit message for clarity (Siva)
v3: Correct the mask to check for bits[23:0] instead of only bits[16:0].
Had missed checking for PIPE C altogether. Remaining are reserved (Siva)
v4: Use ILK_SWF macro for SWF register definitions. Taken from Ville's patch
http://lists.freedesktop.org/archives/intel-gfx/2015-November/079480.html
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com >
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com >
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com >
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1446726932-14078-1-git-send-email-shobhit.kumar@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
2015-11-05 15:02:58 +02:00
01403de3c0
drm/i915: Use paramtrized WRPLL_CTL()
...
v2: Rebase due to SKL_DPLLx usage
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1442595836-23981-21-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
2015-10-26 16:33:37 +02:00
85fa792bee
drm/i915: Parametrize and fix SWF registers
...
Parametrize the SWF registers. This also fixes the register offsets,
which were mostly garbage in the old defines.
Also save/restore only as many SWF registers that each platform has.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
2015-10-13 13:20:38 +02:00
fd8f507c0d
drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.
...
The PIPE_FRMCOUNT_GM45 and PIPE_FLIPCOUNT_GM45 names have bothered me
for a long time. The work equally well for ELK and onwards, so let's
s/GM45/G4X/.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
2015-10-13 13:20:01 +02:00
395b2913e3
drm/i915: Fix a few bad hex numbers in register defines
...
A few register mask defines were missing the '0x' from hex numbers. Or
at least I assume those were meant to be hex numbers. Put the '0x' in
place.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
2015-10-13 13:19:22 +02:00
68d9753837
drm/i915: Protect register macro arguments
...
Always put parens around macro argument evaluations.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
2015-10-13 13:16:19 +02:00
699fc401da
drm/i915: Include gpio_mmio_base in GMBUS reg defines
...
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
2015-10-13 13:16:09 +02:00
436c6d4a14
drm/i915: Parametrize HSW video DIP data registers
...
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
2015-10-13 13:15:50 +02:00
Ville Syrjälä
Patrik Jakobsson
Imre Deak
Mika Kuoppala
Damien Lespiau
Shobhit Kumar