Commit Graph

67 Commits

Author SHA1 Message Date
Andy Fleming 1347a2c1eb [POWERPC} Add oprofile support for e300
The e300 c3 and c4 variants support hardware performance monitor counters
which are identical to those found in the e500.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-02-05 23:37:58 -06:00
Andy Fleming 39aef685af [POWERPC] Made FSL Book-E PMC support more generic
Some of the more recent e300 cores have the same performance monitor
implementation as the e500.  e300 isn't book-e, so the name isn't
really appropriate.  In preparation for e300 support, rename a bunch
of fsl_booke things to say fsl_emb (Freescale Embedded Performance Monitors).

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-02-05 23:34:14 -06:00
Sean MacLennan 3f8fc3e0c7 [POWERPC] 4xx: Add PowerPC 440EP Rev C
This adds the 440EP revision C PVR to the CPU table.  The chip has an
FPU on it, so we also match the logical PVR

Signed-off-by: Sean MacLennan <smaclennan@pikatech.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2008-01-25 07:08:27 -06:00
Stefan Roese b676d84e72 [POWERPC] 4xx: Add 405EXr to cputable
This patch adds the 405EXr to the powerpc cuptable. Basically the 405EXr
is a 405EX with only one EMAC and only one PCIe interface.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2008-01-25 07:06:09 -06:00
Josh Boyer e3e414bcc2 [POWERPC] Conditionally compile e200 and e500 platforms in cputable
The e200 and e500 platforms are separated in various parts of the kernel with
ifdefs, most notably reg_booke.h and traps.c.  The new machine_check rework
requires them to be similarly separated in cputable.c to avoid compile errors.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-12-24 08:44:47 -06:00
Valentine Barshak b2be3b1529 [POWERPC] 4xx: Correct 440GRx machine_check callback
Correct the PowerPC 440GRx machine check callback.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-12-23 13:26:10 -06:00
Benjamin Herrenschmidt 47c0bd1ae2 [POWERPC] Reworking machine check handling and Fix 440/440A
This adds a cputable function pointer for the CPU-side machine
check handling. The semantic is still the same as the old one,
the one in ppc_md. overrides the one in cputable, though
ultimately we'll want to change that so the CPU gets first.

This removes CONFIG_440A which was a problem for multiplatform
kernels and instead fixes up the IVOR at runtime from a setup_cpu
function. The "A" version of the machine check also tweaks the
regs->trap value to differenciate the 2 versions at the C level.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-12-23 13:11:59 -06:00
Li Yang a58d52443f [POWERPC] add e300c4 entry to cputable
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 13:57:17 -06:00
Valentine Barshak d1dfc35d3a [POWERPC] 4xx: Workaround for the 440EP(x)/GR(x) processors identical PVR issue.
PowerPC 440EP(x) 440GR(x) processors have the same PVR values, since
they have identical cores. However, FPU is not supported on GR(x) and
enabling APU instruction broadcast in the CCR0 register (to enable FPU)
may cause unpredictable results. There's no safe way to detect FPU
support at runtime. This patch provides a workarund for the issue.

We use a POWER6 "logical PVR approach". First, we identify all EP(x)
and GR(x) processors as GR(x) ones (which is safe). Then we check
the device tree cpu path. If we have a EP(x) processor entry,
we call identify_cpu again with PVR | 0x8. This bit is always 0
in the real PVR. This way we enable FPU only for 440EP(x).

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-11-01 07:13:43 -05:00
Stefan Roese 5d8476c8fa [POWERPC] 4xx: Add AMCC 405EX support to cputable.c
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-10-11 15:01:22 -05:00
Paul Mackerras 87a72f9e17 [POWERPC] Fix performance monitor on machines with logical PVR
Some IBM machines supply a "logical" PVR (processor version register)
value in the device tree in the cpu nodes rather than the real PVR.
This is used for instance to indicate that the processors in a POWER6
partition have been configured by the hypervisor to run in POWER5+
mode rather than POWER6 mode.  To cope with this, we call identify_cpu
a second time with the logical PVR value (the first call is with the
real PVR value in the very early setup code).

However, POWER5+ machines can also supply a logical PVR value, and use
the same value (the value that indicates a v2.04 architecture
compliant processor).  This causes problems for code that uses the
performance monitor (such as oprofile), because the PMU registers are
different in POWER6 (even in POWER5+ mode) from the real POWER5+.

This change works around this problem by taking out the PMU
information from the cputable entries for the logical PVR values, and
changing identify_cpu so that the second call to it won't overwrite
the PMU information that was established by the first call (the one
with the real PVR), but does update the other fields.  Specifically,
if the cputable entry for the logical PVR value has num_pmcs == 0,
none of the PMU-related fields get used.

So that we can create a mixed cputable entry, we now make cur_cpu_spec
point to a single static struct cpu_spec, and copy stuff from
cpu_specs[i] into it.  This has the side-effect that we can now make
cpu_specs[] be initdata.

Ultimately it would be good to move the PMU-related fields out to a
separate structure, pointed to by the cputable entries, and change
identify_cpu so that it saves the PMU info pointer, copies the whole
structure, and restores the PMU info pointer, rather than identify_cpu
having to list all the fields that are *not* PMU-related.

Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2007-10-11 21:37:50 +10:00
Valentine Barshak 340ffd267c [POWERPC] 4xx: 440EPx/GRx incorrect write to DDR SDRAM errata workaround
Add a workaround for PowerPC 440EPx/GRx incorrect write to
DDR SDRAM errata. Data can be written to wrong address
in SDRAM when write pipelining enabled on plb0. We disable
it in the cpu_setup for these processors at early init.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-10-03 07:20:18 -05:00
Valentine Barshak 8112753bb2 [POWERPC] 4xx: Move 440EP(x) FPU setup from head_44x to cpu_setup_4xx
The PowerPC 440EP(x) FPU init is currently done in head_44x
under ifdefs. Since we should support more then one board
in the same kernel, we move FPU initialization code from head_44x
to cpu_setup_44x and add cpu_setup callbacks for 440EP(x).

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-10-03 07:20:17 -05:00
Valentine Barshak 84e3ad5b91 [POWERPC] 4xx: Introduce cpu_setup functionality to 44x platform
This adds cpu_setup functionality for ppc44x platform.
Low level cpu-spefic initialization routines should be
placed in cpu_setup_44x.S and a callback should be
added to cputable. The cpu_setup is invoked
by identify_cpu() function at early init.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-10-03 07:20:17 -05:00
Kumar Gala 5e14d21e3f [POWERPC] Add cpu feature for SPE handling
Make it so that SPE support can be determined at runtime.  This is similiar
to how we handle AltiVec.  This allows us to have SPE support built in and
work on processors with and without SPE.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-14 08:53:30 -05:00
Valentine Barshak 15fc993e31 [POWERPC] PowerPC 440EPx: Sequoia board support
AMCC PPC440EPx Sequoia board support.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2007-09-07 07:49:13 -05:00
Mike Wolf 31a12cece7 [POWERPC] Oprofile support for Power 5++
This adds a new oprofile cpu type for Power 5 revision 3 chips.
The new name is ppc64/power5++ and is used so that the performance
counters can be set up correctly.

Signed-off-by: Mike Wolf <mjw@us.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-07-11 13:21:46 +10:00
Roland Dreier 333e615483 [POWERPC] Add cputable entry for PowerPC 440SPe Rev. B
When adding the cputable entry for 440SPe Rev. B, we also need to
adjust the existing entries for 440SP Rev. A and 440SPe Rev. B so that
they look more bits of the PVR.  The 440SPe Rev. B has PVR 53421891,
which would match the current 440SP Rev. A pattern of 53xxx891.  To
distinguish between 440SP and 440SPe, we need to use the first three
digits of the PVR, which are respectively 532 and 534.

Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-07-10 21:53:44 +10:00
Anton Blanchard 2fae4985a1 [POWERPC] Add missing pmc_type fields in cpu_table
A number of cpu_table entries were missing the pmc_type field,
which means that the sysfs entries for the performance monitor
counters don't get created.  This adds them.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-05-22 20:20:56 +10:00
James.Yang 3d372548b4 [POWERPC] Remove CPU_FTR_NEED_COHERENT for 7448.
Remove CPU_FTR_NEED_COHERENT for MPC7448 (and single-core MPC86xx).
This prevents needlessly setting M=1 when not SMP.

Signed-off-by: James.Yang <James.Yang@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-05-17 21:10:15 +10:00
Olof Johansson 25fc530eed [POWERPC] pasemi: PA6T oprofile support
Oprofile support for PA6T, kernel side.

Also rename the PA6T_SPRN.* defines to SPRN_PA6T.*.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-04-24 21:31:51 +10:00
Josh Boyer a14c4508f4 [POWERPC] Fix PowerPC 750CL and 750GX CPU features
PowerPC 750CL has high BATs.  The patch below adds a CPU_FTRS_750CL that
includes that.  Without it, the original firmware mappings in the high BATs
aren't cleared which continue to override the linux translations.

It also adds CPU_FTR_COMMON to CPU_FTRS_750GX for completeness.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-04-24 21:31:47 +10:00
Jake Moilanen cfbff8a380 [POWERPC] 750CL cputable entry
750CL cputable entry from Steve Winiecki.

Signed-off-by: Jake Moilanen <moilanen@austin.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-03-09 15:03:26 +11:00
Olof Johansson 3546e811f1 [POWERPC] No DEEPNAP on 970MP 1.0
970MP rev 1.0 is reported to have nonworking DEEPNAP support, we've had
bug reports of lockups on those machines. Appearantly Apple used them
on some dual-core dual-cpu systems. Rev 1.1 is OK, and that's the one
that all 4-way systems seem to use.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-03-08 04:09:32 +11:00
Stephen Rothwell 40d244d69a [POWERPC] correct a prototype
This rids us of a warning.

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-02-13 15:35:52 +11:00