Add the Cisco Powertv cable settop box to the MIPS tree. This platform is
based on a MIPS 24Kc processor with various devices integrated on the same
ASIC. There are multiple models of this box, with differing configuration
but the same kernel runs across the product line.
Signed-off-by: David VomLehn <dvomlehn@cisco.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/132/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch adds two new kernel options: CPU_SUPPORTS_CPUFREQ and
CPU_SUPPORTS_ADDRWINCFG to describe the new features of Loongons 2F and
replaces the several ugly #if clauses by them.
These two options will be utilized by the future loongson revisions and
related drivers such as the coming Loongson 2F CPUFreq driver.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Loongson 2F has built-in DDR2 and PCI-X controller. The PCI-X controller
has a programming interface similiar to the the FPGA northbridge used on
Loongson 2E.
The main differences between Loongson 2E and Loongson 2F include:
1. Loongson 2F has an extra address window configuration module, which
is used to map CPU address space to DDR or PCI address space, or map
the PCI-DMA address space to DDR or LIO address space.
2. Loongson 2F supports 8 levels of software configurable CPu frequency
which can be configured in the LOONGSON_CHIPCFG0 register. The coming
cpufreq and standby support are based on this feature.
Loongson.h abstracts the modules and corresponding methods are abstracted.
Add other Loongson-2F-specific source code including gcc 4.4 support, PCI
memory space, PCI IO space, DMA address.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
To share the same kernel image amon different machines we have added the
machtype command line support.
In the old serial port implementation the UART base address is hardcoded as
a macro in machine.h which breaks with machtype, so change that to discover
the address dynamically. Also move the initialization of the UART base
address to uart_base.c to avoid remapping twice for early_printk.c and
serial.c.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/581/
Patchwork: http://patchwork.linux-mips.org/patch/682/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
To choose code for different machines by the value of machtype it needs to
be initialized as early as possible. So move initialization of
mips_machtype to prom_init().
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
On SMP systems, the collection of statistics can cause cache line
bouncing in the lines associated with the counters. Also there are
races incrementing the counters on multiple CPUs.
To fix both problems, we collect the statistics in per-CPU variables,
and add them up in the debugfs read operation.
As a test I ran the LTP float_bessel test on a 12 CPU Octeon system.
Without CONFIG_DEBUG_FS : 2602 seconds.
With CONFIG_DEBUG_FS: 2640 seconds.
With non-cpu-local atomic statistics: 14569 seconds.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The built-in Loongson 2E/2F northbridge in is bonito64-compatible but not
identical with it. To avoid influencing the original bonito64 support and
make the loongson support more maintainable, it's better to separate the
Bonito64 code from the Loongson code.
This also prepares the kernel for the coming Loongson 2f machines family
support.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: yanh@lemote.com
Cc: huhb@lemote.com
Cc: Zhang Le <r0bertz@gentoo.org>
Cc: zhangfx@lemote.com,
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Processors that support the mips64r2 ISA can in four instructions
convert a shifted PGD pointer stored in the upper bits of c0_context
into a usable pointer. By doing this we save a memory load and
associated potential cache miss in the TLB exception handlers.
Since the upper bits of c0_context were holding the CPU number, we
move this to the upper bits of c0_xcontext which doesn't have enough
bits to hold the PGD pointer, but has plenty for the CPU number.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The Octeon SOC has two types of Ethernet ports, each type with its own
driver. However, the PHYs for all the ports are controlled by a
common MDIO bus. Because the mdio driver is not associated with a
particular driver, but is instead a system level resource, we create s
stand-alone driver for it.
As for the driver, we put the register definitions in
arch/mips/include/asm/octeon where most of the other Octeon register
definitions live. This is a platform driver with the platform device
for "mdio-octeon" being registered in the platform startup code.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The MIPS-specific macro CL_SIZE is merely aliasing the macro
COMMAND_LINE_SIZE. Other architectures use the latter; also,
COMMAND_LINE_SIZE is documented in kernel-parameters.txt, so
let's use it, and remove the alias.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Nobody is using the ARCS-specific prom_getcmdline(), so let's remove it.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The raw_spin* namespace was taken by lockdep for the architecture
specific implementations. raw_spin_* would be the ideal name space for
the spinlocks which are not converted to sleeping locks in preempt-rt.
Linus suggested to convert the raw_ to arch_ locks and cleanup the
name space instead of using an artifical name like core_spin,
atomic_spin or whatever
No functional change.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Ingo Molnar <mingo@elte.hu>
Cc: linux-arch@vger.kernel.org
Wu Zhangjin
David VomLehn
David Daney
Dmitri Vorobiev
Christoph Hellwig
Thomas Gleixner