Commit Graph

4427 Commits

Author SHA1 Message Date
Jesse Barnes 645c62a5e9 drm/i915: split PCH clock gating init
Ibex Peak and CougarPoint already require a different setting (added
here), and future chips will likely follow that precedent.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:53 -07:00
Jesse Barnes 28963a3eb5 drm/i915: add Ivybridge clock gating init function
Some of the bits have changed, including one we were setting that enables
a VGA test mode, preventing pipe B from working at all.  So add a new
IVB specific function with the right bits.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:53 -07:00
Eric Anholt 4593010b68 drm/i915: Update the location of the ringbuffers' HWS_PGA registers for IVB.
They have been moved from the ringbuffer groups to their own group it
looks like.  Fixes GPU hangs on gnome startup.

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:52 -07:00
Eric Anholt 25aebfc30b drm/i915: Add support for fence registers on Ivybridge.
The registers are the same as on Sandybridge.  Fixes scrambled display
in X when it does software drawing to the GTT, and scans the results
out as tiled.

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:51 -07:00
Eric Anholt 10ed13e4a5 drm/i915: Use existing function instead of open-coding fence reg clear.
This is once less place to miss a new INTEL_INFO(dev)->gen update now.

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:50 -07:00
Jesse Barnes 6067aaeadb drm/i915: split clock gating init into per-chipset functions
This helps contain the mess to init_display() instead.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:50 -07:00
Jesse Barnes 90711d50d0 drm/i915: set IBX pch type explicitly
This is a little less confusing than relying on the implicit zeroing of
the dev_priv.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:49 -07:00
Jesse Barnes c76b615c43 drm/i915: add Ivy Bridge PCI IDs and driver feature structs
There are several variants, set feature bits appropriately for both
mobile and desktop parts.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:48 -07:00
Jesse Barnes c792513bd1 drm/i915: add PantherPoint PCH ID
We can treat PantherPoint as CougarPoint as far as display goes.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:11:51 -07:00
Jesse Barnes 65d3eb1e06 drm/i915: ring support for Ivy Bridge
Use Sandy Bridge paths in a few places.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:10:33 -07:00
Jesse Barnes 51d56126a2 drm/i915: page flip support for Ivy Bridge
Treat Ivy Bridge like previous chips as far as flip submission is
concerned.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:10:13 -07:00
Jesse Barnes b1f14ad01a drm/i915: interrupt & vblank support for Ivy Bridge
Add new interrupt handling functions for Ivy Bridge.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:09:52 -07:00
Jesse Barnes fe100d4da1 drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
Not fully tested.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:08:31 -07:00
Jesse Barnes 357555c00f drm/i915: manual FDI training for Ivy Bridge
A0 stepping chips need to use manual training, but the bits have all
moved.  So fix things up so we can at least train FDI for VGA links.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:06:22 -07:00
Jesse Barnes 37808944e4 drm/i915: add swizzle/tiling support for Ivy Bridge
Treat it like Ironlake and Sandy Bridge.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:05:43 -07:00
Jesse Barnes eceae4817e drm/i915: Ivy Bridge has split display and pipe control
Ivy Bridge has a similar split display controller to Sandy Bridge, so
use HAS_PCH_SPLIT.  And gen7 also has the pipe control instruction, so
use HAS_PIPE_CONTROL as well.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:05:15 -07:00
Jesse Barnes 4b65177b27 drm/i915: add IS_IVYBRIDGE macro for checks
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:04:29 -07:00
Jesse Barnes 85436696fe drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later
Note: IS_GEN* are for render related checks.  Display and other checks
should use IS_MOBILE, IS_$CHIPSET or test for specific features.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:03:38 -07:00
Jesse Barnes f796cf8f51 drm/i915: split enable/disable vblank code into chipset specific functions
This makes the Ironlake+ code trivial and generally simplifies things.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:03:10 -07:00
Jesse Barnes 4697995b98 drm/i915: split irq handling into per-chipset functions
Set the IRQ handling functions in driver load so they'll just be used
directly, rather than branching over most of the code in the chipset
functions.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:02:44 -07:00
Jesse Barnes 674cf96761 drm/i915: make FDI training a display function
Rather than branching in ironlake_pch_enable, add a new train_fdi
function to the display function pointer struct and use it instead.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:02:19 -07:00
Ben Widawsky 8eb572942c drm/i915: forcewake debugfs fix
Forcewake needs to register itself with drm to use the remove function.

The file also should be read only.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 13:38:35 -07:00
Ben Widawsky 6d794d4250 drm/i915: debugfs interface for forcewake reference count
forcewake is controlled by the open and close of the debugfs file. This
assures that buggy applications cannot cause the GT to stay on forever.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:56:48 -07:00
Ben Widawsky 4912d04193 drm/i915: move gen6 rps handling to workqueue
The render P-state handling code requires reading from a GT register.
This means that FORCEWAKE must be written to, a resource which is shared
and should be protected by struct_mutex. Hence we can not manipulate
that register from within the interrupt handling and so must delegate
the task to a workqueue.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:56:47 -07:00
Ben Widawsky d1ebd816e6 drm/i915: forcewake struct mutex locking fixes
Found by the new strict checking for the mutex being held whilst
manipulating the forcewake status.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:56:47 -07:00