da6110bcbc
drm/i915/bxt: PORT_PLL_REF_SEL bit should be set for all BXT variations
...
This patch is to correct one thing in this commit:
commit 25a5670533dongwon.kim@intel.com >
Date: Wed Mar 16 18:06:13 2016 -0700
drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
This reversed bit polarity is actually common
for all BXT and APL SoCs. Therefore, revision checking
in the original commit should be removed to make
the bit set regardless of revision ID of GFX block.
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com >
Reviewed-by: Imre Deak <imre.deak@intel.com >
Signed-off-by: Imre Deak <imre.deak@intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1460673463-14453-1-git-send-email-dongwon.kim@intel.com
2016-04-15 16:10:59 +03:00
8f6d855c4b
drm/i915/bxt: Enable runtime PM
...
With the preceding fixes runtime PM should be functional, I could
runtime suspend/resume the device without problems.
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: David Weinehall <david.weinehall@intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-17-git-send-email-imre.deak@intel.com
2016-04-15 14:48:19 +03:00
f11f4e9524
Revert "drm/i915/bxt: Disable power well support"
...
With the preceding fixes power well support should be functional on
Broxton, I could enter/exit DC5 without problems.
This reverts commit 1802419957matthew.d.roper@intel.com >
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: David Weinehall <david.weinehall@intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-16-git-send-email-imre.deak@intel.com
2016-04-15 14:48:19 +03:00
adc7f04bfd
drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK
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I caught a few errors in our current PHY/CDCLK programming by sanity
checking the actual programmed state, so I thought it would be also
useful for the future. In addition to verifying the state after
programming it also verify it after exiting DC5, to make sure DMC
restored/kept intact everything related.
v2:
- Inlining __phy_reg_verify_state() doesn't make sense and also
incorrect, so don't do it (PW/CI gcc)
v3:
- Rebase on latest -nightly
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: David Weinehall <david.weinehall@intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459780030-15781-1-git-send-email-imre.deak@intel.com
2016-04-15 14:48:19 +03:00
bd48006178
drm/i915/bxt: Don't reprogram an already enabled DDI PHY
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If BIOS has already programmed and enabled a PHY, don't reprogram it as
that may interfere with the currently active outputs. A follow-up patch
will add state verification, so we can catch any misconfiguration on
BIOS's behalf.
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-14-git-send-email-imre.deak@intel.com
2016-04-15 14:48:18 +03:00
c2e001ef84
drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK
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When determining whether CDCLK is enabled by BIOS and so we should skip
reprogramming it, we didn't check the related DBUF power request and
state. In theory BIOS could enable one without the other so check for
this case and reprogram things if something is amiss.
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-13-git-send-email-imre.deak@intel.com
2016-04-15 14:48:18 +03:00
d7d7c9ee69
drm/i915/bxt: Don't toggle power well 1 on-demand
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Power well 1 is managed by the DMC firmware so don't toggle it on-demand
from the driver. This means we need to follow the BSpec display
initialization sequence during driver loading and resuming (both system
and runtime) and enable power well 1 only once there. Afterwards DMC
will toggle power well 1 whenever entering/exiting DC5.
For this to work we also need to do away getting the PLL power domain,
since that just kept runtime PM disabled for good.
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-12-git-send-email-imre.deak@intel.com
2016-04-15 14:48:18 +03:00
d7d33fd85a
drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit
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The power-down step logically belongs to the individual PHY uninit
sequence so move it there. The only functional change is that we will
power down now PHY 1 separately before PHY 0 and preserve the other bits
in the register which are defined as reserved.
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-11-git-send-email-imre.deak@intel.com
2016-04-15 14:48:17 +03:00
c6c4696fa5
drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers
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For internal APIs passing dev_priv is preferred to reduce indirections,
so convert over a few DDI PHY, CDCLK helpers.
No functional change.
Signed-off-by: Imre Deak <imre.deak@intel.com >
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Reviewed-by: David Weinehall <david.weinehall@intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-10-git-send-email-imre.deak@intel.com
2016-04-15 14:48:17 +03:00
443a93ac89
drm/i915/skl: Unexport skl_pw1_misc_io_init
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On Broxton we need to enable/disable power well 1 during the init/unit
display sequence similarly to Skylake/Kabylake. The code for this will
be added in a follow-up patch, but to prepare for that unexport
skl_pw1_misc_io_init(). It's a simple function called only from a single
place and having it inlined in the Skylake display core init/unit
functions will make it easier to compare it with its Broxton
counterpart.
This also flips the order of Misc IO and power well 1 disabling which
matches the enabling order. The specification doesn't prescribe the
disabling order, so this should be fine.
v2:
- Fix incorrect enable vs. disable power well call in
skl_display_core_uninit() (Patrik)
- Add commit comment about chaning the order of PW1 and Misc IO power
well disabling (Patrik)
CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459773777-10701-1-git-send-email-imre.deak@intel.com
2016-04-15 14:47:51 +03:00
a7c8125f46
drm/i915/bxt: Suspend power domains during suspend-to-idle
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On SKL/KBL suspend-to-idle (aka freeze/s0ix) is performed with DMC
firmware assistance where the target display power state is DC6. On
Broxton on the other hand we don't use the firmware for this, but rely
instead on a manual DC9 flow. For this we have to uninitialize the
display following the BSpec display uninit sequence, just as during
S3/S4, so make sure we follow this sequence.
CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-8-git-send-email-imre.deak@intel.com
2016-04-15 14:46:54 +03:00
bfcdabe888
drm/i915/gen9: Fix DMC/DC state asserts
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The display power well support and DC state management doesn't depend on
runtime PM support, so remove the incorrect asserts about this.
Also Broxton does support DC5, so the related assert in
assert_can_enable_dc5() is incorrect. There is a more generic and
correct assert for this already in gen9_set_dc_state(), so we can remove
all the other ones.
At the same time convert WARNs to WARN_ONCE for consistency with the
other DC state asserts.
CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-7-git-send-email-imre.deak@intel.com
2016-04-15 14:46:53 +03:00
1d963afae1
drm/i915/gen9: Make power well disabling synchronous
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So far we only power well enabling was synchronous not disabling. Since
we don't exactly know how the firmware (both DMC and PCU) synchronizes
against the actual power well state during DC transitions, make the
disabling also synchronous.
CC: Mika Kuoppala <mika.kuoppala@linux.intel.com >
CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-6-git-send-email-imre.deak@intel.com
2016-04-15 14:46:53 +03:00
c6782b76d3
drm/i915/gen9: Reset secondary power well requests left on by DMC/KVMR
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DMC forces on power well 1 and the misc IO power well by setting the
corresponding request bits both in the BIOS and the DEBUG power well
request registers. This is somewhat unexpected since the firmware should
really just save and restore state but not alter it. We also depend on
being able to disable power well 1, and the misc IO power well before
entering S3/S4 on BXT and SKL or entering DC9 on BXT. To fix this make
sure these request bits are cleared whenever we want to disable the
given power wells.
On SKL there is another twist where the firmware also clears the power
well 1 request bit in HSW_POWER_WELL_DRIVER (but not that of the misc IO
power well). This happens to not cause a problem due to the forced-on
request bits in the other request registers.
I've filed a bug about all this, but fixing that may take a while and
having this sanity check in place makes sense even for future firmware
versions.
At the same time also check the KVMR request bits. I haven't seen this
being altered, but we don't expect any request bits in here either, so
sanitize this register as well.
v2:
- Apply the workaround on SKL as well. I noticed the related failure
from the CI report, later Patrik also reported seeing it on his
machine.
CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459851965-6137-1-git-send-email-imre.deak@intel.com
2016-04-15 14:44:54 +03:00
28ca6931f0
drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only
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This register is read-only, so we have never actually set
OCL2_LDOFUSE_PWR_DIS in it as specified by the specification. Add a code
comment about this. I filed a specification update request to clarify
this there.
CC: Arthur J Runyan <arthur.j.runyan@intel.com >
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: David Weinehall <david.weinehall@intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-4-git-send-email-imre.deak@intel.com
2016-04-15 14:19:52 +03:00
d1e082ffb8
drm/i915/bxt: Fix GRC code register field definitions
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This has been corrected in BSpec quite some time ago, but we missed it
somehow. The wrong field definitions resulted in configuring PHY0 with
an incorrect GRC value.
v2:
- Remove the FIXME comment, we left in the code exactly about this
issue. (Ville)
CC: Arthur J Runyan <arthur.j.runyan@intel.com >
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-3-git-send-email-imre.deak@intel.com
2016-04-15 14:18:16 +03:00
e7968531f8
drm/i915/bxt: Reject DMC firmware versions with known bugs
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DMC version 1.06 has a known bug, where the firmware polls forever for a
port PLL to lock, if the PLL was disabled when entering DC5, which locks
up the machine. Version 1.07 fixes this, so make that the minimum
required version on BXT.
CC: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-2-git-send-email-imre.deak@intel.com
2016-04-15 14:12:35 +03:00
560ce1dc7c
drm/i915: use drm_crtc_send_vblank_event()
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Replace the legacy drm_send_vblank_event() with the new helper function.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
Link: http://patchwork.freedesktop.org/patch/msgid/1460656118-16766-4-git-send-email-gustavo@padovan.org
2016-04-15 09:42:17 +02:00
3d7d0c85e4
drm/i915: Use fw_domains_put_with_fifo() on HSW
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HSW still has the wake FIFO, so let's check it.
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com >
Cc: Deepak S <deepak.s@linux.intel.com >
Fixes: 05a2fb157eville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1460633942-24013-1-git-send-email-ville.syrjala@linux.intel.com
Cc: stable@vger.kernel.org
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com >
2016-04-14 15:02:16 +03:00
e30e251acc
drm/i915: Split gen8_gt_irq_handler into ack+handle
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As we did on VLV, split the gt irq handling to ack and handler phases on
CHV. Leave the BDW+ codepath mostly intact for now.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1460571598-24452-13-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
2016-04-14 14:46:00 +03:00
261e40b8b7
drm/i915: Eliminate passing dev+dev_priv to {snb,ilk}_gt_irq_handler()
...
It looks silly to pass both dev and dev_priv to the snb/ilk gt irq
handlers. Just pass dev_priv.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1460571598-24452-12-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch >
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
2016-04-14 14:45:49 +03:00
528948745f
drm/i915: Move gt/pm irq handling out from irq disabled section on VLV
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No need to actually handle the GT/PM interrupt while we have interrupt
sources disabled. Move the actual processing to happen after we've
restored VLV_IER and master interrupt enable.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1460571598-24452-11-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
2016-04-14 14:45:45 +03:00
2ecb8ca4a0
drm/i915: Split VLV/CVH PIPESTAT handling into ack+handler
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Minimize the amount of stuff we do with interrupt sources disabled by
splitting the PIPESTAT irq handling into ack+handler phases.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1460571598-24452-10-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
2016-04-14 14:45:42 +03:00
1ae3c34c09
drm/i915: Split PORT_HOTPLUG_STAT ack out from i9xx_hpd_irq_handler()
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Split the VLV/CHV hoplug irq handling to ack and handler phases. This
way we can move the actual irq handling outside the section where
we have disabled the interrupt sources.
For now, we leave things as is for pre-VLV GMCH platforms, but
eventually they could get the same treatment.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1460571598-24452-9-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
2016-04-14 14:45:37 +03:00
6e814800a2
drm/i915: Move variables to narrower scope in VLV/CHV irq handlers
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Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: http://patchwork.freedesktop.org/patch/msgid/1460571598-24452-8-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk >
2016-04-14 14:45:33 +03:00
Dongwon Kim
Imre Deak
Gustavo Padovan
Ville Syrjälä