Add PCI ID and detection for 5709 copper and SerDes chips.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This updated patch adds the Intel ICH9 LPC and SMBus Controller DID's.
Signed-off-by: Jason Gaston <jason.d.gaston@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
It was obesrved that at least one older PCI card predating the
requirement for the TRDY signal to respond within 16 clock ticks actually
does not meet this rule nor even the power-on defaults of the PCI bridges
found in development systems built around the Broadcom SiByte SOCs. Here
is a patch that bumps up the timeout to the highest finite value supported
by these chips, which is 255 clock ticks. The bridges affected are the
SiByte SOC itself and the SP1011.
This change does not effectively affect systems only having PCI option
cards installed that meet the TRDY requirement of the current PCI spec.
The rule was introduced with PCI 2.1, so any older card may make the
system affected. If this is the case, performance of the system will
suffer in return for the card working at all. If this is a concern, then
the solution is not to use such cards.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
with byte enables disabled on the unused 32-bit word. This is legal
but causes problems on the AMD 8132 which will eventually stop
responding after a while.
Without this patch, the MSI test done by the driver during open will
pass, but MSI will eventually stop working after a few MSIs are
written by the device.
AMD believes this incompatibility is unique to the 5706, and
prefers to locally disable MSI rather than globally disabling it
using pci_msi_quirk.
Update version to 1.4.45.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add support for the new 5709 device. This is a new 10/100 Mbps chip.
The mailbox access and firmware interface are quite different from
all other tg3 chips.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add support for the temperature sensor(s) found in AMD K8 CPUs.
Signed-off-by: Rudolf Marek <r.marek@sh.cvut.cz>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Introduce msi_ht_cap_enabled() to check the MSI capability in the
Hypertransport configuration space.
It is used in a generic quirk quirk_msi_ht_cap() to check whether
MSI is enabled on hypertransport chipset, and a nVidia specific quirk
quirk_nvidia_ck804_msi_ht_cap() where two 2 HT MSI mappings have to
be checked.
Both quirks set the PCI_BUS_FLAGS_NO_MSI bus flag when MSI is disabled.
Signed-off-by: Brice Goglin <brice@myri.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
New SiS south bridge device ID is 0x966.
Next coming product will be 0x968. (Will be released in Q4, this year)
We don't make any updates to the IDE controller.
Signed-off-by: David Wang <touch@sis.com>
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Patch to add VIA PCI quirk for Enhanced/Extended USB on VT8235
southbridge. It is needed in order to use EHCI/USB 2.0 with ACPI.
Without it IRQs are not routed correctly, you get an "Unlink after
no-IRQ?" error and the device is unusable.
I belive this could also be a fix for Bugzilla Bug 5835.
Signed-off-by: Mark Hindley <mark@hindley.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Here is a patch that adds support for the Instashield IS-200 2 port PCI
serial card.
Signed-off-by: Peter Horton <pdh@colonel-panic.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Unhide the SMBus controller on the Asus PU-DLS board.
This fixes bug #6763.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
arcmsr is a driver for the Areca Raid controller, a host based RAID
subsystem that speaks SCSI at the firmware level.
This patch is quite a clean up over the initial submission with
contributions from:
Randy Dunlap <rdunlap@xenotime.net>
Christoph Hellwig <hch@lst.de>
Matthew Wilcox <matthew@wil.cx>
Adrian Bunk <bunk@stusta.de>
Signed-off-by: Erich Chen <erich@areca.com.tw>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
The patch below adds support for the TI PCIxx12 CardBus controllers.
This seems to be sufficient to detect the cardbus bridge on an HP nc6320
and works with an orinoco wifi card.
Signed-off-by: Alex Williamson <alex.williamson@hp.com>
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
Michael Chan
Ayaz Abdulla
Jason Gaston
Peer Chen
Ben Collins
Yoichi Yuasa
Maciej W. Rozycki
Rudolf Marek
Linus Torvalds
Ralf Baechle
Brice Goglin
James Bottomley
David Wang
Mark Hindley
James Bottomley
Peter Horton
Jean Delvare
Erich Chen
Jeff Garzik
Pierre Ossman
Alex Williamson
Randy Dunlap